tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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arm64: cpufeature: Add FEAT_LSUI

Since Armv9.6, FEAT_LSUI introduces atomic instructions that allow
privileged code to access user memory without clearing the PSTATE.PAN
bit. Add CPU feature detection for FEAT_LSUI.

Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
[catalin.marinas@arm.com: Remove commit log references to SW_PAN]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

authored by

Yeoreum Yun and committed by
Catalin Marinas 7181f718 1f318b96

+13
+2
arch/arm64/include/asm/cpucaps.h
··· 71 71 return true; 72 72 case ARM64_HAS_PMUV3: 73 73 return IS_ENABLED(CONFIG_HW_PERF_EVENTS); 74 + case ARM64_HAS_LSUI: 75 + return IS_ENABLED(CONFIG_ARM64_LSUI); 74 76 } 75 77 76 78 return true;
+10
arch/arm64/kernel/cpufeature.c
··· 281 281 282 282 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 283 283 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), 284 + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSUI_SHIFT, 4, ID_AA64ISAR3_EL1_LSUI_NI), 284 285 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSFE_SHIFT, 4, 0), 285 286 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 286 287 ARM64_FTR_END, ··· 3170 3169 .cpu_enable = cpu_enable_ls64_v, 3171 3170 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LS64, LS64_V) 3172 3171 }, 3172 + #ifdef CONFIG_ARM64_LSUI 3173 + { 3174 + .desc = "Unprivileged Load Store Instructions (LSUI)", 3175 + .capability = ARM64_HAS_LSUI, 3176 + .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3177 + .matches = has_cpuid_feature, 3178 + ARM64_CPUID_FIELDS(ID_AA64ISAR3_EL1, LSUI, IMP) 3179 + }, 3180 + #endif 3173 3181 {}, 3174 3182 }; 3175 3183
+1
arch/arm64/tools/cpucaps
··· 48 48 HAS_LSE_ATOMICS 49 49 HAS_LS64 50 50 HAS_LS64_V 51 + HAS_LSUI 51 52 HAS_MOPS 52 53 HAS_NESTED_VIRT 53 54 HAS_BBML2_NOABORT