Merge tag 'mmc-v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

+3 -1

Documentation/devicetree/bindings/mmc/arm,pl18x.yaml

··· 95 95 PIO (polled I/O) interrupt and occurs when the FIFO needs to be 96 96 emptied as part of a bulk read from the card. Some variants have these 97 97 two interrupts wired into the same line (logic OR) and in that case 98 - only one interrupt may be provided. 98 + only one interrupt may be provided. The interrupt-names property is 99 + not used due to inconsistency of existing DTs regarding its content. 100 + deprecated: false 99 101 minItems: 1 100 102 maxItems: 2 101 103

+2 -1

Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml

··· 50 50 - const: fsl,imx8mm-usdhc 51 51 - items: 52 52 - enum: 53 + - fsl,imx8dxl-usdhc 53 54 - fsl,imx8qm-usdhc 54 55 - const: fsl,imx8qxp-usdhc 55 56 - items: 56 57 - enum: 57 - - fsl,imx8dxl-usdhc 58 58 - fsl,imx8mm-usdhc 59 59 - fsl,imx8mn-usdhc 60 60 - fsl,imx8mp-usdhc ··· 71 71 deprecated: true 72 72 - items: 73 73 - enum: 74 + - fsl,imx8dxl-usdhc 74 75 - fsl,imx8qm-usdhc 75 76 - const: fsl,imx8qxp-usdhc 76 77 - const: fsl,imx7d-usdhc

+57

Documentation/devicetree/bindings/mmc/fujitsu,sdhci-fujitsu.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mmc/fujitsu,sdhci-fujitsu.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Fujitsu/Socionext SDHCI controller (F_SDH30) 8 + 9 + maintainers: 10 + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 11 + 12 + allOf: 13 + - $ref: mmc-controller.yaml# 14 + 15 + properties: 16 + compatible: 17 + enum: 18 + - fujitsu,mb86s70-sdhci-3.0 19 + - socionext,f-sdh30-e51-mmc 20 + 21 + reg: 22 + maxItems: 1 23 + 24 + clocks: 25 + maxItems: 2 26 + 27 + clock-names: 28 + items: 29 + - const: iface 30 + - const: core 31 + 32 + resets: 33 + maxItems: 1 34 + 35 + fujitsu,cmd-dat-delay-select: 36 + type: boolean 37 + description: | 38 + Indicating that this host requires the CMD_DAT_DELAY control to be enabled 39 + 40 + unevaluatedProperties: false 41 + 42 + required: 43 + - compatible 44 + - reg 45 + - clocks 46 + - clock-names 47 + 48 + examples: 49 + - | 50 + sdhci1: mmc@36600000 { 51 + compatible = "fujitsu,mb86s70-sdhci-3.0"; 52 + reg = <0x36600000 0x1000>; 53 + bus-width = <4>; 54 + vqmmc-supply = <&vccq_sdhci1>; 55 + clocks = <&clock 2 2 0>, <&clock 2 3 0>; 56 + clock-names = "iface", "core"; 57 + };

-1

Documentation/devicetree/bindings/mmc/mmc-controller.yaml

··· 293 293 description: 294 294 SDIO only. Preserves card power during a suspend/resume cycle. 295 295 296 - # Deprecated: enable-sdio-wakeup 297 296 wakeup-source: 298 297 $ref: /schemas/types.yaml#/definitions/flag 299 298 description:

+141 -30

Documentation/devicetree/bindings/mmc/mtk-sd.yaml

··· 10 10 - Chaotian Jing <chaotian.jing@mediatek.com> 11 11 - Wenbin Mei <wenbin.mei@mediatek.com> 12 12 13 - allOf: 14 - - $ref: mmc-controller.yaml# 15 - 16 13 properties: 17 14 compatible: 18 15 oneOf: ··· 20 23 - mediatek,mt6795-mmc 21 24 - mediatek,mt7620-mmc 22 25 - mediatek,mt7622-mmc 26 + - mediatek,mt7986-mmc 23 27 - mediatek,mt8135-mmc 24 28 - mediatek,mt8173-mmc 25 29 - mediatek,mt8183-mmc ··· 46 48 description: 47 49 Should contain phandle for the clock feeding the MMC controller. 48 50 minItems: 2 49 - items: 50 - - description: source clock (required). 51 - - description: HCLK which used for host (required). 52 - - description: independent source clock gate (required for MT2712). 53 - - description: bus clock used for internal register access (required for MT2712 MSDC0/3). 54 - - description: msdc subsys clock gate (required for MT8192). 55 - - description: peripheral bus clock gate (required for MT8192). 56 - - description: AXI bus clock gate (required for MT8192). 57 - - description: AHB bus clock gate (required for MT8192). 51 + maxItems: 7 58 52 59 53 clock-names: 60 54 minItems: 2 61 - items: 62 - - const: source 63 - - const: hclk 64 - - const: source_cg 65 - - const: bus_clk 66 - - const: sys_cg 67 - - const: pclk_cg 68 - - const: axi_cg 69 - - const: ahb_cg 55 + maxItems: 7 70 56 71 57 interrupts: 72 58 description: ··· 172 190 - vmmc-supply 173 191 - vqmmc-supply 174 192 175 - if: 176 - properties: 177 - compatible: 178 - contains: 179 - const: mediatek,mt8183-mmc 180 - then: 181 - properties: 182 - reg: 183 - minItems: 2 193 + allOf: 194 + - $ref: mmc-controller.yaml# 195 + - if: 196 + properties: 197 + compatible: 198 + enum: 199 + - mediatek,mt2701-mmc 200 + - mediatek,mt6779-mmc 201 + - mediatek,mt6795-mmc 202 + - mediatek,mt7620-mmc 203 + - mediatek,mt7622-mmc 204 + - mediatek,mt7623-mmc 205 + - mediatek,mt8135-mmc 206 + - mediatek,mt8173-mmc 207 + - mediatek,mt8183-mmc 208 + - mediatek,mt8186-mmc 209 + - mediatek,mt8188-mmc 210 + - mediatek,mt8195-mmc 211 + - mediatek,mt8516-mmc 212 + then: 213 + properties: 214 + clocks: 215 + minItems: 2 216 + items: 217 + - description: source clock 218 + - description: HCLK which used for host 219 + - description: independent source clock gate 220 + clock-names: 221 + minItems: 2 222 + items: 223 + - const: source 224 + - const: hclk 225 + - const: source_cg 226 + 227 + - if: 228 + properties: 229 + compatible: 230 + contains: 231 + const: mediatek,mt2712-mmc 232 + then: 233 + properties: 234 + clocks: 235 + minItems: 3 236 + items: 237 + - description: source clock 238 + - description: HCLK which used for host 239 + - description: independent source clock gate 240 + - description: bus clock used for internal register access (required for MSDC0/3). 241 + clock-names: 242 + minItems: 3 243 + items: 244 + - const: source 245 + - const: hclk 246 + - const: source_cg 247 + - const: bus_clk 248 + 249 + - if: 250 + properties: 251 + compatible: 252 + contains: 253 + const: mediatek,mt8183-mmc 254 + then: 255 + properties: 256 + reg: 257 + minItems: 2 258 + 259 + - if: 260 + properties: 261 + compatible: 262 + contains: 263 + enum: 264 + - mediatek,mt7986-mmc 265 + then: 266 + properties: 267 + clocks: 268 + minItems: 3 269 + items: 270 + - description: source clock 271 + - description: HCLK which used for host 272 + - description: independent source clock gate 273 + - description: bus clock used for internal register access (required for MSDC0/3). 274 + - description: msdc subsys clock gate 275 + clock-names: 276 + minItems: 3 277 + items: 278 + - const: source 279 + - const: hclk 280 + - const: source_cg 281 + - const: bus_clk 282 + - const: sys_cg 283 + 284 + - if: 285 + properties: 286 + compatible: 287 + enum: 288 + - mediatek,mt8186-mmc 289 + - mediatek,mt8188-mmc 290 + - mediatek,mt8195-mmc 291 + then: 292 + properties: 293 + clocks: 294 + items: 295 + - description: source clock 296 + - description: HCLK which used for host 297 + - description: independent source clock gate 298 + - description: crypto clock used for data encrypt/decrypt (optional) 299 + clock-names: 300 + items: 301 + - const: source 302 + - const: hclk 303 + - const: source_cg 304 + - const: crypto 305 + 306 + - if: 307 + properties: 308 + compatible: 309 + contains: 310 + const: mediatek,mt8192-mmc 311 + then: 312 + properties: 313 + clocks: 314 + items: 315 + - description: source clock 316 + - description: HCLK which used for host 317 + - description: independent source clock gate 318 + - description: msdc subsys clock gate 319 + - description: peripheral bus clock gate 320 + - description: AXI bus clock gate 321 + - description: AHB bus clock gate 322 + clock-names: 323 + items: 324 + - const: source 325 + - const: hclk 326 + - const: source_cg 327 + - const: sys_cg 328 + - const: pclk_cg 329 + - const: axi_cg 330 + - const: ahb_cg 184 331 185 332 unevaluatedProperties: false 186 333

+1

Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml

··· 64 64 - enum: 65 65 - renesas,sdhi-r8a779a0 # R-Car V3U 66 66 - renesas,sdhi-r8a779f0 # R-Car S4-8 67 + - renesas,sdhi-r8a779g0 # R-Car V4H 67 68 - const: renesas,rcar-gen4-sdhi # R-Car Gen4 68 69 69 70 reg:

+3

Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml

··· 71 71 to control the clock phases, "ciu-sample" is required for tuning 72 72 high speed modes. 73 73 74 + power-domains: 75 + maxItems: 1 76 + 74 77 rockchip,default-sample-phase: 75 78 $ref: /schemas/types.yaml#/definitions/uint32 76 79 minimum: 0

+37 -32

Documentation/devicetree/bindings/mmc/sdhci-am654.yaml

··· 2 2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 3 3 %YAML 1.2 4 4 --- 5 - $id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#" 6 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 5 + $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml# 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 8 8 title: TI AM654 MMC Controller 9 9 ··· 11 11 - Ulf Hansson <ulf.hansson@linaro.org> 12 12 13 13 allOf: 14 - - $ref: mmc-controller.yaml# 14 + - $ref: sdhci-common.yaml# 15 15 16 16 properties: 17 17 compatible: 18 18 oneOf: 19 - - const: ti,am654-sdhci-5.1 20 - - const: ti,j721e-sdhci-8bit 21 - - const: ti,j721e-sdhci-4bit 22 - - const: ti,am64-sdhci-8bit 23 - - const: ti,am64-sdhci-4bit 24 - - const: ti,am62-sdhci 19 + - enum: 20 + - ti,am62-sdhci 21 + - ti,am64-sdhci-4bit 22 + - ti,am64-sdhci-8bit 23 + - ti,am654-sdhci-5.1 24 + - ti,j721e-sdhci-4bit 25 + - ti,j721e-sdhci-8bit 25 26 - items: 26 27 - const: ti,j7200-sdhci-8bit 27 28 - const: ti,j721e-sdhci-8bit ··· 50 49 - const: clk_ahb 51 50 - const: clk_xin 52 51 53 - sdhci-caps-mask: true 54 - 55 52 dma-coherent: 56 53 type: boolean 57 54 ··· 60 61 61 62 ti,otap-del-sel-legacy: 62 63 description: Output tap delay for SD/MMC legacy timing 63 - $ref: "/schemas/types.yaml#/definitions/uint32" 64 + $ref: /schemas/types.yaml#/definitions/uint32 64 65 minimum: 0 65 66 maximum: 0xf 66 67 67 68 ti,otap-del-sel-mmc-hs: 68 69 description: Output tap delay for MMC high speed timing 69 - $ref: "/schemas/types.yaml#/definitions/uint32" 70 + $ref: /schemas/types.yaml#/definitions/uint32 70 71 minimum: 0 71 72 maximum: 0xf 72 73 73 74 ti,otap-del-sel-sd-hs: 74 75 description: Output tap delay for SD high speed timing 75 - $ref: "/schemas/types.yaml#/definitions/uint32" 76 + $ref: /schemas/types.yaml#/definitions/uint32 76 77 minimum: 0 77 78 maximum: 0xf 78 79 79 80 ti,otap-del-sel-sdr12: 80 81 description: Output tap delay for SD UHS SDR12 timing 81 - $ref: "/schemas/types.yaml#/definitions/uint32" 82 + $ref: /schemas/types.yaml#/definitions/uint32 82 83 minimum: 0 83 84 maximum: 0xf 84 85 85 86 ti,otap-del-sel-sdr25: 86 87 description: Output tap delay for SD UHS SDR25 timing 87 - $ref: "/schemas/types.yaml#/definitions/uint32" 88 + $ref: /schemas/types.yaml#/definitions/uint32 88 89 minimum: 0 89 90 maximum: 0xf 90 91 91 92 ti,otap-del-sel-sdr50: 92 93 description: Output tap delay for SD UHS SDR50 timing 93 - $ref: "/schemas/types.yaml#/definitions/uint32" 94 + $ref: /schemas/types.yaml#/definitions/uint32 94 95 minimum: 0 95 96 maximum: 0xf 96 97 97 98 ti,otap-del-sel-sdr104: 98 99 description: Output tap delay for SD UHS SDR104 timing 99 - $ref: "/schemas/types.yaml#/definitions/uint32" 100 + $ref: /schemas/types.yaml#/definitions/uint32 100 101 minimum: 0 101 102 maximum: 0xf 102 103 103 104 ti,otap-del-sel-ddr50: 104 105 description: Output tap delay for SD UHS DDR50 timing 105 - $ref: "/schemas/types.yaml#/definitions/uint32" 106 + $ref: /schemas/types.yaml#/definitions/uint32 106 107 minimum: 0 107 108 maximum: 0xf 108 109 109 110 ti,otap-del-sel-ddr52: 110 111 description: Output tap delay for eMMC DDR52 timing 111 - $ref: "/schemas/types.yaml#/definitions/uint32" 112 + $ref: /schemas/types.yaml#/definitions/uint32 112 113 minimum: 0 113 114 maximum: 0xf 114 115 115 116 ti,otap-del-sel-hs200: 116 117 description: Output tap delay for eMMC HS200 timing 117 - $ref: "/schemas/types.yaml#/definitions/uint32" 118 + $ref: /schemas/types.yaml#/definitions/uint32 118 119 minimum: 0 119 120 maximum: 0xf 120 121 121 122 ti,otap-del-sel-hs400: 122 123 description: Output tap delay for eMMC HS400 timing 123 - $ref: "/schemas/types.yaml#/definitions/uint32" 124 + $ref: /schemas/types.yaml#/definitions/uint32 124 125 minimum: 0 125 126 maximum: 0xf 126 127 ··· 130 131 131 132 ti,itap-del-sel-legacy: 132 133 description: Input tap delay for SD/MMC legacy timing 133 - $ref: "/schemas/types.yaml#/definitions/uint32" 134 + $ref: /schemas/types.yaml#/definitions/uint32 134 135 minimum: 0 135 136 maximum: 0x1f 136 137 137 138 ti,itap-del-sel-mmc-hs: 138 139 description: Input tap delay for MMC high speed timing 139 - $ref: "/schemas/types.yaml#/definitions/uint32" 140 + $ref: /schemas/types.yaml#/definitions/uint32 140 141 minimum: 0 141 142 maximum: 0x1f 142 143 143 144 ti,itap-del-sel-sd-hs: 144 145 description: Input tap delay for SD high speed timing 145 - $ref: "/schemas/types.yaml#/definitions/uint32" 146 + $ref: /schemas/types.yaml#/definitions/uint32 146 147 minimum: 0 147 148 maximum: 0x1f 148 149 149 150 ti,itap-del-sel-sdr12: 150 151 description: Input tap delay for SD UHS SDR12 timing 151 - $ref: "/schemas/types.yaml#/definitions/uint32" 152 + $ref: /schemas/types.yaml#/definitions/uint32 152 153 minimum: 0 153 154 maximum: 0x1f 154 155 155 156 ti,itap-del-sel-sdr25: 156 157 description: Input tap delay for SD UHS SDR25 timing 157 - $ref: "/schemas/types.yaml#/definitions/uint32" 158 + $ref: /schemas/types.yaml#/definitions/uint32 159 + minimum: 0 160 + maximum: 0x1f 161 + 162 + ti,itap-del-sel-ddr50: 163 + description: Input tap delay for MMC DDR50 timing 164 + $ref: /schemas/types.yaml#/definitions/uint32 158 165 minimum: 0 159 166 maximum: 0x1f 160 167 161 168 ti,itap-del-sel-ddr52: 162 169 description: Input tap delay for MMC DDR52 timing 163 - $ref: "/schemas/types.yaml#/definitions/uint32" 170 + $ref: /schemas/types.yaml#/definitions/uint32 164 171 minimum: 0 165 172 maximum: 0x1f 166 173 167 174 ti,trm-icp: 168 175 description: DLL trim select 169 - $ref: "/schemas/types.yaml#/definitions/uint32" 176 + $ref: /schemas/types.yaml#/definitions/uint32 170 177 minimum: 0 171 178 maximum: 0xf 172 179 173 180 ti,driver-strength-ohm: 174 181 description: DLL drive strength in ohms 175 - $ref: "/schemas/types.yaml#/definitions/uint32" 182 + $ref: /schemas/types.yaml#/definitions/uint32 176 183 enum: 177 184 - 33 178 185 - 40 ··· 188 183 189 184 ti,strobe-sel: 190 185 description: strobe select delay for HS400 speed mode. 191 - $ref: "/schemas/types.yaml#/definitions/uint32" 186 + $ref: /schemas/types.yaml#/definitions/uint32 192 187 193 188 ti,clkbuf-sel: 194 189 description: Clock Delay Buffer Select 195 - $ref: "/schemas/types.yaml#/definitions/uint32" 190 + $ref: /schemas/types.yaml#/definitions/uint32 196 191 197 192 ti,fails-without-test-cd: 198 193 $ref: /schemas/types.yaml#/definitions/flag

+32

Documentation/devicetree/bindings/mmc/sdhci-common.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mmc/sdhci-common.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: SDHCI Controller Common Properties 8 + 9 + maintainers: 10 + - Adrian Hunter <adrian.hunter@intel.com> 11 + 12 + description: 13 + Common properties present on Secure Digital Host Controller Interface (SDHCI) 14 + devices. 15 + 16 + properties: 17 + sdhci-caps: 18 + $ref: /schemas/types.yaml#/definitions/uint64 19 + description: 20 + Additionally present SDHCI capabilities - values for SDHCI_CAPABILITIES 21 + and SDHCI_CAPABILITIES_1 registers. 22 + 23 + sdhci-caps-mask: 24 + $ref: /schemas/types.yaml#/definitions/uint64 25 + description: 26 + Masked SDHCI capabilities to remove from SDHCI_CAPABILITIES and 27 + SDHCI_CAPABILITIES_1 registers. 28 + 29 + allOf: 30 + - $ref: mmc-controller.yaml# 31 + 32 + additionalProperties: true

-32

Documentation/devicetree/bindings/mmc/sdhci-fujitsu.txt

··· 1 - * Fujitsu SDHCI controller 2 - 3 - This file documents differences between the core properties in mmc.txt 4 - and the properties used by the sdhci_f_sdh30 driver. 5 - 6 - Required properties: 7 - - compatible: "fujitsu,mb86s70-sdhci-3.0" 8 - - clocks: Must contain an entry for each entry in clock-names. It is a 9 - list of phandles and clock-specifier pairs. 10 - See ../clocks/clock-bindings.txt for details. 11 - - clock-names: Should contain the following two entries: 12 - "iface" - clock used for sdhci interface 13 - "core" - core clock for sdhci controller 14 - 15 - Optional properties: 16 - - vqmmc-supply: phandle to the regulator device tree node, mentioned 17 - as the VCCQ/VDD_IO supply in the eMMC/SD specs. 18 - - fujitsu,cmd-dat-delay-select: boolean property indicating that this host 19 - requires the CMD_DAT_DELAY control to be enabled. 20 - 21 - Example: 22 - 23 - sdhci1: mmc@36600000 { 24 - compatible = "fujitsu,mb86s70-sdhci-3.0"; 25 - reg = <0 0x36600000 0x1000>; 26 - interrupts = <0 172 0x4>, 27 - <0 173 0x4>; 28 - bus-width = <4>; 29 - vqmmc-supply = <&vccq_sdhci1>; 30 - clocks = <&clock 2 2 0>, <&clock 2 3 0>; 31 - clock-names = "iface", "core"; 32 - };

+9 -14

Documentation/devicetree/bindings/mmc/sdhci-msm.yaml

··· 1 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 - 3 2 %YAML 1.2 4 3 --- 5 - $id: "http://devicetree.org/schemas/mmc/sdhci-msm.yaml#" 6 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 4 + $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 6 8 7 title: Qualcomm SDHCI controller (sdhci-msm) 9 8 ··· 25 26 - qcom,msm8226-sdhci 26 27 - qcom,msm8953-sdhci 27 28 - qcom,msm8974-sdhci 29 + - qcom,msm8976-sdhci 28 30 - qcom,msm8916-sdhci 29 31 - qcom,msm8992-sdhci 30 32 - qcom,msm8994-sdhci ··· 45 45 - qcom,sm6115-sdhci 46 46 - qcom,sm6125-sdhci 47 47 - qcom,sm6350-sdhci 48 + - qcom,sm6375-sdhci 48 49 - qcom,sm8150-sdhci 49 50 - qcom,sm8250-sdhci 51 + - qcom,sm8350-sdhci 50 52 - qcom,sm8450-sdhci 53 + - qcom,sm8550-sdhci 51 54 - const: qcom,sdhci-msm-v5 # for sdcc version 5.0 52 55 53 56 reg: ··· 82 79 - const: bus 83 80 - const: cal 84 81 - const: sleep 82 + 83 + dma-coherent: true 85 84 86 85 interrupts: 87 86 maxItems: 2 ··· 138 133 description: A phandle to sdhci power domain node 139 134 maxItems: 1 140 135 141 - mmc-ddr-1_8v: true 142 - 143 - mmc-hs200-1_8v: true 144 - 145 - mmc-hs400-1_8v: true 146 - 147 - bus-width: true 148 - 149 - max-frequency: true 150 - 151 136 operating-points-v2: true 152 137 153 138 patternProperties: ··· 160 165 - interrupts 161 166 162 167 allOf: 163 - - $ref: mmc-controller.yaml# 168 + - $ref: sdhci-common.yaml# 164 169 165 170 - if: 166 171 properties:

+11

Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml

··· 45 45 - const: block 46 46 - const: timer 47 47 48 + resets: 49 + maxItems: 5 50 + 51 + reset-names: 52 + items: 53 + - const: core 54 + - const: bus 55 + - const: axi 56 + - const: block 57 + - const: timer 58 + 48 59 rockchip,txclk-tapnum: 49 60 description: Specify the number of delay for tx sampling. 50 61 $ref: /schemas/types.yaml#/definitions/uint8

+61

Documentation/devicetree/bindings/mmc/sunplus,mmc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + # Copyright (C) Sunplus Ltd. Co. 2021 3 + %YAML 1.2 4 + --- 5 + $id: http://devicetree.org/schemas/mmc/sunplus,mmc.yaml# 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 + 8 + title: Sunplus MMC Controller 9 + 10 + maintainers: 11 + - Tony Huang <tonyhuang.sunplus@gmail.com> 12 + - Li-hao Kuo <lhjeff911@gmail.com> 13 + 14 + allOf: 15 + - $ref: "mmc-controller.yaml" 16 + 17 + properties: 18 + compatible: 19 + enum: 20 + - sunplus,sp7021-mmc 21 + 22 + reg: 23 + maxItems: 1 24 + 25 + interrupts: 26 + maxItems: 1 27 + 28 + clocks: 29 + maxItems: 1 30 + 31 + resets: 32 + maxItems: 1 33 + 34 + required: 35 + - compatible 36 + - reg 37 + - interrupts 38 + - clocks 39 + - resets 40 + 41 + unevaluatedProperties: false 42 + 43 + examples: 44 + - | 45 + #include <dt-bindings/interrupt-controller/irq.h> 46 + #include <dt-bindings/interrupt-controller/arm-gic.h> 47 + mmc0: mmc@9c003b00 { 48 + compatible = "sunplus,sp7021-mmc"; 49 + reg = <0x9c003b00 0x180>; 50 + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 51 + clocks = <&clkc 0x4e>; 52 + resets = <&rstc 0x3e>; 53 + bus-width = <8>; 54 + max-frequency = <52000000>; 55 + non-removable; 56 + disable-wp; 57 + cap-mmc-highspeed; 58 + mmc-ddr-3_3v; 59 + no-sdio; 60 + no-sd; 61 + };

+29 -3

Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml

··· 6 6 7 7 title: Synopsys Designware Mobile Storage Host Controller Binding 8 8 9 - allOf: 10 - - $ref: "synopsys-dw-mshc-common.yaml#" 11 - 12 9 maintainers: 13 10 - Ulf Hansson <ulf.hansson@linaro.org> 14 11 ··· 34 37 items: 35 38 - const: biu 36 39 - const: ciu 40 + 41 + altr,sysmgr-syscon: 42 + $ref: /schemas/types.yaml#/definitions/phandle-array 43 + items: 44 + - items: 45 + - description: phandle to the sysmgr node 46 + - description: register offset that controls the SDMMC clock phase 47 + - description: register shift for the smplsel(drive in) setting 48 + description: 49 + This property is optional. Contains the phandle to System Manager block 50 + that contains the SDMMC clock-phase control register. The first value is 51 + the pointer to the sysmgr, the 2nd value is the register offset for the 52 + SDMMC clock phase register, and the 3rd value is the bit shift for the 53 + smplsel(drive in) setting. 54 + 55 + allOf: 56 + - $ref: synopsys-dw-mshc-common.yaml# 57 + 58 + - if: 59 + properties: 60 + compatible: 61 + contains: 62 + const: altr,socfpga-dw-mshc 63 + then: 64 + properties: 65 + altr,sysmgr-syscon: true 66 + else: 67 + properties: 68 + altr,sysmgr-syscon: false 37 69 38 70 required: 39 71 - compatible

+6 -7

Documentation/devicetree/bindings/power/wakeup-source.txt

··· 17 17 List of legacy properties and respective binding document 18 18 --------------------------------------------------------- 19 19 20 - 1. "enable-sdio-wakeup" Documentation/devicetree/bindings/mmc/mmc.txt 21 - 2. "gpio-key,wakeup" Documentation/devicetree/bindings/input/gpio-keys{,-polled}.txt 22 - 3. "has-tpo" Documentation/devicetree/bindings/rtc/rtc-opal.txt 23 - 4. "linux,wakeup" Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt 20 + 1. "gpio-key,wakeup" Documentation/devicetree/bindings/input/gpio-keys{,-polled}.txt 21 + 2. "has-tpo" Documentation/devicetree/bindings/rtc/rtc-opal.txt 22 + 3. "linux,wakeup" Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt 24 23 Documentation/devicetree/bindings/mfd/tc3589x.txt 25 24 Documentation/devicetree/bindings/input/touchscreen/ads7846.txt 26 - 5. "linux,keypad-wakeup" Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt 27 - 6. "linux,input-wakeup" Documentation/devicetree/bindings/input/samsung-keypad.txt 28 - 7. "nvidia,wakeup-source" Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt 25 + 4. "linux,keypad-wakeup" Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt 26 + 5. "linux,input-wakeup" Documentation/devicetree/bindings/input/samsung-keypad.txt 27 + 6. "nvidia,wakeup-source" Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt 29 28 30 29 Examples 31 30 --------

+9

MAINTAINERS

··· 18612 18612 K: \bTIF_SECCOMP\b 18613 18613 18614 18614 SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) Broadcom BRCMSTB DRIVER 18615 + M: Kamal Dasu <kdasu.kdev@gmail.com> 18615 18616 M: Al Cooper <alcooperx@gmail.com> 18616 18617 R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com> 18617 18618 L: linux-mmc@vger.kernel.org ··· 18623 18622 M: Adrian Hunter <adrian.hunter@intel.com> 18624 18623 L: linux-mmc@vger.kernel.org 18625 18624 S: Supported 18625 + F: Documentation/devicetree/bindings/mmc/sdhci-common.yaml 18626 18626 F: drivers/mmc/host/sdhci* 18627 18627 18628 18628 SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) MICROCHIP DRIVER ··· 19885 19883 W: https://sunplus.atlassian.net/wiki/spaces/doc/overview 19886 19884 F: Documentation/devicetree/bindings/net/sunplus,sp7021-emac.yaml 19887 19885 F: drivers/net/ethernet/sunplus/ 19886 + 19887 + SUNPLUS MMC DRIVER 19888 + M: Tony Huang <tonyhuang.sunplus@gmail.com> 19889 + M: Li-hao Kuo <lhjeff911@gmail.com> 19890 + S: Maintained 19891 + F: Documentation/devicetree/bindings/mmc/sunplus,mmc.yaml 19892 + F: drivers/mmc/host/sunplus-mmc.c 19888 19893 19889 19894 SUNPLUS OCOTP DRIVER 19890 19895 M: Vincent Shih <vincent.sunplus@gmail.com>

-68

drivers/clk/socfpga/clk-gate-a10.c

··· 35 35 return parent_rate / div; 36 36 } 37 37 38 - static int socfpga_clk_prepare(struct clk_hw *hwclk) 39 - { 40 - struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); 41 - int i; 42 - u32 hs_timing; 43 - u32 clk_phase[2]; 44 - 45 - if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { 46 - for (i = 0; i < ARRAY_SIZE(clk_phase); i++) { 47 - switch (socfpgaclk->clk_phase[i]) { 48 - case 0: 49 - clk_phase[i] = 0; 50 - break; 51 - case 45: 52 - clk_phase[i] = 1; 53 - break; 54 - case 90: 55 - clk_phase[i] = 2; 56 - break; 57 - case 135: 58 - clk_phase[i] = 3; 59 - break; 60 - case 180: 61 - clk_phase[i] = 4; 62 - break; 63 - case 225: 64 - clk_phase[i] = 5; 65 - break; 66 - case 270: 67 - clk_phase[i] = 6; 68 - break; 69 - case 315: 70 - clk_phase[i] = 7; 71 - break; 72 - default: 73 - clk_phase[i] = 0; 74 - break; 75 - } 76 - } 77 - 78 - hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]); 79 - if (!IS_ERR(socfpgaclk->sys_mgr_base_addr)) 80 - regmap_write(socfpgaclk->sys_mgr_base_addr, 81 - SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing); 82 - else 83 - pr_err("%s: cannot set clk_phase because sys_mgr_base_addr is not available!\n", 84 - __func__); 85 - } 86 - return 0; 87 - } 88 - 89 38 static struct clk_ops gateclk_ops = { 90 - .prepare = socfpga_clk_prepare, 91 39 .recalc_rate = socfpga_gate_clk_recalc_rate, 92 40 }; 93 41 ··· 44 96 { 45 97 u32 clk_gate[2]; 46 98 u32 div_reg[3]; 47 - u32 clk_phase[2]; 48 99 u32 fixed_div; 49 100 struct clk_hw *hw_clk; 50 101 struct socfpga_gate_clk *socfpga_clk; ··· 81 134 socfpga_clk->width = div_reg[2]; 82 135 } else { 83 136 socfpga_clk->div_reg = NULL; 84 - } 85 - 86 - rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2); 87 - if (!rc) { 88 - socfpga_clk->clk_phase[0] = clk_phase[0]; 89 - socfpga_clk->clk_phase[1] = clk_phase[1]; 90 - 91 - socfpga_clk->sys_mgr_base_addr = 92 - syscon_regmap_lookup_by_compatible("altr,sys-mgr"); 93 - if (IS_ERR(socfpga_clk->sys_mgr_base_addr)) { 94 - pr_err("%s: failed to find altr,sys-mgr regmap!\n", 95 - __func__); 96 - kfree(socfpga_clk); 97 - return; 98 - } 99 137 } 100 138 101 139 of_property_read_string(node, "clock-output-names", &clk_name);

-61

drivers/clk/socfpga/clk-gate.c

··· 108 108 return parent_rate / div; 109 109 } 110 110 111 - static int socfpga_clk_prepare(struct clk_hw *hwclk) 112 - { 113 - struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); 114 - struct regmap *sys_mgr_base_addr; 115 - int i; 116 - u32 hs_timing; 117 - u32 clk_phase[2]; 118 - 119 - if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { 120 - sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr"); 121 - if (IS_ERR(sys_mgr_base_addr)) { 122 - pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__); 123 - return -EINVAL; 124 - } 125 - 126 - for (i = 0; i < 2; i++) { 127 - switch (socfpgaclk->clk_phase[i]) { 128 - case 0: 129 - clk_phase[i] = 0; 130 - break; 131 - case 45: 132 - clk_phase[i] = 1; 133 - break; 134 - case 90: 135 - clk_phase[i] = 2; 136 - break; 137 - case 135: 138 - clk_phase[i] = 3; 139 - break; 140 - case 180: 141 - clk_phase[i] = 4; 142 - break; 143 - case 225: 144 - clk_phase[i] = 5; 145 - break; 146 - case 270: 147 - clk_phase[i] = 6; 148 - break; 149 - case 315: 150 - clk_phase[i] = 7; 151 - break; 152 - default: 153 - clk_phase[i] = 0; 154 - break; 155 - } 156 - } 157 - hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]); 158 - regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET, 159 - hs_timing); 160 - } 161 - return 0; 162 - } 163 - 164 111 static struct clk_ops gateclk_ops = { 165 - .prepare = socfpga_clk_prepare, 166 112 .recalc_rate = socfpga_clk_recalc_rate, 167 113 .get_parent = socfpga_clk_get_parent, 168 114 .set_parent = socfpga_clk_set_parent, ··· 118 172 { 119 173 u32 clk_gate[2]; 120 174 u32 div_reg[3]; 121 - u32 clk_phase[2]; 122 175 u32 fixed_div; 123 176 struct clk_hw *hw_clk; 124 177 struct socfpga_gate_clk *socfpga_clk; ··· 161 216 socfpga_clk->width = div_reg[2]; 162 217 } else { 163 218 socfpga_clk->div_reg = NULL; 164 - } 165 - 166 - rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2); 167 - if (!rc) { 168 - socfpga_clk->clk_phase[0] = clk_phase[0]; 169 - socfpga_clk->clk_phase[1] = clk_phase[1]; 170 219 } 171 220 172 221 of_property_read_string(node, "clock-output-names", &clk_name);

-1

drivers/clk/socfpga/clk.h

··· 50 50 u32 width; /* only valid if div_reg != 0 */ 51 51 u32 shift; /* only valid if div_reg != 0 */ 52 52 u32 bypass_shift; /* only valid if bypass_reg != 0 */ 53 - u32 clk_phase[2]; 54 53 }; 55 54 56 55 struct socfpga_periph_clk {

+8 -1

drivers/memstick/core/ms_block.c

··· 2116 2116 dbg("Set total disk size to %lu sectors", capacity); 2117 2117 2118 2118 msb->io_queue = alloc_ordered_workqueue("ms_block", WQ_MEM_RECLAIM); 2119 + if (!msb->io_queue) { 2120 + rc = -ENOMEM; 2121 + goto out_cleanup_disk; 2122 + } 2123 + 2119 2124 INIT_WORK(&msb->io_work, msb_io_work); 2120 2125 sg_init_table(msb->prealloc_sg, MS_BLOCK_MAX_SEGS+1); 2121 2126 ··· 2130 2125 msb_start(card); 2131 2126 rc = device_add_disk(&card->dev, msb->disk, NULL); 2132 2127 if (rc) 2133 - goto out_cleanup_disk; 2128 + goto out_destroy_workqueue; 2134 2129 dbg("Disk added"); 2135 2130 return 0; 2136 2131 2132 + out_destroy_workqueue: 2133 + destroy_workqueue(msb->io_queue); 2137 2134 out_cleanup_disk: 2138 2135 put_disk(msb->disk); 2139 2136 out_free_tag_set:

+72 -105

drivers/memstick/core/mspro_block.c

··· 260 260 buffer[rc++] = '\n'; 261 261 } 262 262 263 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "%02x ", 264 - ((unsigned char *)s_attr->data)[cnt]); 263 + rc += sysfs_emit_at(buffer, rc, "%02x ", 264 + ((unsigned char *)s_attr->data)[cnt]); 265 265 } 266 266 return rc; 267 267 } ··· 290 290 date_tz_f *= 15; 291 291 } 292 292 293 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "class: %x\n", 294 - x_sys->class); 295 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "block size: %x\n", 296 - be16_to_cpu(x_sys->block_size)); 297 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "block count: %x\n", 298 - be16_to_cpu(x_sys->block_count)); 299 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "user block count: %x\n", 300 - be16_to_cpu(x_sys->user_block_count)); 301 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "page size: %x\n", 302 - be16_to_cpu(x_sys->page_size)); 303 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "assembly date: " 304 - "GMT%+d:%d %04u-%02u-%02u %02u:%02u:%02u\n", 305 - date_tz, date_tz_f, 306 - be16_to_cpup((__be16 *)&x_sys->assembly_date[1]), 307 - x_sys->assembly_date[3], x_sys->assembly_date[4], 308 - x_sys->assembly_date[5], x_sys->assembly_date[6], 309 - x_sys->assembly_date[7]); 310 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "serial number: %x\n", 311 - be32_to_cpu(x_sys->serial_number)); 312 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, 313 - "assembly maker code: %x\n", 314 - x_sys->assembly_maker_code); 315 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "assembly model code: " 316 - "%02x%02x%02x\n", x_sys->assembly_model_code[0], 317 - x_sys->assembly_model_code[1], 318 - x_sys->assembly_model_code[2]); 319 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "memory maker code: %x\n", 320 - be16_to_cpu(x_sys->memory_maker_code)); 321 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "memory model code: %x\n", 322 - be16_to_cpu(x_sys->memory_model_code)); 323 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "vcc: %x\n", 324 - x_sys->vcc); 325 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "vpp: %x\n", 326 - x_sys->vpp); 327 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "controller number: %x\n", 328 - be16_to_cpu(x_sys->controller_number)); 329 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, 330 - "controller function: %x\n", 331 - be16_to_cpu(x_sys->controller_function)); 332 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "start sector: %x\n", 333 - be16_to_cpu(x_sys->start_sector)); 334 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "unit size: %x\n", 335 - be16_to_cpu(x_sys->unit_size)); 336 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "sub class: %x\n", 337 - x_sys->ms_sub_class); 338 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "interface type: %x\n", 339 - x_sys->interface_type); 340 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "controller code: %x\n", 341 - be16_to_cpu(x_sys->controller_code)); 342 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "format type: %x\n", 343 - x_sys->format_type); 344 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "device type: %x\n", 345 - x_sys->device_type); 346 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "mspro id: %s\n", 347 - x_sys->mspro_id); 293 + rc += sysfs_emit_at(buffer, rc, "class: %x\n", x_sys->class); 294 + rc += sysfs_emit_at(buffer, rc, "block size: %x\n", be16_to_cpu(x_sys->block_size)); 295 + rc += sysfs_emit_at(buffer, rc, "block count: %x\n", be16_to_cpu(x_sys->block_count)); 296 + rc += sysfs_emit_at(buffer, rc, "user block count: %x\n", 297 + be16_to_cpu(x_sys->user_block_count)); 298 + rc += sysfs_emit_at(buffer, rc, "page size: %x\n", be16_to_cpu(x_sys->page_size)); 299 + rc += sysfs_emit_at(buffer, rc, "assembly date: GMT%+d:%d %04u-%02u-%02u %02u:%02u:%02u\n", 300 + date_tz, date_tz_f, 301 + be16_to_cpup((__be16 *)&x_sys->assembly_date[1]), 302 + x_sys->assembly_date[3], x_sys->assembly_date[4], 303 + x_sys->assembly_date[5], x_sys->assembly_date[6], 304 + x_sys->assembly_date[7]); 305 + rc += sysfs_emit_at(buffer, rc, "serial number: %x\n", be32_to_cpu(x_sys->serial_number)); 306 + rc += sysfs_emit_at(buffer, rc, "assembly maker code: %x\n", x_sys->assembly_maker_code); 307 + rc += sysfs_emit_at(buffer, rc, "assembly model code: %02x%02x%02x\n", 308 + x_sys->assembly_model_code[0], 309 + x_sys->assembly_model_code[1], 310 + x_sys->assembly_model_code[2]); 311 + rc += sysfs_emit_at(buffer, rc, "memory maker code: %x\n", 312 + be16_to_cpu(x_sys->memory_maker_code)); 313 + rc += sysfs_emit_at(buffer, rc, "memory model code: %x\n", 314 + be16_to_cpu(x_sys->memory_model_code)); 315 + rc += sysfs_emit_at(buffer, rc, "vcc: %x\n", x_sys->vcc); 316 + rc += sysfs_emit_at(buffer, rc, "vpp: %x\n", x_sys->vpp); 317 + rc += sysfs_emit_at(buffer, rc, "controller number: %x\n", 318 + be16_to_cpu(x_sys->controller_number)); 319 + rc += sysfs_emit_at(buffer, rc, "controller function: %x\n", 320 + be16_to_cpu(x_sys->controller_function)); 321 + rc += sysfs_emit_at(buffer, rc, "start sector: %x\n", be16_to_cpu(x_sys->start_sector)); 322 + rc += sysfs_emit_at(buffer, rc, "unit size: %x\n", be16_to_cpu(x_sys->unit_size)); 323 + rc += sysfs_emit_at(buffer, rc, "sub class: %x\n", x_sys->ms_sub_class); 324 + rc += sysfs_emit_at(buffer, rc, "interface type: %x\n", x_sys->interface_type); 325 + rc += sysfs_emit_at(buffer, rc, "controller code: %x\n", 326 + be16_to_cpu(x_sys->controller_code)); 327 + rc += sysfs_emit_at(buffer, rc, "format type: %x\n", x_sys->format_type); 328 + rc += sysfs_emit_at(buffer, rc, "device type: %x\n", x_sys->device_type); 329 + rc += sysfs_emit_at(buffer, rc, "mspro id: %s\n", x_sys->mspro_id); 348 330 return rc; 349 331 } 350 332 ··· 338 356 struct mspro_sys_attr, 339 357 dev_attr); 340 358 341 - return scnprintf(buffer, PAGE_SIZE, "%s", (char *)s_attr->data); 359 + return sysfs_emit(buffer, "%s", (char *)s_attr->data); 342 360 } 343 361 344 362 static ssize_t mspro_block_attr_show_mbr(struct device *dev, ··· 351 369 struct mspro_mbr *x_mbr = x_attr->data; 352 370 ssize_t rc = 0; 353 371 354 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "boot partition: %x\n", 355 - x_mbr->boot_partition); 356 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "start head: %x\n", 357 - x_mbr->start_head); 358 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "start sector: %x\n", 359 - x_mbr->start_sector); 360 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "start cylinder: %x\n", 361 - x_mbr->start_cylinder); 362 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "partition type: %x\n", 363 - x_mbr->partition_type); 364 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "end head: %x\n", 365 - x_mbr->end_head); 366 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "end sector: %x\n", 367 - x_mbr->end_sector); 368 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "end cylinder: %x\n", 369 - x_mbr->end_cylinder); 370 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "start sectors: %x\n", 371 - x_mbr->start_sectors); 372 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, 373 - "sectors per partition: %x\n", 374 - x_mbr->sectors_per_partition); 372 + rc += sysfs_emit_at(buffer, rc, "boot partition: %x\n", x_mbr->boot_partition); 373 + rc += sysfs_emit_at(buffer, rc, "start head: %x\n", x_mbr->start_head); 374 + rc += sysfs_emit_at(buffer, rc, "start sector: %x\n", x_mbr->start_sector); 375 + rc += sysfs_emit_at(buffer, rc, "start cylinder: %x\n", x_mbr->start_cylinder); 376 + rc += sysfs_emit_at(buffer, rc, "partition type: %x\n", x_mbr->partition_type); 377 + rc += sysfs_emit_at(buffer, rc, "end head: %x\n", x_mbr->end_head); 378 + rc += sysfs_emit_at(buffer, rc, "end sector: %x\n", x_mbr->end_sector); 379 + rc += sysfs_emit_at(buffer, rc, "end cylinder: %x\n", x_mbr->end_cylinder); 380 + rc += sysfs_emit_at(buffer, rc, "start sectors: %x\n", x_mbr->start_sectors); 381 + rc += sysfs_emit_at(buffer, rc, "sectors per partition: %x\n", 382 + x_mbr->sectors_per_partition); 375 383 return rc; 376 384 } 377 385 ··· 381 409 memcpy(ext, x_spfile->ext, 3); 382 410 ext[3] = 0; 383 411 384 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "name: %s\n", name); 385 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "ext: %s\n", ext); 386 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "attribute: %x\n", 387 - x_spfile->attr); 388 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "time: %d:%d:%d\n", 389 - x_spfile->time >> 11, 390 - (x_spfile->time >> 5) & 0x3f, 391 - (x_spfile->time & 0x1f) * 2); 392 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "date: %d-%d-%d\n", 393 - (x_spfile->date >> 9) + 1980, 394 - (x_spfile->date >> 5) & 0xf, 395 - x_spfile->date & 0x1f); 396 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "start cluster: %x\n", 397 - x_spfile->cluster); 398 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "size: %x\n", 399 - x_spfile->size); 412 + rc += sysfs_emit_at(buffer, rc, "name: %s\n", name); 413 + rc += sysfs_emit_at(buffer, rc, "ext: %s\n", ext); 414 + rc += sysfs_emit_at(buffer, rc, "attribute: %x\n", x_spfile->attr); 415 + rc += sysfs_emit_at(buffer, rc, "time: %d:%d:%d\n", 416 + x_spfile->time >> 11, 417 + (x_spfile->time >> 5) & 0x3f, 418 + (x_spfile->time & 0x1f) * 2); 419 + rc += sysfs_emit_at(buffer, rc, "date: %d-%d-%d\n", 420 + (x_spfile->date >> 9) + 1980, 421 + (x_spfile->date >> 5) & 0xf, 422 + x_spfile->date & 0x1f); 423 + rc += sysfs_emit_at(buffer, rc, "start cluster: %x\n", x_spfile->cluster); 424 + rc += sysfs_emit_at(buffer, rc, "size: %x\n", x_spfile->size); 400 425 return rc; 401 426 } 402 427 ··· 407 438 struct mspro_devinfo *x_devinfo = x_attr->data; 408 439 ssize_t rc = 0; 409 440 410 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "cylinders: %x\n", 411 - be16_to_cpu(x_devinfo->cylinders)); 412 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "heads: %x\n", 413 - be16_to_cpu(x_devinfo->heads)); 414 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "bytes per track: %x\n", 415 - be16_to_cpu(x_devinfo->bytes_per_track)); 416 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "bytes per sector: %x\n", 417 - be16_to_cpu(x_devinfo->bytes_per_sector)); 418 - rc += scnprintf(buffer + rc, PAGE_SIZE - rc, "sectors per track: %x\n", 419 - be16_to_cpu(x_devinfo->sectors_per_track)); 441 + rc += sysfs_emit_at(buffer, rc, "cylinders: %x\n", be16_to_cpu(x_devinfo->cylinders)); 442 + rc += sysfs_emit_at(buffer, rc, "heads: %x\n", be16_to_cpu(x_devinfo->heads)); 443 + rc += sysfs_emit_at(buffer, rc, "bytes per track: %x\n", 444 + be16_to_cpu(x_devinfo->bytes_per_track)); 445 + rc += sysfs_emit_at(buffer, rc, "bytes per sector: %x\n", 446 + be16_to_cpu(x_devinfo->bytes_per_sector)); 447 + rc += sysfs_emit_at(buffer, rc, "sectors per track: %x\n", 448 + be16_to_cpu(x_devinfo->sectors_per_track)); 420 449 return rc; 421 450 } 422 451

-13

drivers/mmc/core/block.c

··· 514 514 if (idata->ic.data_timeout_ns) 515 515 data.timeout_ns = idata->ic.data_timeout_ns; 516 516 517 - if ((cmd.flags & MMC_RSP_R1B) == MMC_RSP_R1B) { 518 - /* 519 - * Pretend this is a data transfer and rely on the 520 - * host driver to compute timeout. When all host 521 - * drivers support cmd.cmd_timeout for R1B, this 522 - * can be changed to: 523 - * 524 - * mrq.data = NULL; 525 - * cmd.cmd_timeout = idata->ic.cmd_timeout_ms; 526 - */ 527 - data.timeout_ns = idata->ic.cmd_timeout_ms * 1000000; 528 - } 529 - 530 517 mrq.data = &data; 531 518 } 532 519

-4

drivers/mmc/core/bus.c

··· 359 359 uhs_bus_speed_mode, type, card->rca); 360 360 } 361 361 362 - #ifdef CONFIG_DEBUG_FS 363 362 mmc_add_card_debugfs(card); 364 - #endif 365 363 card->dev.of_node = mmc_of_find_child_device(card->host, 0); 366 364 367 365 device_enable_async_suspend(&card->dev); ··· 381 383 { 382 384 struct mmc_host *host = card->host; 383 385 384 - #ifdef CONFIG_DEBUG_FS 385 386 mmc_remove_card_debugfs(card); 386 - #endif 387 387 388 388 if (mmc_card_present(card)) { 389 389 if (mmc_host_is_spi(card->host)) {

+3 -4

drivers/mmc/core/core.c

··· 56 56 /* 57 57 * Enabling software CRCs on the data blocks can be a significant (30%) 58 58 * performance cost, and for other reasons may not always be desired. 59 - * So we allow it it to be disabled. 59 + * So we allow it to be disabled. 60 60 */ 61 61 bool use_spi_crc = 1; 62 62 module_param(use_spi_crc, bool, 0); ··· 142 142 int err = cmd->error; 143 143 144 144 /* Flag re-tuning needed on CRC errors */ 145 - if (cmd->opcode != MMC_SEND_TUNING_BLOCK && 146 - cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 && 145 + if (!mmc_op_tuning(cmd->opcode) && 147 146 !host->retune_crc_disable && 148 147 (err == -EILSEQ || (mrq->sbc && mrq->sbc->error == -EILSEQ) || 149 148 (mrq->data && mrq->data->error == -EILSEQ) || ··· 526 527 * mmc_cqe_recovery - Recover from CQE errors. 527 528 * @host: MMC host to recover 528 529 * 529 - * Recovery consists of stopping CQE, stopping eMMC, discarding the queue in 530 + * Recovery consists of stopping CQE, stopping eMMC, discarding the queue 530 531 * in eMMC, and discarding the queue in CQE. CQE must call 531 532 * mmc_cqe_request_done() on all requests. An error is returned if the eMMC 532 533 * fails to discard its queue.

+15

drivers/mmc/core/core.h

··· 86 86 extern bool use_spi_crc; 87 87 88 88 /* Debugfs information for hosts and cards */ 89 + #ifdef CONFIG_DEBUG_FS 89 90 void mmc_add_host_debugfs(struct mmc_host *host); 90 91 void mmc_remove_host_debugfs(struct mmc_host *host); 91 92 92 93 void mmc_add_card_debugfs(struct mmc_card *card); 93 94 void mmc_remove_card_debugfs(struct mmc_card *card); 95 + #else 96 + static inline void mmc_add_host_debugfs(struct mmc_host *host) 97 + { 98 + } 99 + static inline void mmc_remove_host_debugfs(struct mmc_host *host) 100 + { 101 + } 102 + static inline void mmc_add_card_debugfs(struct mmc_card *card) 103 + { 104 + } 105 + static inline void mmc_remove_card_debugfs(struct mmc_card *card) 106 + { 107 + } 108 + #endif 94 109 95 110 int mmc_execute_tuning(struct mmc_card *card); 96 111 int mmc_hs200_to_hs400(struct mmc_card *card);

+1 -5

drivers/mmc/core/host.c

··· 269 269 * @host: host whose properties should be parsed. 270 270 * 271 271 * To keep the rest of the MMC subsystem unaware of whether DT has been 272 - * used to to instantiate and configure this host instance or not, we 272 + * used to instantiate and configure this host instance or not, we 273 273 * parse the properties and set respective generic mmc-host flags and 274 274 * parameters. 275 275 */ ··· 629 629 630 630 led_trigger_register_simple(dev_name(&host->class_dev), &host->led); 631 631 632 - #ifdef CONFIG_DEBUG_FS 633 632 mmc_add_host_debugfs(host); 634 - #endif 635 633 636 634 mmc_start_host(host); 637 635 return 0; ··· 649 651 { 650 652 mmc_stop_host(host); 651 653 652 - #ifdef CONFIG_DEBUG_FS 653 654 mmc_remove_host_debugfs(host); 654 - #endif 655 655 656 656 device_del(&host->class_dev); 657 657

-5

drivers/mmc/core/mmc_test.c

··· 932 932 unsigned blocks, unsigned blksz, int write) 933 933 { 934 934 int ret, i; 935 - unsigned long flags; 936 935 937 936 if (write) { 938 937 for (i = 0; i < blocks * blksz; i++) ··· 939 940 } else { 940 941 memset(test->scratch, 0, BUFFER_SIZE); 941 942 } 942 - local_irq_save(flags); 943 943 sg_copy_from_buffer(sg, sg_len, test->scratch, BUFFER_SIZE); 944 - local_irq_restore(flags); 945 944 946 945 ret = mmc_test_set_blksize(test, blksz); 947 946 if (ret) ··· 984 987 return RESULT_FAIL; 985 988 } 986 989 } else { 987 - local_irq_save(flags); 988 990 sg_copy_to_buffer(sg, sg_len, test->scratch, BUFFER_SIZE); 989 - local_irq_restore(flags); 990 991 for (i = 0; i < blocks * blksz; i++) { 991 992 if (test->scratch[i] != (u8)i) 992 993 return RESULT_FAIL;

+1 -1

drivers/mmc/core/pwrseq.c

··· 29 29 30 30 mutex_lock(&pwrseq_list_mutex); 31 31 list_for_each_entry(p, &pwrseq_list, pwrseq_node) { 32 - if (p->dev->of_node == np) { 32 + if (device_match_of_node(p->dev, np)) { 33 33 if (!try_module_get(p->owner)) 34 34 dev_err(host->parent, 35 35 "increasing module refcount failed\n");

+8 -3

drivers/mmc/core/sd.c

··· 1259 1259 */ 1260 1260 err = sd_read_ext_reg(card, 0, 0, 0, 512, gen_info_buf); 1261 1261 if (err) { 1262 - pr_warn("%s: error %d reading general info of SD ext reg\n", 1262 + pr_err("%s: error %d reading general info of SD ext reg\n", 1263 1263 mmc_hostname(card->host), err); 1264 1264 goto out; 1265 1265 } ··· 1273 1273 /* Number of extensions to be find. */ 1274 1274 num_ext = gen_info_buf[4]; 1275 1275 1276 - /* We support revision 0, but limit it to 512 bytes for simplicity. */ 1276 + /* 1277 + * We only support revision 0 and limit it to 512 bytes for simplicity. 1278 + * No matter what, let's return zero to allow us to continue using the 1279 + * card, even if we can't support the features from the SD function 1280 + * extensions registers. 1281 + */ 1277 1282 if (rev != 0 || len > 512) { 1278 1283 pr_warn("%s: non-supported SD ext reg layout\n", 1279 1284 mmc_hostname(card->host)); ··· 1293 1288 for (i = 0; i < num_ext; i++) { 1294 1289 err = sd_parse_ext_reg(card, gen_info_buf, &next_ext_addr); 1295 1290 if (err) { 1296 - pr_warn("%s: error %d parsing SD ext reg\n", 1291 + pr_err("%s: error %d parsing SD ext reg\n", 1297 1292 mmc_hostname(card->host), err); 1298 1293 goto out; 1299 1294 }

+11 -2

drivers/mmc/host/Kconfig

··· 14 14 added host drivers please don't invent their private macro for 15 15 debugging. 16 16 17 + config MMC_SUNPLUS 18 + tristate "Sunplus SP7021 MMC Controller" 19 + depends on ARCH_SUNPLUS || COMPILE_TEST 20 + help 21 + If you say yes here, you will get support for eMMC host interface 22 + on Sunplus SoCs. 23 + 24 + If unsure, say N 25 + 17 26 config MMC_ARMMMCI 18 27 tristate "ARM AMBA Multimedia Card Interface support" 19 28 depends on ARM_AMBA ··· 1049 1040 1050 1041 config MMC_SDHCI_BRCMSTB 1051 1042 tristate "Broadcom SDIO/SD/MMC support" 1052 - depends on ARCH_BRCMSTB || BMIPS_GENERIC 1043 + depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 1053 1044 depends on MMC_SDHCI_PLTFM 1054 1045 select MMC_CQHCI 1055 - default y 1046 + default ARCH_BRCMSTB || BMIPS_GENERIC 1056 1047 help 1057 1048 This selects support for the SDIO/SD/MMC Host Controller on 1058 1049 Broadcom STB SoCs.

+1

drivers/mmc/host/Makefile

··· 97 97 obj-$(CONFIG_MMC_SDHCI_BRCMSTB) += sdhci-brcmstb.o 98 98 obj-$(CONFIG_MMC_SDHCI_OMAP) += sdhci-omap.o 99 99 obj-$(CONFIG_MMC_SDHCI_SPRD) += sdhci-sprd.o 100 + obj-$(CONFIG_MMC_SUNPLUS) += sunplus-mmc.o 100 101 obj-$(CONFIG_MMC_CQHCI) += cqhci.o 101 102 cqhci-y += cqhci-core.o 102 103 cqhci-$(CONFIG_MMC_CRYPTO) += cqhci-crypto.o

+4 -1

drivers/mmc/host/alcor.c

··· 1114 1114 alcor_hw_init(host); 1115 1115 1116 1116 dev_set_drvdata(&pdev->dev, host); 1117 - mmc_add_host(mmc); 1117 + ret = mmc_add_host(mmc); 1118 + if (ret) 1119 + goto free_host; 1120 + 1118 1121 return 0; 1119 1122 1120 1123 free_host:

+6 -3

drivers/mmc/host/atmel-mci.c

··· 2222 2222 { 2223 2223 struct mmc_host *mmc; 2224 2224 struct atmel_mci_slot *slot; 2225 + int ret; 2225 2226 2226 2227 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev); 2227 2228 if (!mmc) ··· 2306 2305 2307 2306 host->slot[id] = slot; 2308 2307 mmc_regulator_get_supply(mmc); 2309 - mmc_add_host(mmc); 2308 + ret = mmc_add_host(mmc); 2309 + if (ret) { 2310 + mmc_free_host(mmc); 2311 + return ret; 2312 + } 2310 2313 2311 2314 if (gpio_is_valid(slot->detect_pin)) { 2312 - int ret; 2313 - 2314 2315 timer_setup(&slot->detect_timer, atmci_detect_change, 0); 2315 2316 2316 2317 ret = request_irq(gpio_to_irq(slot->detect_pin),

+4 -4

drivers/mmc/host/au1xmmc.c

··· 388 388 389 389 /* This is the pointer to the data buffer */ 390 390 sg = &data->sg[host->pio.index]; 391 - sg_ptr = kmap_atomic(sg_page(sg)) + sg->offset + host->pio.offset; 391 + sg_ptr = kmap_local_page(sg_page(sg)) + sg->offset + host->pio.offset; 392 392 393 393 /* This is the space left inside the buffer */ 394 394 sg_len = data->sg[host->pio.index].length - host->pio.offset; ··· 409 409 __raw_writel((unsigned long)val, HOST_TXPORT(host)); 410 410 wmb(); /* drain writebuffer */ 411 411 } 412 - kunmap_atomic(sg_ptr); 412 + kunmap_local(sg_ptr); 413 413 414 414 host->pio.len -= count; 415 415 host->pio.offset += count; ··· 446 446 447 447 if (host->pio.index < host->dma.len) { 448 448 sg = &data->sg[host->pio.index]; 449 - sg_ptr = kmap_atomic(sg_page(sg)) + sg->offset + host->pio.offset; 449 + sg_ptr = kmap_local_page(sg_page(sg)) + sg->offset + host->pio.offset; 450 450 451 451 /* This is the space left inside the buffer */ 452 452 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset; ··· 488 488 sg_ptr[count] = (unsigned char)(val & 0xFF); 489 489 } 490 490 if (sg_ptr) 491 - kunmap_atomic(sg_ptr); 491 + kunmap_local(sg_ptr); 492 492 493 493 host->pio.len -= count; 494 494 host->pio.offset += count;

+2 -10

drivers/mmc/host/bcm2835.c

··· 327 327 328 328 static void bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read) 329 329 { 330 - unsigned long flags; 331 330 size_t blksize; 332 331 unsigned long wait_max; 333 332 334 333 blksize = host->data->blksz; 335 334 336 335 wait_max = jiffies + msecs_to_jiffies(500); 337 - 338 - local_irq_save(flags); 339 336 340 337 while (blksize) { 341 338 int copy_words; ··· 418 421 } 419 422 420 423 sg_miter_stop(&host->sg_miter); 421 - 422 - local_irq_restore(flags); 423 424 } 424 425 425 426 static void bcm2835_transfer_pio(struct bcm2835_host *host) ··· 1063 1068 } 1064 1069 1065 1070 if (host->drain_words) { 1066 - unsigned long flags; 1067 1071 void *page; 1068 1072 u32 *buf; 1069 1073 ··· 1070 1076 host->drain_page += host->drain_offset >> PAGE_SHIFT; 1071 1077 host->drain_offset &= ~PAGE_MASK; 1072 1078 } 1073 - local_irq_save(flags); 1074 - page = kmap_atomic(host->drain_page); 1079 + page = kmap_local_page(host->drain_page); 1075 1080 buf = page + host->drain_offset; 1076 1081 1077 1082 while (host->drain_words) { ··· 1081 1088 host->drain_words--; 1082 1089 } 1083 1090 1084 - kunmap_atomic(page); 1085 - local_irq_restore(flags); 1091 + kunmap_local(page); 1086 1092 } 1087 1093 1088 1094 bcm2835_finish_data(host);

+40 -1

drivers/mmc/host/dw_mmc-pltfm.c

··· 17 17 #include <linux/mmc/host.h> 18 18 #include <linux/mmc/mmc.h> 19 19 #include <linux/of.h> 20 + #include <linux/mfd/altera-sysmgr.h> 21 + #include <linux/regmap.h> 20 22 21 23 #include "dw_mmc.h" 22 24 #include "dw_mmc-pltfm.h" 25 + 26 + #define SOCFPGA_DW_MMC_CLK_PHASE_STEP 45 27 + #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel, reg_shift) \ 28 + ((((smplsel) & 0x7) << reg_shift) | (((drvsel) & 0x7) << 0)) 23 29 24 30 int dw_mci_pltfm_register(struct platform_device *pdev, 25 31 const struct dw_mci_drv_data *drv_data) ··· 68 62 }; 69 63 EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops); 70 64 65 + static int dw_mci_socfpga_priv_init(struct dw_mci *host) 66 + { 67 + struct device_node *np = host->dev->of_node; 68 + struct regmap *sys_mgr_base_addr; 69 + u32 clk_phase[2] = {0}, reg_offset, reg_shift; 70 + int i, rc, hs_timing; 71 + 72 + rc = of_property_read_variable_u32_array(np, "clk-phase-sd-hs", &clk_phase[0], 2, 0); 73 + if (rc < 0) 74 + return 0; 75 + 76 + sys_mgr_base_addr = altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon"); 77 + if (IS_ERR(sys_mgr_base_addr)) { 78 + dev_warn(host->dev, "clk-phase-sd-hs was specified, but failed to find altr,sys-mgr regmap!\n"); 79 + return 0; 80 + } 81 + 82 + of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset); 83 + of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift); 84 + 85 + for (i = 0; i < ARRAY_SIZE(clk_phase); i++) 86 + clk_phase[i] /= SOCFPGA_DW_MMC_CLK_PHASE_STEP; 87 + 88 + hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1], reg_shift); 89 + regmap_write(sys_mgr_base_addr, reg_offset, hs_timing); 90 + 91 + return 0; 92 + } 93 + 94 + static const struct dw_mci_drv_data socfpga_drv_data = { 95 + .init = dw_mci_socfpga_priv_init, 96 + }; 97 + 71 98 static const struct of_device_id dw_mci_pltfm_match[] = { 72 99 { .compatible = "snps,dw-mshc", }, 73 - { .compatible = "altr,socfpga-dw-mshc", }, 100 + { .compatible = "altr,socfpga-dw-mshc", .data = &socfpga_drv_data, }, 74 101 { .compatible = "img,pistachio-dw-mshc", }, 75 102 {}, 76 103 };

+2 -3

drivers/mmc/host/dw_mmc.c

··· 334 334 cmdr == MMC_READ_MULTIPLE_BLOCK || 335 335 cmdr == MMC_WRITE_BLOCK || 336 336 cmdr == MMC_WRITE_MULTIPLE_BLOCK || 337 - cmdr == MMC_SEND_TUNING_BLOCK || 338 - cmdr == MMC_SEND_TUNING_BLOCK_HS200 || 337 + mmc_op_tuning(cmdr) || 339 338 cmdr == MMC_GEN_CMD) { 340 339 stop->opcode = MMC_STOP_TRANSMISSION; 341 340 stop->arg = 0; ··· 1362 1363 * is just about to roll over. 1363 1364 * 1364 1365 * We do this whole thing under spinlock and only if the 1365 - * command hasn't already completed (indicating the the irq 1366 + * command hasn't already completed (indicating the irq 1366 1367 * already ran so we don't want the timeout). 1367 1368 */ 1368 1369 spin_lock_irqsave(&host->irq_lock, irqflags);

+1

drivers/mmc/host/litex_mmc.c

··· 502 502 503 503 use_polling: 504 504 host->mmc->caps |= MMC_CAP_NEEDS_POLL; 505 + host->irq = 0; 505 506 return 0; 506 507 } 507 508

+3 -1

drivers/mmc/host/meson-gx-mmc.c

··· 1335 1335 } 1336 1336 1337 1337 mmc->ops = &meson_mmc_ops; 1338 - mmc_add_host(mmc); 1338 + ret = mmc_add_host(mmc); 1339 + if (ret) 1340 + goto err_free_irq; 1339 1341 1340 1342 return 0; 1341 1343

+15 -25

drivers/mmc/host/mmc_hsq.c

··· 13 13 14 14 #include "mmc_hsq.h" 15 15 16 - #define HSQ_NUM_SLOTS 64 17 - #define HSQ_INVALID_TAG HSQ_NUM_SLOTS 18 - 19 16 static void mmc_hsq_retry_handler(struct work_struct *work) 20 17 { 21 18 struct mmc_hsq *hsq = container_of(work, struct mmc_hsq, retry_work); ··· 70 73 71 74 static void mmc_hsq_update_next_tag(struct mmc_hsq *hsq, int remains) 72 75 { 73 - struct hsq_slot *slot; 74 76 int tag; 75 77 76 78 /* ··· 78 82 */ 79 83 if (!remains) { 80 84 hsq->next_tag = HSQ_INVALID_TAG; 85 + hsq->tail_tag = HSQ_INVALID_TAG; 81 86 return; 82 87 } 83 88 84 - /* 85 - * Increasing the next tag and check if the corresponding request is 86 - * available, if yes, then we found a candidate request. 87 - */ 88 - if (++hsq->next_tag != HSQ_INVALID_TAG) { 89 - slot = &hsq->slot[hsq->next_tag]; 90 - if (slot->mrq) 91 - return; 92 - } 93 - 94 - /* Othersie we should iterate all slots to find a available tag. */ 95 - for (tag = 0; tag < HSQ_NUM_SLOTS; tag++) { 96 - slot = &hsq->slot[tag]; 97 - if (slot->mrq) 98 - break; 99 - } 100 - 101 - if (tag == HSQ_NUM_SLOTS) 102 - tag = HSQ_INVALID_TAG; 103 - 89 + tag = hsq->tag_slot[hsq->next_tag]; 90 + hsq->tag_slot[hsq->next_tag] = HSQ_INVALID_TAG; 104 91 hsq->next_tag = tag; 105 92 } 106 93 ··· 212 233 * Set the next tag as current request tag if no available 213 234 * next tag. 214 235 */ 215 - if (hsq->next_tag == HSQ_INVALID_TAG) 236 + if (hsq->next_tag == HSQ_INVALID_TAG) { 216 237 hsq->next_tag = tag; 238 + hsq->tail_tag = tag; 239 + hsq->tag_slot[hsq->tail_tag] = HSQ_INVALID_TAG; 240 + } else { 241 + hsq->tag_slot[hsq->tail_tag] = tag; 242 + hsq->tail_tag = tag; 243 + } 217 244 218 245 hsq->qcnt++; 219 246 ··· 324 339 325 340 int mmc_hsq_init(struct mmc_hsq *hsq, struct mmc_host *mmc) 326 341 { 342 + int i; 327 343 hsq->num_slots = HSQ_NUM_SLOTS; 328 344 hsq->next_tag = HSQ_INVALID_TAG; 345 + hsq->tail_tag = HSQ_INVALID_TAG; 329 346 330 347 hsq->slot = devm_kcalloc(mmc_dev(mmc), hsq->num_slots, 331 348 sizeof(struct hsq_slot), GFP_KERNEL); ··· 337 350 hsq->mmc = mmc; 338 351 hsq->mmc->cqe_private = hsq; 339 352 mmc->cqe_ops = &mmc_hsq_ops; 353 + 354 + for (i = 0; i < HSQ_NUM_SLOTS; i++) 355 + hsq->tag_slot[i] = HSQ_INVALID_TAG; 340 356 341 357 INIT_WORK(&hsq->retry_work, mmc_hsq_retry_handler); 342 358 spin_lock_init(&hsq->lock);

+5

drivers/mmc/host/mmc_hsq.h

··· 2 2 #ifndef LINUX_MMC_HSQ_H 3 3 #define LINUX_MMC_HSQ_H 4 4 5 + #define HSQ_NUM_SLOTS 64 6 + #define HSQ_INVALID_TAG HSQ_NUM_SLOTS 7 + 5 8 struct hsq_slot { 6 9 struct mmc_request *mrq; 7 10 }; ··· 20 17 int next_tag; 21 18 int num_slots; 22 19 int qcnt; 20 + int tail_tag; 21 + int tag_slot[HSQ_NUM_SLOTS]; 23 22 24 23 bool enabled; 25 24 bool waiting_for_idle;

+3 -1

drivers/mmc/host/mmci.c

··· 2256 2256 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 2257 2257 pm_runtime_use_autosuspend(&dev->dev); 2258 2258 2259 - mmc_add_host(mmc); 2259 + ret = mmc_add_host(mmc); 2260 + if (ret) 2261 + goto clk_disable; 2260 2262 2261 2263 pm_runtime_put(&dev->dev); 2262 2264 return 0;

+3 -1

drivers/mmc/host/moxart-mmc.c

··· 665 665 goto out; 666 666 667 667 dev_set_drvdata(dev, mmc); 668 - mmc_add_host(mmc); 668 + ret = mmc_add_host(mmc); 669 + if (ret) 670 + goto out; 669 671 670 672 dev_dbg(dev, "IRQ=%d, FIFO is %d bytes\n", irq, host->fifo_width); 671 673

+30 -8

drivers/mmc/host/mtk-sd.c

··· 452 452 struct clk *bus_clk; /* bus clock which used to access register */ 453 453 struct clk *src_clk_cg; /* msdc source clock control gate */ 454 454 struct clk *sys_clk_cg; /* msdc subsys clock control gate */ 455 + struct clk *crypto_clk; /* msdc crypto clock control gate */ 455 456 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; 456 457 u32 mclk; /* mmc subsystem clock frequency */ 457 458 u32 src_clk_freq; /* source clock frequency */ ··· 553 552 .support_64g = false, 554 553 }; 555 554 555 + static const struct mtk_mmc_compatible mt7986_compat = { 556 + .clk_div_bits = 12, 557 + .recheck_sdio_irq = true, 558 + .hs400_tune = false, 559 + .pad_tune_reg = MSDC_PAD_TUNE0, 560 + .async_fifo = true, 561 + .data_tune = true, 562 + .busy_check = true, 563 + .stop_clk_fix = true, 564 + .enhance_rx = true, 565 + .support_64g = true, 566 + }; 567 + 556 568 static const struct mtk_mmc_compatible mt8135_compat = { 557 569 .clk_div_bits = 8, 558 570 .recheck_sdio_irq = true, ··· 623 609 { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat}, 624 610 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 625 611 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 612 + { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat}, 626 613 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 627 614 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 628 615 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, ··· 750 735 else 751 736 bd[j].bd_info &= ~BDMA_DESC_EOL; 752 737 753 - /* checksume need to clear first */ 738 + /* checksum need to clear first */ 754 739 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 755 740 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 756 741 } ··· 841 826 static void msdc_gate_clock(struct msdc_host *host) 842 827 { 843 828 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); 829 + clk_disable_unprepare(host->crypto_clk); 844 830 clk_disable_unprepare(host->src_clk_cg); 845 831 clk_disable_unprepare(host->src_clk); 846 832 clk_disable_unprepare(host->bus_clk); ··· 857 841 clk_prepare_enable(host->bus_clk); 858 842 clk_prepare_enable(host->src_clk); 859 843 clk_prepare_enable(host->src_clk_cg); 844 + clk_prepare_enable(host->crypto_clk); 860 845 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); 861 846 if (ret) { 862 847 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); ··· 1224 1207 1225 1208 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1226 1209 if (events & MSDC_INT_CMDTMO || 1227 - (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1228 - cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 && 1229 - !host->hs400_tuning)) 1210 + (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning)) 1230 1211 /* 1231 1212 * should not clear fifo/interrupt as the tune data 1232 - * may have alreay come when cmd19/cmd21 gets response 1213 + * may have already come when cmd19/cmd21 gets response 1233 1214 * CRC error. 1234 1215 */ 1235 1216 msdc_reset_hw(host); ··· 1318 1303 { 1319 1304 if ((cmd->error && 1320 1305 !(cmd->error == -EILSEQ && 1321 - (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1322 - cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 || 1323 - host->hs400_tuning))) || 1306 + (mmc_op_tuning(cmd->opcode) || host->hs400_tuning))) || 1324 1307 (mrq->sbc && mrq->sbc->error)) 1325 1308 msdc_request_done(host, mrq); 1326 1309 else if (cmd == mrq->sbc) ··· 2667 2654 if (IS_ERR(host->reset)) { 2668 2655 ret = PTR_ERR(host->reset); 2669 2656 goto host_free; 2657 + } 2658 + 2659 + /* only eMMC has crypto property */ 2660 + if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) { 2661 + host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto"); 2662 + if (IS_ERR(host->crypto_clk)) 2663 + host->crypto_clk = NULL; 2664 + else 2665 + mmc->caps2 |= MMC_CAP2_CRYPTO; 2670 2666 } 2671 2667 2672 2668 host->irq = platform_get_irq(pdev, 0);

+3 -1

drivers/mmc/host/mxcmmc.c

··· 1143 1143 1144 1144 timer_setup(&host->watchdog, mxcmci_watchdog, 0); 1145 1145 1146 - mmc_add_host(mmc); 1146 + ret = mmc_add_host(mmc); 1147 + if (ret) 1148 + goto out_free_dma; 1147 1149 1148 1150 return 0; 1149 1151

+3 -1

drivers/mmc/host/omap_hsmmc.c

··· 1946 1946 if (!ret) 1947 1947 mmc->caps |= MMC_CAP_SDIO_IRQ; 1948 1948 1949 - mmc_add_host(mmc); 1949 + ret = mmc_add_host(mmc); 1950 + if (ret) 1951 + goto err_irq; 1950 1952 1951 1953 if (mmc_pdata(host)->name != NULL) { 1952 1954 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);

+6 -1

drivers/mmc/host/pxamci.c

··· 763 763 dev_warn(dev, "gpio_ro and get_ro() both defined\n"); 764 764 } 765 765 766 - mmc_add_host(mmc); 766 + ret = mmc_add_host(mmc); 767 + if (ret) { 768 + if (host->pdata && host->pdata->exit) 769 + host->pdata->exit(dev, mmc); 770 + goto out; 771 + } 767 772 768 773 return 0; 769 774

+12 -4

drivers/mmc/host/renesas_sdhi.h

··· 38 38 39 39 #define SDHI_CALIB_TABLE_MAX 32 40 40 41 + #define sdhi_has_quirk(p, q) ((p)->quirks && (p)->quirks->q) 42 + 41 43 struct renesas_sdhi_quirks { 42 44 bool hs400_disabled; 43 45 bool hs400_4taps; 44 46 bool fixed_addr_mode; 45 47 bool dma_one_rx_only; 46 48 bool manual_tap_correction; 49 + bool old_info1_layout; 47 50 u32 hs400_bad_taps; 48 51 const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX]; 49 52 }; ··· 56 53 const struct renesas_sdhi_quirks *quirks; 57 54 }; 58 55 59 - struct tmio_mmc_dma { 56 + /* We want both end_flags to be set before we mark DMA as finished */ 57 + #define SDHI_DMA_END_FLAG_DMA 0 58 + #define SDHI_DMA_END_FLAG_ACCESS 1 59 + 60 + struct renesas_sdhi_dma { 61 + unsigned long end_flags; 60 62 enum dma_slave_buswidth dma_buswidth; 61 63 bool (*filter)(struct dma_chan *chan, void *arg); 62 64 void (*enable)(struct tmio_mmc_host *host, bool enable); 63 - struct completion dma_dataend; 64 - struct tasklet_struct dma_complete; 65 + struct completion dma_dataend; 66 + struct tasklet_struct dma_complete; 65 67 }; 66 68 67 69 struct renesas_sdhi { ··· 74 66 struct clk *clkh; 75 67 struct clk *clk_cd; 76 68 struct tmio_mmc_data mmc_data; 77 - struct tmio_mmc_dma dma_priv; 69 + struct renesas_sdhi_dma dma_priv; 78 70 const struct renesas_sdhi_quirks *quirks; 79 71 struct pinctrl *pinctrl; 80 72 struct pinctrl_state *pins_default, *pins_uhs;

+16 -16

drivers/mmc/host/renesas_sdhi_core.c

··· 141 141 142 142 if (priv->clkh) { 143 143 /* HS400 with 4TAP needs different clock settings */ 144 - bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 144 + bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 145 145 bool need_slow_clkh = host->mmc->ios.timing == MMC_TIMING_MMC_HS400; 146 146 clkh_shift = use_4tap && need_slow_clkh ? 1 : 2; 147 147 ref_clk = priv->clkh; ··· 383 383 struct tmio_mmc_host *host = mmc_priv(mmc); 384 384 struct renesas_sdhi *priv = host_to_priv(host); 385 385 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 386 - bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 386 + bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 387 387 388 388 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 389 389 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); ··· 395 395 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, 396 396 priv->scc_tappos_hs400); 397 397 398 - if (priv->quirks && priv->quirks->manual_tap_correction) 398 + if (sdhi_has_quirk(priv, manual_tap_correction)) 399 399 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 400 400 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 401 401 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); ··· 546 546 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 547 547 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 548 548 549 - if (priv->adjust_hs400_calib_table) 549 + if (sdhi_has_quirk(priv, hs400_calib_table) || sdhi_has_quirk(priv, hs400_bad_taps)) 550 550 renesas_sdhi_adjust_hs400_mode_disable(host); 551 551 552 552 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | ··· 732 732 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 733 733 734 734 /* Change TAP position according to correction status */ 735 - if (priv->quirks && priv->quirks->manual_tap_correction && 735 + if (sdhi_has_quirk(priv, manual_tap_correction) && 736 736 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 737 737 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 738 738 /* ··· 796 796 struct mmc_request *mrq) 797 797 { 798 798 struct renesas_sdhi *priv = host_to_priv(host); 799 - bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 799 + bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 800 800 bool ret = false; 801 801 802 802 /* ··· 908 908 { 909 909 struct tmio_mmc_data *mmd = pdev->dev.platform_data; 910 910 struct tmio_mmc_data *mmc_data; 911 - struct tmio_mmc_dma *dma_priv; 911 + struct renesas_sdhi_dma *dma_priv; 912 912 struct tmio_mmc_host *host; 913 913 struct renesas_sdhi *priv; 914 914 int num_irqs, irq, ret, i; ··· 990 990 host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 991 991 host->dma_ops = dma_ops; 992 992 993 - if (quirks && quirks->hs400_disabled) 993 + if (sdhi_has_quirk(priv, hs400_disabled)) 994 994 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 995 995 996 996 /* For some SoC, we disable internal WP. GPIO may override this */ ··· 1018 1018 dma_priv->filter = shdma_chan_filter; 1019 1019 dma_priv->enable = renesas_sdhi_enable_dma; 1020 1020 1021 - mmc_data->alignment_shift = 1; /* 2-byte alignment */ 1022 1021 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1023 1022 1024 1023 /* ··· 1055 1056 if (ver == SDHI_VER_GEN2_SDR50) 1056 1057 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 1057 1058 1058 - if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) { 1059 + if (ver == SDHI_VER_GEN3_SDMMC && sdhi_has_quirk(priv, hs400_calib_table)) { 1059 1060 host->fixup_request = renesas_sdhi_fixup_request; 1060 1061 priv->adjust_hs400_calib_table = *( 1061 1062 res->start == SDHI_GEN3_MMC0_ADDR ? ··· 1067 1068 if (ver >= SDHI_VER_GEN3_SD) 1068 1069 host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles; 1069 1070 1071 + /* Check for SCC so we can reset it if needed */ 1072 + if (of_data && of_data->scc_offset && ver >= SDHI_VER_GEN2_SDR104) 1073 + priv->scc_ctl = host->ctl + of_data->scc_offset; 1074 + 1070 1075 /* Enable tuning iff we have an SCC and a supported mode */ 1071 - if (of_data && of_data->scc_offset && 1072 - (host->mmc->caps & MMC_CAP_UHS_SDR104 || 1073 - host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | 1074 - MMC_CAP2_HS400_1_8V))) { 1076 + if (priv->scc_ctl && (host->mmc->caps & MMC_CAP_UHS_SDR104 || 1077 + host->mmc->caps2 & MMC_CAP2_HSX00_1_8V)) { 1075 1078 const struct renesas_sdhi_scc *taps = of_data->taps; 1076 - bool use_4tap = quirks && quirks->hs400_4taps; 1079 + bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 1077 1080 bool hit = false; 1078 1081 1079 1082 for (i = 0; i < of_data->taps_num; i++) { ··· 1093 1092 if (!hit) 1094 1093 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); 1095 1094 1096 - priv->scc_ctl = host->ctl + of_data->scc_offset; 1097 1095 host->check_retune = renesas_sdhi_check_scc_error; 1098 1096 host->ops.execute_tuning = renesas_sdhi_execute_tuning; 1099 1097 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning;

+55 -31

drivers/mmc/host/renesas_sdhi_internal_dmac.c

··· 47 47 #define RST_RESERVED_BITS GENMASK_ULL(31, 0) 48 48 49 49 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */ 50 - #define INFO1_CLEAR 0 51 50 #define INFO1_MASK_CLEAR GENMASK_ULL(31, 0) 52 - #define INFO1_DTRANEND1 BIT(17) 51 + #define INFO1_DTRANEND1 BIT(20) 52 + #define INFO1_DTRANEND1_OLD BIT(17) 53 53 #define INFO1_DTRANEND0 BIT(16) 54 54 55 55 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */ ··· 165 165 .hs400_disabled = true, 166 166 .hs400_4taps = true, 167 167 .dma_one_rx_only = true, 168 + .old_info1_layout = true, 168 169 }; 169 170 170 171 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = { ··· 281 280 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match); 282 281 283 282 static void 284 - renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host, 285 - int addr, u64 val) 286 - { 287 - writeq(val, host->ctl + addr); 288 - } 289 - 290 - static void 291 283 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable) 292 284 { 293 285 struct renesas_sdhi *priv = host_to_priv(host); 286 + u32 dma_irqs = INFO1_DTRANEND0 | 287 + (sdhi_has_quirk(priv, old_info1_layout) ? 288 + INFO1_DTRANEND1_OLD : INFO1_DTRANEND1); 294 289 295 290 if (!host->chan_tx || !host->chan_rx) 296 291 return; 297 292 298 - if (!enable) 299 - renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1, 300 - INFO1_CLEAR); 293 + writel(enable ? ~dma_irqs : INFO1_MASK_CLEAR, host->ctl + DM_CM_INFO1_MASK); 301 294 302 295 if (priv->dma_priv.enable) 303 296 priv->dma_priv.enable(host, enable); ··· 304 309 305 310 renesas_sdhi_internal_dmac_enable_dma(host, false); 306 311 307 - renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 308 - RST_RESERVED_BITS & ~val); 309 - renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 310 - RST_RESERVED_BITS | val); 312 + writel(RST_RESERVED_BITS & ~val, host->ctl + DM_CM_RST); 313 + writel(RST_RESERVED_BITS | val, host->ctl + DM_CM_RST); 311 314 312 315 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 313 316 314 317 renesas_sdhi_internal_dmac_enable_dma(host, true); 315 318 } 316 319 320 + static bool renesas_sdhi_internal_dmac_dma_irq(struct tmio_mmc_host *host) 321 + { 322 + struct renesas_sdhi *priv = host_to_priv(host); 323 + struct renesas_sdhi_dma *dma_priv = &priv->dma_priv; 324 + 325 + u32 dma_irqs = INFO1_DTRANEND0 | 326 + (sdhi_has_quirk(priv, old_info1_layout) ? 327 + INFO1_DTRANEND1_OLD : INFO1_DTRANEND1); 328 + u32 status = readl(host->ctl + DM_CM_INFO1); 329 + 330 + if (status & dma_irqs) { 331 + writel(status ^ dma_irqs, host->ctl + DM_CM_INFO1); 332 + set_bit(SDHI_DMA_END_FLAG_DMA, &dma_priv->end_flags); 333 + if (test_bit(SDHI_DMA_END_FLAG_ACCESS, &dma_priv->end_flags)) 334 + tasklet_schedule(&dma_priv->dma_complete); 335 + } 336 + 337 + return status & dma_irqs; 338 + } 339 + 317 340 static void 318 341 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) 319 342 { 320 343 struct renesas_sdhi *priv = host_to_priv(host); 344 + struct renesas_sdhi_dma *dma_priv = &priv->dma_priv; 321 345 322 - tasklet_schedule(&priv->dma_priv.dma_complete); 346 + set_bit(SDHI_DMA_END_FLAG_ACCESS, &dma_priv->end_flags); 347 + if (test_bit(SDHI_DMA_END_FLAG_DMA, &dma_priv->end_flags) || 348 + host->data->error) 349 + tasklet_schedule(&dma_priv->dma_complete); 323 350 } 324 351 325 352 /* ··· 396 379 struct scatterlist *sg = host->sg_ptr; 397 380 u32 dtran_mode = DTRAN_MODE_BUS_WIDTH; 398 381 399 - if (!(priv->quirks && priv->quirks->fixed_addr_mode)) 382 + if (!sdhi_has_quirk(priv, fixed_addr_mode)) 400 383 dtran_mode |= DTRAN_MODE_ADDR_MODE; 401 384 402 385 if (!renesas_sdhi_internal_dmac_map(host, data, COOKIE_MAPPED)) ··· 404 387 405 388 if (data->flags & MMC_DATA_READ) { 406 389 dtran_mode |= DTRAN_MODE_CH_NUM_CH1; 407 - if (priv->quirks && priv->quirks->dma_one_rx_only && 390 + if (sdhi_has_quirk(priv, dma_one_rx_only) && 408 391 test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags)) 409 392 goto force_pio_with_unmap; 410 393 } else { 411 394 dtran_mode |= DTRAN_MODE_CH_NUM_CH0; 412 395 } 413 396 397 + priv->dma_priv.end_flags = 0; 414 398 renesas_sdhi_internal_dmac_enable_dma(host, true); 415 399 416 400 /* set dma parameters */ 417 - renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE, 418 - dtran_mode); 419 - renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR, 420 - sg_dma_address(sg)); 401 + writel(dtran_mode, host->ctl + DM_CM_DTRAN_MODE); 402 + writel(sg_dma_address(sg), host->ctl + DM_DTRAN_ADDR); 421 403 422 404 host->dma_on = true; 423 405 ··· 432 416 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg) 433 417 { 434 418 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 419 + struct renesas_sdhi *priv = host_to_priv(host); 435 420 436 421 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 437 422 438 - /* start the DMAC */ 439 - renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL, 440 - DTRAN_CTRL_DM_START); 423 + if (!host->cmd->error) { 424 + /* start the DMAC */ 425 + writel(DTRAN_CTRL_DM_START, host->ctl + DM_CM_DTRAN_CTRL); 426 + } else { 427 + /* on CMD errors, simulate DMA end immediately */ 428 + set_bit(SDHI_DMA_END_FLAG_DMA, &priv->dma_priv.end_flags); 429 + if (test_bit(SDHI_DMA_END_FLAG_ACCESS, &priv->dma_priv.end_flags)) 430 + tasklet_schedule(&priv->dma_priv.dma_complete); 431 + } 441 432 } 442 433 443 434 static bool renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host *host) ··· 524 501 { 525 502 struct renesas_sdhi *priv = host_to_priv(host); 526 503 527 - /* Disable DMAC interrupts, we don't use them */ 528 - renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1_MASK, 529 - INFO1_MASK_CLEAR); 530 - renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO2_MASK, 531 - INFO2_MASK_CLEAR); 504 + /* Disable DMAC interrupts initially */ 505 + writel(INFO1_MASK_CLEAR, host->ctl + DM_CM_INFO1_MASK); 506 + writel(INFO2_MASK_CLEAR, host->ctl + DM_CM_INFO2_MASK); 507 + writel(0, host->ctl + DM_CM_INFO1); 508 + writel(0, host->ctl + DM_CM_INFO2); 532 509 533 510 /* Each value is set to non-zero to assume "enabling" each DMA */ 534 511 host->chan_rx = host->chan_tx = (void *)0xdeadbeaf; ··· 560 537 .abort = renesas_sdhi_internal_dmac_abort_dma, 561 538 .dataend = renesas_sdhi_internal_dmac_dataend_dma, 562 539 .end = renesas_sdhi_internal_dmac_end_dma, 540 + .dma_irq = renesas_sdhi_internal_dmac_dma_irq, 563 541 }; 564 542 565 543 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)

+5 -6

drivers/mmc/host/renesas_sdhi_sys_dmac.c

··· 160 160 dma_cookie_t cookie; 161 161 int ret, i; 162 162 bool aligned = true, multiple = true; 163 - unsigned int align = (1 << host->pdata->alignment_shift) - 1; 163 + unsigned int align = 1; /* 2-byte alignment */ 164 164 165 165 for_each_sg(sg, sg_tmp, host->sg_len, i) { 166 166 if (sg_tmp->offset & align) ··· 232 232 dma_cookie_t cookie; 233 233 int ret, i; 234 234 bool aligned = true, multiple = true; 235 - unsigned int align = (1 << host->pdata->alignment_shift) - 1; 235 + unsigned int align = 1; /* 2-byte alignment */ 236 236 237 237 for_each_sg(sg, sg_tmp, host->sg_len, i) { 238 238 if (sg_tmp->offset & align) ··· 254 254 255 255 /* The only sg element can be unaligned, use our bounce buffer then */ 256 256 if (!aligned) { 257 - unsigned long flags; 258 - void *sg_vaddr = tmio_mmc_kmap_atomic(sg, &flags); 257 + void *sg_vaddr = kmap_local_page(sg_page(sg)); 259 258 260 259 sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length); 261 - memcpy(host->bounce_buf, sg_vaddr, host->bounce_sg.length); 262 - tmio_mmc_kunmap_atomic(sg, &flags, sg_vaddr); 260 + memcpy(host->bounce_buf, sg_vaddr + sg->offset, host->bounce_sg.length); 261 + kunmap_local(sg_vaddr); 263 262 host->sg_ptr = &host->bounce_sg; 264 263 sg = host->sg_ptr; 265 264 }

+8 -1

drivers/mmc/host/rtsx_pci_sdmmc.c

··· 1474 1474 struct realtek_pci_sdmmc *host; 1475 1475 struct rtsx_pcr *pcr; 1476 1476 struct pcr_handle *handle = pdev->dev.platform_data; 1477 + int ret; 1477 1478 1478 1479 if (!handle) 1479 1480 return -ENXIO; ··· 1512 1511 pm_runtime_mark_last_busy(&pdev->dev); 1513 1512 pm_runtime_use_autosuspend(&pdev->dev); 1514 1513 1515 - mmc_add_host(mmc); 1514 + ret = mmc_add_host(mmc); 1515 + if (ret) { 1516 + pm_runtime_dont_use_autosuspend(&pdev->dev); 1517 + pm_runtime_disable(&pdev->dev); 1518 + mmc_free_host(mmc); 1519 + return ret; 1520 + } 1516 1521 1517 1522 return 0; 1518 1523 }

+10 -1

drivers/mmc/host/rtsx_usb_sdmmc.c

··· 1329 1329 #ifdef RTSX_USB_USE_LEDS_CLASS 1330 1330 int err; 1331 1331 #endif 1332 + int ret; 1332 1333 1333 1334 ucr = usb_get_intfdata(to_usb_interface(pdev->dev.parent)); 1334 1335 if (!ucr) ··· 1366 1365 INIT_WORK(&host->led_work, rtsx_usb_update_led); 1367 1366 1368 1367 #endif 1369 - mmc_add_host(mmc); 1368 + ret = mmc_add_host(mmc); 1369 + if (ret) { 1370 + #ifdef RTSX_USB_USE_LEDS_CLASS 1371 + led_classdev_unregister(&host->led); 1372 + #endif 1373 + mmc_free_host(mmc); 1374 + pm_runtime_disable(&pdev->dev); 1375 + return ret; 1376 + } 1370 1377 1371 1378 return 0; 1372 1379 }

+2 -2

drivers/mmc/host/sdhci-acpi.c

··· 648 648 * in reading a garbage value and using the wrong presets. 649 649 * 650 650 * Since HS400 and HS200 presets must be identical, we could 651 - * instead use the the SDR104 preset register. 651 + * instead use the SDR104 preset register. 652 652 * 653 653 * If the above issues are resolved we could remove this quirk for 654 - * firmware that that has valid presets (i.e., SDR12 <= 12 MHz). 654 + * firmware that has valid presets (i.e., SDR12 <= 12 MHz). 655 655 */ 656 656 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 657 657

+1 -1

drivers/mmc/host/sdhci-bcm-kona.c

··· 168 168 /* 169 169 * JEDEC and SD spec specify supplying 74 continuous clocks to 170 170 * device after power up. With minimum bus (100KHz) that 171 - * that translates to 740us 171 + * translates to 740us 172 172 */ 173 173 if (power_mode != MMC_POWER_OFF) 174 174 udelay(740);

+1 -1

drivers/mmc/host/sdhci-brcmstb.c

··· 179 179 .ops = &sdhci_brcmstb_ops_7216, 180 180 }; 181 181 182 - static const struct of_device_id sdhci_brcm_of_match[] = { 182 + static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = { 183 183 { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 }, 184 184 { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 }, 185 185 { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 },

+47 -40

drivers/mmc/host/sdhci-esdhc-imx.c

··· 307 307 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 308 308 }; 309 309 static struct esdhc_soc_data usdhc_imxrt1050_data = { 310 - .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_HS200 | ESDHC_FLAG_ERR004536, 310 + .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 311 + | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, 311 312 }; 312 313 313 314 static struct esdhc_soc_data usdhc_imx8qxp_data = { ··· 1013 1012 SDHCI_HOST_CONTROL); 1014 1013 } 1015 1014 1015 + static void esdhc_reset_tuning(struct sdhci_host *host) 1016 + { 1017 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1018 + struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1019 + u32 ctrl; 1020 + int ret; 1021 + 1022 + /* Reset the tuning circuit */ 1023 + if (esdhc_is_usdhc(imx_data)) { 1024 + if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1025 + ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); 1026 + ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1027 + ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 1028 + writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 1029 + writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1030 + } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1031 + ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1032 + ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1033 + ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE; 1034 + writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1035 + /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */ 1036 + ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS, 1037 + ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50); 1038 + if (ret == -ETIMEDOUT) 1039 + dev_warn(mmc_dev(host->mmc), 1040 + "Warning! clear execute tuning bit failed\n"); 1041 + /* 1042 + * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the 1043 + * usdhc IP internal logic flag execute_tuning_with_clr_buf, which 1044 + * will finally make sure the normal data transfer logic correct. 1045 + */ 1046 + ctrl = readl(host->ioaddr + SDHCI_INT_STATUS); 1047 + ctrl |= SDHCI_INT_DATA_AVAIL; 1048 + writel(ctrl, host->ioaddr + SDHCI_INT_STATUS); 1049 + } 1050 + } 1051 + } 1052 + 1016 1053 static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1017 1054 { 1018 1055 struct sdhci_host *host = mmc_priv(mmc); ··· 1062 1023 if (host->timing == MMC_TIMING_UHS_DDR50) 1063 1024 return 0; 1064 1025 1026 + /* 1027 + * Reset tuning circuit logic. If not, the previous tuning result 1028 + * will impact current tuning, make current tuning can't set the 1029 + * correct delay cell. 1030 + */ 1031 + esdhc_reset_tuning(host); 1065 1032 return sdhci_execute_tuning(mmc, opcode); 1066 1033 } 1067 1034 ··· 1239 1194 if (ret == -ETIMEDOUT) 1240 1195 dev_warn(mmc_dev(host->mmc), 1241 1196 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v); 1242 - } 1243 - 1244 - static void esdhc_reset_tuning(struct sdhci_host *host) 1245 - { 1246 - struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1247 - struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1248 - u32 ctrl; 1249 - int ret; 1250 - 1251 - /* Reset the tuning circuit */ 1252 - if (esdhc_is_usdhc(imx_data)) { 1253 - if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1254 - ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); 1255 - ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1256 - ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 1257 - writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 1258 - writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1259 - } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1260 - ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1261 - ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1262 - ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE; 1263 - writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1264 - /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */ 1265 - ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS, 1266 - ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50); 1267 - if (ret == -ETIMEDOUT) 1268 - dev_warn(mmc_dev(host->mmc), 1269 - "Warning! clear execute tuning bit failed\n"); 1270 - /* 1271 - * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the 1272 - * usdhc IP internal logic flag execute_tuning_with_clr_buf, which 1273 - * will finally make sure the normal data transfer logic correct. 1274 - */ 1275 - ctrl = readl(host->ioaddr + SDHCI_INT_STATUS); 1276 - ctrl |= SDHCI_INT_DATA_AVAIL; 1277 - writel(ctrl, host->ioaddr + SDHCI_INT_STATUS); 1278 - } 1279 - } 1280 1197 } 1281 1198 1282 1199 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) ··· 1461 1454 1462 1455 /* 1463 1456 * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card 1464 - * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let the 1457 + * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let 1465 1458 * the 1st linux configure power/clock for the 2nd Linux. 1466 1459 * 1467 1460 * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux

+3 -10

drivers/mmc/host/sdhci-msm.c

··· 19 19 #include <linux/pinctrl/consumer.h> 20 20 #include <linux/reset.h> 21 21 22 + #include "sdhci-cqhci.h" 22 23 #include "sdhci-pltfm.h" 23 24 #include "cqhci.h" 24 25 ··· 2219 2218 if (!msm_host->use_cdr) 2220 2219 break; 2221 2220 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) && 2222 - SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK_HS200 && 2223 - SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK) 2221 + !mmc_op_tuning(SDHCI_GET_CMD(val))) 2224 2222 sdhci_msm_set_cdr(host, true); 2225 2223 else 2226 2224 sdhci_msm_set_cdr(host, false); ··· 2302 2302 } 2303 2303 msm_host->caps_0 |= caps; 2304 2304 pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps); 2305 - } 2306 - 2307 - static void sdhci_msm_reset(struct sdhci_host *host, u8 mask) 2308 - { 2309 - if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL)) 2310 - cqhci_deactivate(host->mmc); 2311 - sdhci_reset(host, mask); 2312 2305 } 2313 2306 2314 2307 static int sdhci_msm_register_vreg(struct sdhci_msm_host *msm_host) ··· 2443 2450 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); 2444 2451 2445 2452 static const struct sdhci_ops sdhci_msm_ops = { 2446 - .reset = sdhci_msm_reset, 2453 + .reset = sdhci_and_cqhci_reset, 2447 2454 .set_clock = sdhci_msm_set_clock, 2448 2455 .get_min_clock = sdhci_msm_get_min_clock, 2449 2456 .get_max_clock = sdhci_msm_get_max_clock,

+69

drivers/mmc/host/sdhci-of-arasan.c

··· 21 21 #include <linux/of_device.h> 22 22 #include <linux/phy/phy.h> 23 23 #include <linux/regmap.h> 24 + #include <linux/reset.h> 24 25 #include <linux/of.h> 25 26 #include <linux/firmware/xlnx-zynqmp.h> 26 27 ··· 1523 1522 return 0; 1524 1523 } 1525 1524 1525 + static int sdhci_zynqmp_set_dynamic_config(struct device *dev, 1526 + struct sdhci_arasan_data *sdhci_arasan) 1527 + { 1528 + struct sdhci_host *host = sdhci_arasan->host; 1529 + struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw; 1530 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1531 + const char *clk_name = clk_hw_get_name(hw); 1532 + u32 mhz, node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1; 1533 + struct reset_control *rstc; 1534 + int ret; 1535 + 1536 + /* Obtain SDHC reset control */ 1537 + rstc = devm_reset_control_get_optional_exclusive(dev, NULL); 1538 + if (IS_ERR(rstc)) { 1539 + dev_err(dev, "Cannot get SDHC reset.\n"); 1540 + return PTR_ERR(rstc); 1541 + } 1542 + 1543 + ret = reset_control_assert(rstc); 1544 + if (ret) 1545 + return ret; 1546 + 1547 + ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_FIXED, 0); 1548 + if (ret) 1549 + return ret; 1550 + 1551 + ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_EMMC_SEL, 1552 + !!(host->mmc->caps & MMC_CAP_NONREMOVABLE)); 1553 + if (ret) 1554 + return ret; 1555 + 1556 + mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000); 1557 + if (mhz > 100 && mhz <= 200) 1558 + mhz = 200; 1559 + else if (mhz > 50 && mhz <= 100) 1560 + mhz = 100; 1561 + else if (mhz > 25 && mhz <= 50) 1562 + mhz = 50; 1563 + else 1564 + mhz = 25; 1565 + 1566 + ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_BASECLK, mhz); 1567 + if (ret) 1568 + return ret; 1569 + 1570 + ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_8BIT, 1571 + !!(host->mmc->caps & MMC_CAP_8_BIT_DATA)); 1572 + if (ret) 1573 + return ret; 1574 + 1575 + ret = reset_control_deassert(rstc); 1576 + if (ret) 1577 + return ret; 1578 + 1579 + usleep_range(1000, 1500); 1580 + 1581 + return 0; 1582 + } 1583 + 1526 1584 static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan) 1527 1585 { 1528 1586 struct sdhci_host *host = sdhci_arasan->host; ··· 1744 1684 if (ret) { 1745 1685 ret = dev_err_probe(dev, ret, "parsing dt failed.\n"); 1746 1686 goto unreg_clk; 1687 + } 1688 + 1689 + if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) { 1690 + ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_SD_CONFIG); 1691 + if (!ret) { 1692 + ret = sdhci_zynqmp_set_dynamic_config(dev, sdhci_arasan); 1693 + if (ret) 1694 + goto unreg_clk; 1695 + } 1747 1696 } 1748 1697 1749 1698 sdhci_arasan->phy = ERR_PTR(-ENODEV);

+9 -2

drivers/mmc/host/sdhci-of-esdhc.c

··· 42 42 .max_clk[MMC_TIMING_SD_HS] = 46500000, 43 43 }; 44 44 45 + static const struct esdhc_clk_fixup ls1043a_esdhc_clk = { 46 + .sd_dflt_max_clk = 25000000, 47 + .max_clk[MMC_TIMING_UHS_SDR104] = 116700000, 48 + .max_clk[MMC_TIMING_MMC_HS200] = 116700000, 49 + }; 50 + 45 51 static const struct esdhc_clk_fixup ls1046a_esdhc_clk = { 46 52 .sd_dflt_max_clk = 25000000, 47 53 .max_clk[MMC_TIMING_UHS_SDR104] = 167000000, ··· 69 63 70 64 static const struct of_device_id sdhci_esdhc_of_match[] = { 71 65 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk}, 66 + { .compatible = "fsl,ls1043a-esdhc", .data = &ls1043a_esdhc_clk}, 72 67 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk}, 73 68 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk}, 74 69 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk}, ··· 98 91 }; 99 92 100 93 /** 101 - * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register 94 + * esdhc_readl_fixup - Fixup the value read from incompatible eSDHC register 102 95 * to make it compatible with SD spec. 103 96 * 104 97 * @host: pointer to sdhci_host ··· 223 216 } 224 217 225 218 /** 226 - * esdhc_write*_fixup - Fixup the SD spec register value so that it could be 219 + * esdhc_writel_fixup - Fixup the SD spec register value so that it could be 227 220 * written into eSDHC register. 228 221 * 229 222 * @host: pointer to sdhci_host

+1 -1

drivers/mmc/host/sdhci-omap.c

··· 370 370 371 371 /* 372 372 * Stage 1: Search for a maximum pass window ignoring any 373 - * any single point failures. If the tuning value ends up 373 + * single point failures. If the tuning value ends up 374 374 * near it, move away from it in stage 2 below 375 375 */ 376 376 while (phase_delay <= MAX_PHASE_DELAY) {

+4 -10

drivers/mmc/host/sdhci-pci-core.c

··· 38 38 #include "cqhci.h" 39 39 40 40 #include "sdhci.h" 41 + #include "sdhci-cqhci.h" 41 42 #include "sdhci-pci.h" 42 43 43 44 static void sdhci_pci_hw_reset(struct sdhci_host *host); ··· 233 232 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 234 233 { 235 234 sdhci_dumpregs(mmc_priv(mmc)); 236 - } 237 - 238 - static void sdhci_cqhci_reset(struct sdhci_host *host, u8 mask) 239 - { 240 - if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && 241 - host->mmc->cqe_private) 242 - cqhci_deactivate(host->mmc); 243 - sdhci_reset(host, mask); 244 235 } 245 236 246 237 /*****************************************************************************\ ··· 696 703 .set_power = sdhci_intel_set_power, 697 704 .enable_dma = sdhci_pci_enable_dma, 698 705 .set_bus_width = sdhci_set_bus_width, 699 - .reset = sdhci_cqhci_reset, 706 + .reset = sdhci_and_cqhci_reset, 700 707 .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 701 708 .hw_reset = sdhci_pci_hw_reset, 702 709 .irq = sdhci_cqhci_irq, ··· 2276 2283 .probe = sdhci_pci_probe, 2277 2284 .remove = sdhci_pci_remove, 2278 2285 .driver = { 2279 - .pm = &sdhci_pci_pm_ops 2286 + .pm = &sdhci_pci_pm_ops, 2287 + .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2280 2288 }, 2281 2289 }; 2282 2290

+2 -9

drivers/mmc/host/sdhci-pci-gli.c

··· 15 15 #include <linux/of.h> 16 16 #include <linux/iopoll.h> 17 17 #include "sdhci.h" 18 + #include "sdhci-cqhci.h" 18 19 #include "sdhci-pci.h" 19 20 #include "cqhci.h" 20 21 ··· 923 922 return ret; 924 923 } 925 924 926 - static void sdhci_gl9763e_reset(struct sdhci_host *host, u8 mask) 927 - { 928 - if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && 929 - host->mmc->cqe_private) 930 - cqhci_deactivate(host->mmc); 931 - sdhci_reset(host, mask); 932 - } 933 - 934 925 static void gli_set_gl9763e(struct sdhci_pci_slot *slot) 935 926 { 936 927 struct pci_dev *pdev = slot->chip->pdev; ··· 1129 1136 .set_clock = sdhci_set_clock, 1130 1137 .enable_dma = sdhci_pci_enable_dma, 1131 1138 .set_bus_width = sdhci_set_bus_width, 1132 - .reset = sdhci_gl9763e_reset, 1139 + .reset = sdhci_and_cqhci_reset, 1133 1140 .set_uhs_signaling = sdhci_set_gl9763e_signaling, 1134 1141 .voltage_switch = sdhci_gli_voltage_switch, 1135 1142 .irq = sdhci_gl9763e_cqhci_irq,

+1 -2

drivers/mmc/host/sdhci-pci-o2micro.c

··· 326 326 (host->timing != MMC_TIMING_UHS_SDR50)) 327 327 return sdhci_execute_tuning(mmc, opcode); 328 328 329 - if (WARN_ON((opcode != MMC_SEND_TUNING_BLOCK_HS200) && 330 - (opcode != MMC_SEND_TUNING_BLOCK))) 329 + if (WARN_ON(!mmc_op_tuning(opcode))) 331 330 return -EINVAL; 332 331 333 332 /* Force power mode enter L0 */

+9 -7

drivers/mmc/host/sdhci-sprd.c

··· 228 228 div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8); 229 229 sdhci_enable_clk(host, div); 230 230 231 - /* enable auto gate sdhc_enable_auto_gate */ 232 - val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); 233 - mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | 234 - SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; 235 - if (mask != (val & mask)) { 236 - val |= mask; 237 - sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); 231 + /* Enable CLK_AUTO when the clock is greater than 400K. */ 232 + if (clk > 400000) { 233 + val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); 234 + mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | 235 + SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; 236 + if (mask != (val & mask)) { 237 + val |= mask; 238 + sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); 239 + } 238 240 } 239 241 } 240 242

+61 -20

drivers/mmc/host/sdhci-tegra.c

··· 3 3 * Copyright (C) 2010 Google, Inc. 4 4 */ 5 5 6 + #include <linux/bitfield.h> 7 + #include <linux/clk.h> 6 8 #include <linux/delay.h> 7 9 #include <linux/dma-mapping.h> 8 10 #include <linux/err.h> 9 - #include <linux/module.h> 11 + #include <linux/gpio/consumer.h> 10 12 #include <linux/init.h> 11 - #include <linux/iopoll.h> 12 - #include <linux/platform_device.h> 13 - #include <linux/clk.h> 14 13 #include <linux/io.h> 15 - #include <linux/of.h> 16 - #include <linux/of_device.h> 17 - #include <linux/pinctrl/consumer.h> 18 - #include <linux/pm_opp.h> 19 - #include <linux/pm_runtime.h> 20 - #include <linux/regulator/consumer.h> 21 - #include <linux/reset.h> 14 + #include <linux/iommu.h> 15 + #include <linux/iopoll.h> 16 + #include <linux/ktime.h> 22 17 #include <linux/mmc/card.h> 23 18 #include <linux/mmc/host.h> 24 19 #include <linux/mmc/mmc.h> 25 20 #include <linux/mmc/slot-gpio.h> 26 - #include <linux/gpio/consumer.h> 27 - #include <linux/ktime.h> 21 + #include <linux/module.h> 22 + #include <linux/of_device.h> 23 + #include <linux/of.h> 24 + #include <linux/pinctrl/consumer.h> 25 + #include <linux/platform_device.h> 26 + #include <linux/pm_opp.h> 27 + #include <linux/pm_runtime.h> 28 + #include <linux/regulator/consumer.h> 29 + #include <linux/reset.h> 28 30 29 31 #include <soc/tegra/common.h> 30 32 ··· 97 95 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 98 96 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 99 97 98 + #define SDHCI_TEGRA_CIF2AXI_CTRL_0 0x1fc 99 + 100 100 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 101 101 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 102 102 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) ··· 126 122 #define NVQUIRK_HAS_TMCLK BIT(10) 127 123 128 124 #define NVQUIRK_HAS_ANDROID_GPT_SECTOR BIT(11) 125 + #define NVQUIRK_PROGRAM_STREAMID BIT(12) 129 126 130 127 /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */ 131 128 #define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000 ··· 183 178 bool enable_hwcq; 184 179 unsigned long curr_clk_rate; 185 180 u8 tuned_tap_delay; 181 + u32 stream_id; 186 182 }; 187 183 188 184 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) ··· 274 268 { 275 269 bool is_tuning_cmd = 0; 276 270 bool clk_enabled; 277 - u8 cmd; 278 271 279 - if (reg == SDHCI_COMMAND) { 280 - cmd = SDHCI_GET_CMD(val); 281 - is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK || 282 - cmd == MMC_SEND_TUNING_BLOCK_HS200; 283 - } 272 + if (reg == SDHCI_COMMAND) 273 + is_tuning_cmd = mmc_op_tuning(SDHCI_GET_CMD(val)); 284 274 285 275 if (is_tuning_cmd) 286 276 clk_enabled = tegra_sdhci_configure_card_clk(host, 0); ··· 1528 1526 SDHCI_QUIRK_NO_HISPD_BIT | 1529 1527 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1530 1528 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1531 - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1529 + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1530 + SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER, 1532 1531 .ops = &tegra186_sdhci_ops, 1533 1532 }; 1534 1533 ··· 1560 1557 .max_tap_delay = 139, 1561 1558 }; 1562 1559 1560 + static const struct sdhci_tegra_soc_data soc_data_tegra234 = { 1561 + .pdata = &sdhci_tegra186_pdata, 1562 + .dma_mask = DMA_BIT_MASK(39), 1563 + .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1564 + NVQUIRK_HAS_PADCALIB | 1565 + NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1566 + NVQUIRK_ENABLE_SDR50 | 1567 + NVQUIRK_ENABLE_SDR104 | 1568 + NVQUIRK_PROGRAM_STREAMID | 1569 + NVQUIRK_HAS_TMCLK, 1570 + .min_tap_delay = 95, 1571 + .max_tap_delay = 111, 1572 + }; 1573 + 1563 1574 static const struct of_device_id sdhci_tegra_dt_match[] = { 1575 + { .compatible = "nvidia,tegra234-sdhci", .data = &soc_data_tegra234 }, 1564 1576 { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 }, 1565 1577 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 1566 1578 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, ··· 1633 1615 cleanup: 1634 1616 sdhci_cleanup_host(host); 1635 1617 return ret; 1618 + } 1619 + 1620 + /* Program MC streamID for DMA transfers */ 1621 + static void sdhci_tegra_program_stream_id(struct sdhci_host *host) 1622 + { 1623 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1624 + struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1625 + 1626 + if (tegra_host->soc_data->nvquirks & NVQUIRK_PROGRAM_STREAMID) { 1627 + tegra_sdhci_writel(host, FIELD_PREP(GENMASK(15, 8), tegra_host->stream_id) | 1628 + FIELD_PREP(GENMASK(7, 0), tegra_host->stream_id), 1629 + SDHCI_TEGRA_CIF2AXI_CTRL_0); 1630 + } 1636 1631 } 1637 1632 1638 1633 static int sdhci_tegra_probe(struct platform_device *pdev) ··· 1707 1676 host->mmc->caps |= MMC_CAP_CD_WAKE; 1708 1677 1709 1678 tegra_sdhci_parse_dt(host); 1679 + 1680 + if (tegra_host->soc_data->nvquirks & NVQUIRK_PROGRAM_STREAMID && 1681 + !tegra_dev_iommu_get_stream_id(&pdev->dev, &tegra_host->stream_id)) { 1682 + dev_warn(mmc_dev(host->mmc), "missing IOMMU stream ID\n"); 1683 + tegra_host->stream_id = 0x7f; 1684 + } 1710 1685 1711 1686 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 1712 1687 GPIOD_OUT_HIGH); ··· 1798 1761 rc = sdhci_tegra_add_host(host); 1799 1762 if (rc) 1800 1763 goto err_add_host; 1764 + 1765 + sdhci_tegra_program_stream_id(host); 1801 1766 1802 1767 return 0; 1803 1768 ··· 1896 1857 ret = pm_runtime_force_resume(dev); 1897 1858 if (ret) 1898 1859 return ret; 1860 + 1861 + sdhci_tegra_program_stream_id(host); 1899 1862 1900 1863 ret = sdhci_resume_host(host); 1901 1864 if (ret)

+31 -54

drivers/mmc/host/sdhci.c

··· 270 270 271 271 static void sdhci_reset_for_reason(struct sdhci_host *host, enum sdhci_reset_reason reason) 272 272 { 273 + if (host->quirks2 & SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER) { 274 + sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 275 + return; 276 + } 277 + 273 278 switch (reason) { 274 279 case SDHCI_RESET_FOR_INIT: 275 280 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); ··· 531 526 532 527 static void sdhci_read_block_pio(struct sdhci_host *host) 533 528 { 534 - unsigned long flags; 535 529 size_t blksize, len, chunk; 536 530 u32 scratch; 537 531 u8 *buf; ··· 539 535 540 536 blksize = host->data->blksz; 541 537 chunk = 0; 542 - 543 - local_irq_save(flags); 544 538 545 539 while (blksize) { 546 540 BUG_ON(!sg_miter_next(&host->sg_miter)); ··· 566 564 } 567 565 568 566 sg_miter_stop(&host->sg_miter); 569 - 570 - local_irq_restore(flags); 571 567 } 572 568 573 569 static void sdhci_write_block_pio(struct sdhci_host *host) 574 570 { 575 - unsigned long flags; 576 571 size_t blksize, len, chunk; 577 572 u32 scratch; 578 573 u8 *buf; ··· 579 580 blksize = host->data->blksz; 580 581 chunk = 0; 581 582 scratch = 0; 582 - 583 - local_irq_save(flags); 584 583 585 584 while (blksize) { 586 585 BUG_ON(!sg_miter_next(&host->sg_miter)); ··· 606 609 } 607 610 608 611 sg_miter_stop(&host->sg_miter); 609 - 610 - local_irq_restore(flags); 611 612 } 612 613 613 614 static void sdhci_transfer_pio(struct sdhci_host *host) ··· 701 706 return sg_count; 702 707 } 703 708 704 - static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 709 + static char *sdhci_kmap_atomic(struct scatterlist *sg) 705 710 { 706 - local_irq_save(*flags); 707 - return kmap_atomic(sg_page(sg)) + sg->offset; 711 + return kmap_local_page(sg_page(sg)) + sg->offset; 708 712 } 709 713 710 - static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 714 + static void sdhci_kunmap_atomic(void *buffer) 711 715 { 712 - kunmap_atomic(buffer); 713 - local_irq_restore(*flags); 716 + kunmap_local(buffer); 714 717 } 715 718 716 719 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, ··· 750 757 struct mmc_data *data, int sg_count) 751 758 { 752 759 struct scatterlist *sg; 753 - unsigned long flags; 754 760 dma_addr_t addr, align_addr; 755 761 void *desc, *align; 756 762 char *buffer; ··· 781 789 SDHCI_ADMA2_MASK; 782 790 if (offset) { 783 791 if (data->flags & MMC_DATA_WRITE) { 784 - buffer = sdhci_kmap_atomic(sg, &flags); 792 + buffer = sdhci_kmap_atomic(sg); 785 793 memcpy(align, buffer, offset); 786 - sdhci_kunmap_atomic(buffer, &flags); 794 + sdhci_kunmap_atomic(buffer); 787 795 } 788 796 789 797 /* tran, valid */ ··· 844 852 int i, size; 845 853 void *align; 846 854 char *buffer; 847 - unsigned long flags; 848 855 849 856 if (data->flags & MMC_DATA_READ) { 850 857 bool has_unaligned = false; ··· 866 875 size = SDHCI_ADMA2_ALIGN - 867 876 (sg_dma_address(sg) & SDHCI_ADMA2_MASK); 868 877 869 - buffer = sdhci_kmap_atomic(sg, &flags); 878 + buffer = sdhci_kmap_atomic(sg); 870 879 memcpy(buffer, align, size); 871 - sdhci_kunmap_atomic(buffer, &flags); 880 + sdhci_kunmap_atomic(buffer); 872 881 873 882 align += SDHCI_ADMA2_ALIGN; 874 883 } ··· 1457 1466 if (host->quirks2 & 1458 1467 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) { 1459 1468 /* must not clear SDHCI_TRANSFER_MODE when tuning */ 1460 - if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) 1469 + if (!mmc_op_tuning(cmd->opcode)) 1461 1470 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 1462 1471 } else { 1463 1472 /* clear Auto CMD settings for no data CMDs */ ··· 1698 1707 flags |= SDHCI_CMD_INDEX; 1699 1708 1700 1709 /* CMD19 is special in that the Data Present Select should be set */ 1701 - if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1702 - cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 1710 + if (cmd->data || mmc_op_tuning(cmd->opcode)) 1703 1711 flags |= SDHCI_CMD_DATA; 1704 1712 1705 1713 timeout = jiffies; ··· 2294 2304 case MMC_TIMING_UHS_DDR50: 2295 2305 case MMC_TIMING_MMC_DDR52: 2296 2306 return true; 2297 - }; 2307 + } 2298 2308 return false; 2299 2309 } 2300 2310 ··· 2408 2418 if (host->version >= SDHCI_SPEC_300) { 2409 2419 u16 clk, ctrl_2; 2410 2420 2421 + /* 2422 + * According to SDHCI Spec v3.00, if the Preset Value 2423 + * Enable in the Host Control 2 register is set, we 2424 + * need to reset SD Clock Enable before changing High 2425 + * Speed Enable to avoid generating clock glitches. 2426 + */ 2427 + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 2428 + if (clk & SDHCI_CLOCK_CARD_EN) { 2429 + clk &= ~SDHCI_CLOCK_CARD_EN; 2430 + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 2431 + } 2432 + 2433 + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 2434 + 2411 2435 if (!host->preset_enabled) { 2412 - sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 2413 2436 /* 2414 2437 * We only need to set Driver Strength if the 2415 2438 * preset value enable is not set. ··· 2445 2442 2446 2443 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 2447 2444 host->drv_type = ios->drv_type; 2448 - } else { 2449 - /* 2450 - * According to SDHC Spec v3.00, if the Preset Value 2451 - * Enable in the Host Control 2 register is set, we 2452 - * need to reset SD Clock Enable before changing High 2453 - * Speed Enable to avoid generating clock gliches. 2454 - */ 2455 - 2456 - /* Reset SD Clock Enable */ 2457 - clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 2458 - clk &= ~SDHCI_CLOCK_CARD_EN; 2459 - sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 2460 - 2461 - sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 2462 - 2463 - /* Re-enable SD Clock */ 2464 - host->ops->set_clock(host, host->clock); 2465 2445 } 2466 - 2467 - /* Reset SD Clock Enable */ 2468 - clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 2469 - clk &= ~SDHCI_CLOCK_CARD_EN; 2470 - sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 2471 2446 2472 2447 host->ops->set_uhs_signaling(host, ios->timing); 2473 2448 host->timing = ios->timing; ··· 3369 3388 3370 3389 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 3371 3390 { 3372 - u32 command; 3373 - 3374 3391 /* 3375 3392 * CMD19 generates _only_ Buffer Read Ready interrupt if 3376 3393 * use sdhci_send_tuning. ··· 3377 3398 * SDHCI_INT_DATA_AVAIL always there, stuck in irq storm. 3378 3399 */ 3379 3400 if (intmask & SDHCI_INT_DATA_AVAIL && !host->data) { 3380 - command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 3381 - if (command == MMC_SEND_TUNING_BLOCK || 3382 - command == MMC_SEND_TUNING_BLOCK_HS200) { 3401 + if (mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)))) { 3383 3402 host->tuning_done = 1; 3384 3403 wake_up(&host->buf_ready_int); 3385 3404 return;

+3 -1

drivers/mmc/host/sdhci.h

··· 345 345 */ 346 346 #define SDHCI_MAX_SEGS 128 347 347 348 - /* Allow for a a command request and a data request at the same time */ 348 + /* Allow for a command request and a data request at the same time */ 349 349 #define SDHCI_MAX_MRQS 2 350 350 351 351 /* ··· 478 478 * block count. 479 479 */ 480 480 #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) 481 + /* Issue CMD and DATA reset together */ 482 + #define SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER (1<<19) 481 483 482 484 int irq; /* Device IRQ */ 483 485 void __iomem *ioaddr; /* Mapped address */

+1 -1

drivers/mmc/host/sdhci_am654.c

··· 836 836 837 837 ret = mmc_of_parse(host->mmc); 838 838 if (ret) { 839 - dev_err(dev, "parsing dt failed (%d)\n", ret); 839 + dev_err_probe(dev, ret, "parsing dt failed\n"); 840 840 goto pm_runtime_put; 841 841 } 842 842

+29 -2

drivers/mmc/host/sdhci_f_sdh30.c

··· 5 5 * Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd 6 6 * Vincent Yang <vincent.yang@tw.fujitsu.com> 7 7 * Copyright (C) 2015 Linaro Ltd Andy Green <andy.green@linaro.org> 8 + * Copyright (C) 2019 Socionext Inc. 8 9 */ 9 10 10 11 #include <linux/acpi.h> ··· 15 14 #include <linux/of.h> 16 15 #include <linux/property.h> 17 16 #include <linux/clk.h> 17 + #include <linux/reset.h> 18 18 19 19 #include "sdhci-pltfm.h" 20 20 #include "sdhci_f_sdh30.h" ··· 23 21 struct f_sdhost_priv { 24 22 struct clk *clk_iface; 25 23 struct clk *clk; 24 + struct reset_control *rst; 26 25 u32 vendor_hs200; 27 26 struct device *dev; 28 27 bool enable_cmd_dat_delay; ··· 76 73 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); 77 74 ctl |= F_SDH30_CMD_DAT_DELAY; 78 75 sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL); 76 + } 77 + 78 + if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) && 79 + !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { 80 + ctl = sdhci_readl(host, F_SDH30_TEST); 81 + ctl |= F_SDH30_FORCE_CARD_INSERT; 82 + sdhci_writel(host, ctl, F_SDH30_TEST); 79 83 } 80 84 } 81 85 ··· 160 150 ret = clk_prepare_enable(priv->clk); 161 151 if (ret) 162 152 goto err_clk; 153 + 154 + priv->rst = devm_reset_control_get_optional_shared(dev, NULL); 155 + if (IS_ERR(priv->rst)) { 156 + ret = PTR_ERR(priv->rst); 157 + goto err_rst; 158 + } 159 + 160 + ret = reset_control_deassert(priv->rst); 161 + if (ret) 162 + goto err_rst; 163 163 } 164 164 165 165 /* init vendor specific regs */ ··· 188 168 if (reg & SDHCI_CAN_DO_8BIT) 189 169 priv->vendor_hs200 = F_SDH30_EMMC_HS200; 190 170 171 + if (!(reg & SDHCI_TIMEOUT_CLK_MASK)) 172 + host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 173 + 191 174 ret = sdhci_add_host(host); 192 175 if (ret) 193 176 goto err_add_host; ··· 198 175 return 0; 199 176 200 177 err_add_host: 178 + reset_control_assert(priv->rst); 179 + err_rst: 201 180 clk_disable_unprepare(priv->clk); 202 181 err_clk: 203 182 clk_disable_unprepare(priv->clk_iface); ··· 216 191 sdhci_remove_host(host, readl(host->ioaddr + SDHCI_INT_STATUS) == 217 192 0xffffffff); 218 193 219 - clk_disable_unprepare(priv->clk_iface); 194 + reset_control_assert(priv->rst); 220 195 clk_disable_unprepare(priv->clk); 196 + clk_disable_unprepare(priv->clk_iface); 221 197 222 198 sdhci_free_host(host); 223 199 platform_set_drvdata(pdev, NULL); ··· 229 203 #ifdef CONFIG_OF 230 204 static const struct of_device_id f_sdh30_dt_ids[] = { 231 205 { .compatible = "fujitsu,mb86s70-sdhci-3.0" }, 206 + { .compatible = "socionext,f-sdh30-e51-mmc" }, 232 207 { /* sentinel */ } 233 208 }; 234 209 MODULE_DEVICE_TABLE(of, f_sdh30_dt_ids); ··· 259 232 260 233 MODULE_DESCRIPTION("F_SDH30 SD Card Controller driver"); 261 234 MODULE_LICENSE("GPL v2"); 262 - MODULE_AUTHOR("FUJITSU SEMICONDUCTOR LTD."); 235 + MODULE_AUTHOR("FUJITSU SEMICONDUCTOR LTD., Socionext Inc."); 263 236 MODULE_ALIAS("platform:f_sdh30");

+3

drivers/mmc/host/sdhci_f_sdh30.h

··· 29 29 #define F_SDH30_CMD_DAT_DELAY BIT(9) 30 30 #define F_SDH30_EMMC_HS200 BIT(24) 31 31 32 + #define F_SDH30_TEST 0x158 33 + #define F_SDH30_FORCE_CARD_INSERT BIT(6) 34 + 32 35 #define F_SDH30_MIN_CLOCK 400000

+1000

drivers/mmc/host/sunplus-mmc.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Copyright (c) Sunplus Inc. 4 + * Author: Tony Huang <tonyhuang.sunplus@gmail.com> 5 + * Author: Li-hao Kuo <lhjeff911@gmail.com> 6 + */ 7 + 8 + #include <linux/bitfield.h> 9 + #include <linux/clk.h> 10 + #include <linux/delay.h> 11 + #include <linux/dma-mapping.h> 12 + #include <linux/interrupt.h> 13 + #include <linux/iopoll.h> 14 + #include <linux/mmc/core.h> 15 + #include <linux/mmc/host.h> 16 + #include <linux/mmc/mmc.h> 17 + #include <linux/mmc/sdio.h> 18 + #include <linux/mmc/slot-gpio.h> 19 + #include <linux/module.h> 20 + #include <linux/of.h> 21 + #include <linux/platform_device.h> 22 + #include <linux/pm.h> 23 + #include <linux/pm_runtime.h> 24 + #include <linux/reset.h> 25 + 26 + #define SPMMC_MIN_CLK 400000 27 + #define SPMMC_MAX_CLK 52000000 28 + #define SPMMC_MAX_BLK_COUNT 65536 29 + #define SPMMC_MAX_TUNABLE_DLY 7 30 + #define SPMMC_TIMEOUT_US 500000 31 + #define SPMMC_POLL_DELAY_US 10 32 + 33 + #define SPMMC_CARD_MEDIATYPE_SRCDST_REG 0x0000 34 + #define SPMMC_MEDIA_TYPE GENMASK(2, 0) 35 + #define SPMMC_DMA_SOURCE GENMASK(6, 4) 36 + #define SPMMC_DMA_DESTINATION GENMASK(10, 8) 37 + #define SPMMC_MEDIA_NONE 0 38 + #define SPMMC_MEDIA_SD 6 39 + #define SPMMC_MEDIA_MS 7 40 + 41 + #define SPMMC_SDRAM_SECTOR_0_SIZE_REG 0x0008 42 + #define SPMMC_DMA_BASE_ADDR_REG 0x000C 43 + #define SPMMC_HW_DMA_CTRL_REG 0x0010 44 + #define SPMMC_HW_DMA_RST BIT(9) 45 + #define SPMMC_DMAIDLE BIT(10) 46 + 47 + #define SPMMC_MAX_DMA_MEMORY_SECTORS 8 48 + 49 + #define SPMMC_SDRAM_SECTOR_1_ADDR_REG 0x0018 50 + #define SPMMC_SDRAM_SECTOR_1_LENG_REG 0x001C 51 + #define SPMMC_SDRAM_SECTOR_2_ADDR_REG 0x0020 52 + #define SPMMC_SDRAM_SECTOR_2_LENG_REG 0x0024 53 + #define SPMMC_SDRAM_SECTOR_3_ADDR_REG 0x0028 54 + #define SPMMC_SDRAM_SECTOR_3_LENG_REG 0x002C 55 + #define SPMMC_SDRAM_SECTOR_4_ADDR_REG 0x0030 56 + #define SPMMC_SDRAM_SECTOR_4_LENG_REG 0x0034 57 + #define SPMMC_SDRAM_SECTOR_5_ADDR_REG 0x0038 58 + #define SPMMC_SDRAM_SECTOR_5_LENG_REG 0x003C 59 + #define SPMMC_SDRAM_SECTOR_6_ADDR_REG 0x0040 60 + #define SPMMC_SDRAM_SECTOR_6_LENG_REG 0x0044 61 + #define SPMMC_SDRAM_SECTOR_7_ADDR_REG 0x0048 62 + #define SPMMC_SDRAM_SECTOR_7_LENG_REG 0x004C 63 + 64 + #define SPMMC_SD_INT_REG 0x0088 65 + #define SPMMC_SDINT_SDCMPEN BIT(0) 66 + #define SPMMC_SDINT_SDCMP BIT(1) 67 + #define SPMMC_SDINT_SDCMPCLR BIT(2) 68 + #define SPMMC_SDINT_SDIOEN BIT(3) 69 + #define SPMMC_SDINT_SDIO BIT(4) 70 + #define SPMMC_SDINT_SDIOCLR BIT(5) 71 + 72 + #define SPMMC_SD_PAGE_NUM_REG 0x008C 73 + 74 + #define SPMMC_SD_CONFIG0_REG 0x0090 75 + #define SPMMC_SD_PIO_MODE BIT(0) 76 + #define SPMMC_SD_DDR_MODE BIT(1) 77 + #define SPMMC_SD_LEN_MODE BIT(2) 78 + #define SPMMC_SD_TRANS_MODE GENMASK(5, 4) 79 + #define SPMMC_SD_AUTO_RESPONSE BIT(6) 80 + #define SPMMC_SD_CMD_DUMMY BIT(7) 81 + #define SPMMC_SD_RSP_CHK_EN BIT(8) 82 + #define SPMMC_SDIO_MODE BIT(9) 83 + #define SPMMC_SD_MMC_MODE BIT(10) 84 + #define SPMMC_SD_DATA_WD BIT(11) 85 + #define SPMMC_RX4_EN BIT(14) 86 + #define SPMMC_SD_RSP_TYPE BIT(15) 87 + #define SPMMC_MMC8_EN BIT(18) 88 + #define SPMMC_CLOCK_DIVISION GENMASK(31, 20) 89 + 90 + #define SPMMC_SDIO_CTRL_REG 0x0094 91 + #define SPMMC_INT_MULTI_TRIG BIT(6) 92 + 93 + #define SPMMC_SD_RST_REG 0x0098 94 + #define SPMMC_SD_CTRL_REG 0x009C 95 + #define SPMMC_NEW_COMMAND_TRIGGER BIT(0) 96 + #define SPMMC_DUMMY_CLOCK_TRIGGER BIT(1) 97 + 98 + #define SPMMC_SD_STATUS_REG 0x00A0 99 + #define SPMMC_SDSTATUS_DUMMY_READY BIT(0) 100 + #define SPMMC_SDSTATUS_RSP_BUF_FULL BIT(1) 101 + #define SPMMC_SDSTATUS_TX_DATA_BUF_EMPTY BIT(2) 102 + #define SPMMC_SDSTATUS_RX_DATA_BUF_FULL BIT(3) 103 + #define SPMMC_SDSTATUS_CMD_PIN_STATUS BIT(4) 104 + #define SPMMC_SDSTATUS_DAT0_PIN_STATUS BIT(5) 105 + #define SPMMC_SDSTATUS_RSP_TIMEOUT BIT(6) 106 + #define SPMMC_SDSTATUS_CARD_CRC_CHECK_TIMEOUT BIT(7) 107 + #define SPMMC_SDSTATUS_STB_TIMEOUT BIT(8) 108 + #define SPMMC_SDSTATUS_RSP_CRC7_ERROR BIT(9) 109 + #define SPMMC_SDSTATUS_CRC_TOKEN_CHECK_ERROR BIT(10) 110 + #define SPMMC_SDSTATUS_RDATA_CRC16_ERROR BIT(11) 111 + #define SPMMC_SDSTATUS_SUSPEND_STATE_READY BIT(12) 112 + #define SPMMC_SDSTATUS_BUSY_CYCLE BIT(13) 113 + #define SPMMC_SDSTATUS_DAT1_PIN_STATUS BIT(14) 114 + #define SPMMC_SDSTATUS_SD_SENSE_STATUS BIT(15) 115 + #define SPMMC_SDSTATUS_BOOT_ACK_TIMEOUT BIT(16) 116 + #define SPMMC_SDSTATUS_BOOT_DATA_TIMEOUT BIT(17) 117 + #define SPMMC_SDSTATUS_BOOT_ACK_ERROR BIT(18) 118 + 119 + #define SPMMC_SD_STATE_REG 0x00A4 120 + #define SPMMC_CRCTOKEN_CHECK_RESULT GENMASK(6, 4) 121 + #define SPMMC_SDSTATE_ERROR BIT(13) 122 + #define SPMMC_SDSTATE_FINISH BIT(14) 123 + 124 + #define SPMMC_SD_HW_STATE_REG 0x00A8 125 + #define SPMMC_SD_BLOCKSIZE_REG 0x00AC 126 + 127 + #define SPMMC_SD_CONFIG1_REG 0x00B0 128 + #define SPMMC_TX_DUMMY_NUM GENMASK(8, 0) 129 + #define SPMMC_SD_HIGH_SPEED_EN BIT(31) 130 + 131 + #define SPMMC_SD_TIMING_CONFIG0_REG 0x00B4 132 + #define SPMMC_SD_CLOCK_DELAY GENMASK(2, 0) 133 + #define SPMMC_SD_WRITE_DATA_DELAY GENMASK(6, 4) 134 + #define SPMMC_SD_WRITE_COMMAND_DELAY GENMASK(10, 8) 135 + #define SPMMC_SD_READ_RESPONSE_DELAY GENMASK(14, 12) 136 + #define SPMMC_SD_READ_DATA_DELAY GENMASK(18, 16) 137 + #define SPMMC_SD_READ_CRC_DELAY GENMASK(22, 20) 138 + 139 + #define SPMMC_SD_PIODATATX_REG 0x00BC 140 + #define SPMMC_SD_PIODATARX_REG 0x00C0 141 + #define SPMMC_SD_CMDBUF0_3_REG 0x00C4 142 + #define SPMMC_SD_CMDBUF4_REG 0x00C8 143 + #define SPMMC_SD_RSPBUF0_3_REG 0x00CC 144 + #define SPMMC_SD_RSPBUF4_5_REG 0x00D0 145 + 146 + #define SPMMC_MAX_RETRIES (8 * 8) 147 + 148 + struct spmmc_tuning_info { 149 + int enable_tuning; 150 + int need_tuning; 151 + int retried; /* how many times has been retried */ 152 + u32 rd_crc_dly:3; 153 + u32 rd_dat_dly:3; 154 + u32 rd_rsp_dly:3; 155 + u32 wr_cmd_dly:3; 156 + u32 wr_dat_dly:3; 157 + u32 clk_dly:3; 158 + }; 159 + 160 + #define SPMMC_DMA_MODE 0 161 + #define SPMMC_PIO_MODE 1 162 + 163 + struct spmmc_host { 164 + void __iomem *base; 165 + struct clk *clk; 166 + struct reset_control *rstc; 167 + struct mmc_host *mmc; 168 + struct mmc_request *mrq; /* current mrq */ 169 + int irq; 170 + int dmapio_mode; 171 + struct spmmc_tuning_info tuning_info; 172 + int dma_int_threshold; 173 + int dma_use_int; 174 + }; 175 + 176 + static inline int spmmc_wait_finish(struct spmmc_host *host) 177 + { 178 + u32 state; 179 + 180 + return readl_poll_timeout(host->base + SPMMC_SD_STATE_REG, state, 181 + (state & SPMMC_SDSTATE_FINISH), 182 + SPMMC_POLL_DELAY_US, SPMMC_TIMEOUT_US); 183 + } 184 + 185 + static inline int spmmc_wait_sdstatus(struct spmmc_host *host, unsigned int status_bit) 186 + { 187 + u32 status; 188 + 189 + return readl_poll_timeout(host->base + SPMMC_SD_STATUS_REG, status, 190 + (status & status_bit), 191 + SPMMC_POLL_DELAY_US, SPMMC_TIMEOUT_US); 192 + } 193 + 194 + #define spmmc_wait_rspbuf_full(host) spmmc_wait_sdstatus(host, SPMMC_SDSTATUS_RSP_BUF_FULL) 195 + #define spmmc_wait_rxbuf_full(host) spmmc_wait_sdstatus(host, SPMMC_SDSTATUS_RX_DATA_BUF_FULL) 196 + #define spmmc_wait_txbuf_empty(host) spmmc_wait_sdstatus(host, SPMMC_SDSTATUS_TX_DATA_BUF_EMPTY) 197 + 198 + static void spmmc_get_rsp(struct spmmc_host *host, struct mmc_command *cmd) 199 + { 200 + u32 value0_3, value4_5; 201 + 202 + if (!(cmd->flags & MMC_RSP_PRESENT)) 203 + return; 204 + if (cmd->flags & MMC_RSP_136) { 205 + if (spmmc_wait_rspbuf_full(host)) 206 + return; 207 + value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG); 208 + value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff; 209 + cmd->resp[0] = (value0_3 << 8) | (value4_5 >> 8); 210 + cmd->resp[1] = value4_5 << 24; 211 + value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG); 212 + value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff; 213 + cmd->resp[1] |= value0_3 >> 8; 214 + cmd->resp[2] = value0_3 << 24; 215 + cmd->resp[2] |= value4_5 << 8; 216 + value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG); 217 + value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff; 218 + cmd->resp[2] |= value0_3 >> 24; 219 + cmd->resp[3] = value0_3 << 8; 220 + cmd->resp[3] |= value4_5 >> 8; 221 + } else { 222 + if (spmmc_wait_rspbuf_full(host)) 223 + return; 224 + value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG); 225 + value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff; 226 + cmd->resp[0] = (value0_3 << 8) | (value4_5 >> 8); 227 + cmd->resp[1] = value4_5 << 24; 228 + } 229 + } 230 + 231 + static void spmmc_set_bus_clk(struct spmmc_host *host, int clk) 232 + { 233 + unsigned int clkdiv; 234 + int f_min = host->mmc->f_min; 235 + int f_max = host->mmc->f_max; 236 + u32 value = readl(host->base + SPMMC_SD_CONFIG0_REG); 237 + 238 + if (clk < f_min) 239 + clk = f_min; 240 + if (clk > f_max) 241 + clk = f_max; 242 + 243 + clkdiv = (clk_get_rate(host->clk) + clk) / clk - 1; 244 + if (clkdiv > 0xfff) 245 + clkdiv = 0xfff; 246 + value &= ~SPMMC_CLOCK_DIVISION; 247 + value |= FIELD_PREP(SPMMC_CLOCK_DIVISION, clkdiv); 248 + writel(value, host->base + SPMMC_SD_CONFIG0_REG); 249 + } 250 + 251 + static void spmmc_set_bus_timing(struct spmmc_host *host, unsigned int timing) 252 + { 253 + u32 value = readl(host->base + SPMMC_SD_CONFIG1_REG); 254 + int clkdiv = FIELD_GET(SPMMC_CLOCK_DIVISION, readl(host->base + SPMMC_SD_CONFIG0_REG)); 255 + int delay = clkdiv / 2 < 7 ? clkdiv / 2 : 7; 256 + int hs_en = 1, ddr_enabled = 0; 257 + 258 + switch (timing) { 259 + case MMC_TIMING_LEGACY: 260 + hs_en = 0; 261 + break; 262 + case MMC_TIMING_MMC_HS: 263 + case MMC_TIMING_SD_HS: 264 + case MMC_TIMING_UHS_SDR50: 265 + case MMC_TIMING_UHS_SDR104: 266 + case MMC_TIMING_MMC_HS200: 267 + hs_en = 1; 268 + break; 269 + case MMC_TIMING_UHS_DDR50: 270 + ddr_enabled = 1; 271 + break; 272 + case MMC_TIMING_MMC_DDR52: 273 + ddr_enabled = 1; 274 + break; 275 + default: 276 + hs_en = 0; 277 + break; 278 + } 279 + 280 + if (hs_en) { 281 + value |= SPMMC_SD_HIGH_SPEED_EN; 282 + writel(value, host->base + SPMMC_SD_CONFIG1_REG); 283 + value = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG); 284 + value &= ~SPMMC_SD_WRITE_DATA_DELAY; 285 + value |= FIELD_PREP(SPMMC_SD_WRITE_DATA_DELAY, delay); 286 + value &= ~SPMMC_SD_WRITE_COMMAND_DELAY; 287 + value |= FIELD_PREP(SPMMC_SD_WRITE_COMMAND_DELAY, delay); 288 + writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG); 289 + } else { 290 + value &= ~SPMMC_SD_HIGH_SPEED_EN; 291 + writel(value, host->base + SPMMC_SD_CONFIG1_REG); 292 + } 293 + if (ddr_enabled) { 294 + value = readl(host->base + SPMMC_SD_CONFIG0_REG); 295 + value |= SPMMC_SD_DDR_MODE; 296 + writel(value, host->base + SPMMC_SD_CONFIG0_REG); 297 + } else { 298 + value = readl(host->base + SPMMC_SD_CONFIG0_REG); 299 + value &= ~SPMMC_SD_DDR_MODE; 300 + writel(value, host->base + SPMMC_SD_CONFIG0_REG); 301 + } 302 + } 303 + 304 + static void spmmc_set_bus_width(struct spmmc_host *host, int width) 305 + { 306 + u32 value = readl(host->base + SPMMC_SD_CONFIG0_REG); 307 + 308 + switch (width) { 309 + case MMC_BUS_WIDTH_8: 310 + value &= ~SPMMC_SD_DATA_WD; 311 + value |= SPMMC_MMC8_EN; 312 + break; 313 + case MMC_BUS_WIDTH_4: 314 + value |= SPMMC_SD_DATA_WD; 315 + value &= ~SPMMC_MMC8_EN; 316 + break; 317 + default: 318 + value &= ~SPMMC_SD_DATA_WD; 319 + value &= ~SPMMC_MMC8_EN; 320 + break; 321 + } 322 + writel(value, host->base + SPMMC_SD_CONFIG0_REG); 323 + } 324 + 325 + /* 326 + * select the working mode of controller: sd/sdio/emmc 327 + */ 328 + static void spmmc_set_sdmmc_mode(struct spmmc_host *host) 329 + { 330 + u32 value = readl(host->base + SPMMC_SD_CONFIG0_REG); 331 + 332 + value |= SPMMC_SD_MMC_MODE; 333 + value &= ~SPMMC_SDIO_MODE; 334 + writel(value, host->base + SPMMC_SD_CONFIG0_REG); 335 + } 336 + 337 + static void spmmc_sw_reset(struct spmmc_host *host) 338 + { 339 + u32 value; 340 + 341 + /* 342 + * Must reset dma operation first, or it will 343 + * be stuck on sd_state == 0x1c00 because of 344 + * a controller software reset bug 345 + */ 346 + value = readl(host->base + SPMMC_HW_DMA_CTRL_REG); 347 + value |= SPMMC_DMAIDLE; 348 + writel(value, host->base + SPMMC_HW_DMA_CTRL_REG); 349 + value &= ~SPMMC_DMAIDLE; 350 + writel(value, host->base + SPMMC_HW_DMA_CTRL_REG); 351 + value = readl(host->base + SPMMC_HW_DMA_CTRL_REG); 352 + value |= SPMMC_HW_DMA_RST; 353 + writel(value, host->base + SPMMC_HW_DMA_CTRL_REG); 354 + writel(0x7, host->base + SPMMC_SD_RST_REG); 355 + readl_poll_timeout_atomic(host->base + SPMMC_SD_HW_STATE_REG, value, 356 + !(value & BIT(6)), 1, SPMMC_TIMEOUT_US); 357 + } 358 + 359 + static void spmmc_prepare_cmd(struct spmmc_host *host, struct mmc_command *cmd) 360 + { 361 + u32 value; 362 + 363 + /* add start bit, according to spec, command format */ 364 + value = ((cmd->opcode | 0x40) << 24) | (cmd->arg >> 8); 365 + writel(value, host->base + SPMMC_SD_CMDBUF0_3_REG); 366 + writeb(cmd->arg & 0xff, host->base + SPMMC_SD_CMDBUF4_REG); 367 + 368 + /* disable interrupt if needed */ 369 + value = readl(host->base + SPMMC_SD_INT_REG); 370 + value |= SPMMC_SDINT_SDCMPCLR; 371 + value &= ~SPMMC_SDINT_SDCMPEN; 372 + writel(value, host->base + SPMMC_SD_INT_REG); 373 + 374 + value = readl(host->base + SPMMC_SD_CONFIG0_REG); 375 + value &= ~SPMMC_SD_TRANS_MODE; 376 + value |= SPMMC_SD_CMD_DUMMY; 377 + if (cmd->flags & MMC_RSP_PRESENT) { 378 + value |= SPMMC_SD_AUTO_RESPONSE; 379 + } else { 380 + value &= ~SPMMC_SD_AUTO_RESPONSE; 381 + writel(value, host->base + SPMMC_SD_CONFIG0_REG); 382 + 383 + return; 384 + } 385 + /* 386 + * Currently, host is not capable of checking R2's CRC7, 387 + * thus, enable crc7 check only for 48 bit response commands 388 + */ 389 + if (cmd->flags & MMC_RSP_CRC && !(cmd->flags & MMC_RSP_136)) 390 + value |= SPMMC_SD_RSP_CHK_EN; 391 + else 392 + value &= ~SPMMC_SD_RSP_CHK_EN; 393 + 394 + if (cmd->flags & MMC_RSP_136) 395 + value |= SPMMC_SD_RSP_TYPE; 396 + else 397 + value &= ~SPMMC_SD_RSP_TYPE; 398 + writel(value, host->base + SPMMC_SD_CONFIG0_REG); 399 + } 400 + 401 + static void spmmc_prepare_data(struct spmmc_host *host, struct mmc_data *data) 402 + { 403 + u32 value, srcdst; 404 + 405 + writel(data->blocks - 1, host->base + SPMMC_SD_PAGE_NUM_REG); 406 + writel(data->blksz - 1, host->base + SPMMC_SD_BLOCKSIZE_REG); 407 + value = readl(host->base + SPMMC_SD_CONFIG0_REG); 408 + if (data->flags & MMC_DATA_READ) { 409 + value &= ~SPMMC_SD_TRANS_MODE; 410 + value |= FIELD_PREP(SPMMC_SD_TRANS_MODE, 2); 411 + value &= ~SPMMC_SD_AUTO_RESPONSE; 412 + value &= ~SPMMC_SD_CMD_DUMMY; 413 + srcdst = readl(host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG); 414 + srcdst &= ~SPMMC_DMA_SOURCE; 415 + srcdst |= FIELD_PREP(SPMMC_DMA_SOURCE, 0x2); 416 + srcdst &= ~SPMMC_DMA_DESTINATION; 417 + srcdst |= FIELD_PREP(SPMMC_DMA_DESTINATION, 0x1); 418 + writel(srcdst, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG); 419 + } else { 420 + value &= ~SPMMC_SD_TRANS_MODE; 421 + value |= FIELD_PREP(SPMMC_SD_TRANS_MODE, 1); 422 + srcdst = readl(host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG); 423 + srcdst &= ~SPMMC_DMA_SOURCE; 424 + srcdst |= FIELD_PREP(SPMMC_DMA_SOURCE, 0x1); 425 + srcdst &= ~SPMMC_DMA_DESTINATION; 426 + srcdst |= FIELD_PREP(SPMMC_DMA_DESTINATION, 0x2); 427 + writel(srcdst, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG); 428 + } 429 + 430 + value |= SPMMC_SD_LEN_MODE; 431 + if (host->dmapio_mode == SPMMC_DMA_MODE) { 432 + struct scatterlist *sg; 433 + dma_addr_t dma_addr; 434 + unsigned int dma_size; 435 + int i, count = 1; 436 + 437 + count = dma_map_sg(host->mmc->parent, data->sg, data->sg_len, 438 + mmc_get_dma_dir(data)); 439 + if (!count || count > SPMMC_MAX_DMA_MEMORY_SECTORS) { 440 + data->error = -EINVAL; 441 + 442 + return; 443 + } 444 + for_each_sg(data->sg, sg, count, i) { 445 + dma_addr = sg_dma_address(sg); 446 + dma_size = sg_dma_len(sg) / data->blksz - 1; 447 + if (i == 0) { 448 + writel(dma_addr, host->base + SPMMC_DMA_BASE_ADDR_REG); 449 + writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_0_SIZE_REG); 450 + } else if (i == 1) { 451 + writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_1_ADDR_REG); 452 + writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_1_LENG_REG); 453 + } else if (i == 2) { 454 + writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_2_ADDR_REG); 455 + writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_2_LENG_REG); 456 + } else if (i == 3) { 457 + writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_3_ADDR_REG); 458 + writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_3_LENG_REG); 459 + } else if (i == 4) { 460 + writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_4_ADDR_REG); 461 + writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_4_LENG_REG); 462 + } else if (i == 5) { 463 + writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_5_ADDR_REG); 464 + writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_5_LENG_REG); 465 + } else if (i == 6) { 466 + writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_6_ADDR_REG); 467 + writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_6_LENG_REG); 468 + } else if (i == 7) { 469 + writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_7_ADDR_REG); 470 + writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_7_LENG_REG); 471 + } 472 + } 473 + value &= ~SPMMC_SD_PIO_MODE; 474 + writel(value, host->base + SPMMC_SD_CONFIG0_REG); 475 + /* enable interrupt if needed */ 476 + if (data->blksz * data->blocks > host->dma_int_threshold) { 477 + host->dma_use_int = 1; 478 + value = readl(host->base + SPMMC_SD_INT_REG); 479 + value &= ~SPMMC_SDINT_SDCMPEN; 480 + value |= FIELD_PREP(SPMMC_SDINT_SDCMPEN, 1); /* sdcmpen */ 481 + writel(value, host->base + SPMMC_SD_INT_REG); 482 + } 483 + } else { 484 + value |= SPMMC_SD_PIO_MODE; 485 + value |= SPMMC_RX4_EN; 486 + writel(value, host->base + SPMMC_SD_CONFIG0_REG); 487 + } 488 + } 489 + 490 + static inline void spmmc_trigger_transaction(struct spmmc_host *host) 491 + { 492 + u32 value = readl(host->base + SPMMC_SD_CTRL_REG); 493 + 494 + value |= SPMMC_NEW_COMMAND_TRIGGER; 495 + writel(value, host->base + SPMMC_SD_CTRL_REG); 496 + } 497 + 498 + static void spmmc_send_stop_cmd(struct spmmc_host *host) 499 + { 500 + struct mmc_command stop = {}; 501 + u32 value; 502 + 503 + stop.opcode = MMC_STOP_TRANSMISSION; 504 + stop.arg = 0; 505 + stop.flags = MMC_RSP_R1B; 506 + spmmc_prepare_cmd(host, &stop); 507 + value = readl(host->base + SPMMC_SD_INT_REG); 508 + value &= ~SPMMC_SDINT_SDCMPEN; 509 + value |= FIELD_PREP(SPMMC_SDINT_SDCMPEN, 0); 510 + writel(value, host->base + SPMMC_SD_INT_REG); 511 + spmmc_trigger_transaction(host); 512 + readl_poll_timeout(host->base + SPMMC_SD_STATE_REG, value, 513 + (value & SPMMC_SDSTATE_FINISH), 1, SPMMC_TIMEOUT_US); 514 + } 515 + 516 + static int spmmc_check_error(struct spmmc_host *host, struct mmc_request *mrq) 517 + { 518 + int ret = 0; 519 + struct mmc_command *cmd = mrq->cmd; 520 + struct mmc_data *data = mrq->data; 521 + 522 + u32 value = readl(host->base + SPMMC_SD_STATE_REG); 523 + u32 crc_token = FIELD_GET(SPMMC_CRCTOKEN_CHECK_RESULT, value); 524 + 525 + if (value & SPMMC_SDSTATE_ERROR) { 526 + u32 timing_cfg0 = 0; 527 + 528 + value = readl(host->base + SPMMC_SD_STATUS_REG); 529 + 530 + if (host->tuning_info.enable_tuning) { 531 + timing_cfg0 = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG); 532 + host->tuning_info.rd_crc_dly = FIELD_GET(SPMMC_SD_READ_CRC_DELAY, 533 + timing_cfg0); 534 + host->tuning_info.rd_dat_dly = FIELD_GET(SPMMC_SD_READ_DATA_DELAY, 535 + timing_cfg0); 536 + host->tuning_info.rd_rsp_dly = FIELD_GET(SPMMC_SD_READ_RESPONSE_DELAY, 537 + timing_cfg0); 538 + host->tuning_info.wr_cmd_dly = FIELD_GET(SPMMC_SD_WRITE_COMMAND_DELAY, 539 + timing_cfg0); 540 + host->tuning_info.wr_dat_dly = FIELD_GET(SPMMC_SD_WRITE_DATA_DELAY, 541 + timing_cfg0); 542 + } 543 + 544 + if (value & SPMMC_SDSTATUS_RSP_TIMEOUT) { 545 + ret = -ETIMEDOUT; 546 + host->tuning_info.wr_cmd_dly++; 547 + } else if (value & SPMMC_SDSTATUS_RSP_CRC7_ERROR) { 548 + ret = -EILSEQ; 549 + host->tuning_info.rd_rsp_dly++; 550 + } else if (data) { 551 + if ((value & SPMMC_SDSTATUS_STB_TIMEOUT)) { 552 + ret = -ETIMEDOUT; 553 + host->tuning_info.rd_dat_dly++; 554 + } else if (value & SPMMC_SDSTATUS_RDATA_CRC16_ERROR) { 555 + ret = -EILSEQ; 556 + host->tuning_info.rd_dat_dly++; 557 + } else if (value & SPMMC_SDSTATUS_CARD_CRC_CHECK_TIMEOUT) { 558 + ret = -ETIMEDOUT; 559 + host->tuning_info.rd_crc_dly++; 560 + } else if (value & SPMMC_SDSTATUS_CRC_TOKEN_CHECK_ERROR) { 561 + ret = -EILSEQ; 562 + if (crc_token == 0x5) 563 + host->tuning_info.wr_dat_dly++; 564 + else 565 + host->tuning_info.rd_crc_dly++; 566 + } 567 + } 568 + cmd->error = ret; 569 + if (data) { 570 + data->error = ret; 571 + data->bytes_xfered = 0; 572 + } 573 + if (!host->tuning_info.need_tuning && host->tuning_info.enable_tuning) 574 + cmd->retries = SPMMC_MAX_RETRIES; 575 + spmmc_sw_reset(host); 576 + 577 + if (host->tuning_info.enable_tuning) { 578 + timing_cfg0 &= ~SPMMC_SD_READ_CRC_DELAY; 579 + timing_cfg0 |= FIELD_PREP(SPMMC_SD_READ_CRC_DELAY, 580 + host->tuning_info.rd_crc_dly); 581 + timing_cfg0 &= ~SPMMC_SD_READ_DATA_DELAY; 582 + timing_cfg0 |= FIELD_PREP(SPMMC_SD_READ_DATA_DELAY, 583 + host->tuning_info.rd_dat_dly); 584 + timing_cfg0 &= ~SPMMC_SD_READ_RESPONSE_DELAY; 585 + timing_cfg0 |= FIELD_PREP(SPMMC_SD_READ_RESPONSE_DELAY, 586 + host->tuning_info.rd_rsp_dly); 587 + timing_cfg0 &= ~SPMMC_SD_WRITE_COMMAND_DELAY; 588 + timing_cfg0 |= FIELD_PREP(SPMMC_SD_WRITE_COMMAND_DELAY, 589 + host->tuning_info.wr_cmd_dly); 590 + timing_cfg0 &= ~SPMMC_SD_WRITE_DATA_DELAY; 591 + timing_cfg0 |= FIELD_PREP(SPMMC_SD_WRITE_DATA_DELAY, 592 + host->tuning_info.wr_dat_dly); 593 + writel(timing_cfg0, host->base + SPMMC_SD_TIMING_CONFIG0_REG); 594 + } 595 + } else if (data) { 596 + data->error = 0; 597 + data->bytes_xfered = data->blocks * data->blksz; 598 + } 599 + host->tuning_info.need_tuning = ret; 600 + 601 + return ret; 602 + } 603 + 604 + /* 605 + * the strategy is: 606 + * 1. if several continuous delays are acceptable, we choose a middle one; 607 + * 2. otherwise, we choose the first one. 608 + */ 609 + static inline int spmmc_find_best_delay(u8 candidate_dly) 610 + { 611 + int f, w, value; 612 + 613 + if (!candidate_dly) 614 + return 0; 615 + f = ffs(candidate_dly) - 1; 616 + w = hweight8(candidate_dly); 617 + value = ((1 << w) - 1) << f; 618 + if (0xff == (value & ~candidate_dly)) 619 + return (f + w / 2); 620 + else 621 + return (f); 622 + } 623 + 624 + static void spmmc_xfer_data_pio(struct spmmc_host *host, struct mmc_data *data) 625 + { 626 + u32 *buf; 627 + int data_left = data->blocks * data->blksz; 628 + int consumed, remain; 629 + 630 + struct sg_mapping_iter sg_miter; 631 + unsigned int flags = 0; 632 + 633 + if (data->flags & MMC_DATA_WRITE) 634 + flags |= SG_MITER_FROM_SG; 635 + else 636 + flags |= SG_MITER_TO_SG; 637 + sg_miter_start(&sg_miter, data->sg, data->sg_len, flags); 638 + while (data_left > 0) { 639 + consumed = 0; 640 + if (!sg_miter_next(&sg_miter)) 641 + break; 642 + buf = sg_miter.addr; 643 + remain = sg_miter.length; 644 + do { 645 + if (data->flags & MMC_DATA_WRITE) { 646 + if (spmmc_wait_txbuf_empty(host)) 647 + goto done; 648 + writel(*buf, host->base + SPMMC_SD_PIODATATX_REG); 649 + } else { 650 + if (spmmc_wait_rxbuf_full(host)) 651 + goto done; 652 + *buf = readl(host->base + SPMMC_SD_PIODATARX_REG); 653 + } 654 + buf++; 655 + /* tx/rx 4 bytes one time in pio mode */ 656 + consumed += 4; 657 + remain -= 4; 658 + } while (remain); 659 + sg_miter.consumed = consumed; 660 + data_left -= consumed; 661 + } 662 + done: 663 + sg_miter_stop(&sg_miter); 664 + } 665 + 666 + static void spmmc_controller_init(struct spmmc_host *host) 667 + { 668 + u32 value; 669 + int ret = reset_control_assert(host->rstc); 670 + 671 + if (!ret) { 672 + usleep_range(1000, 1250); 673 + ret = reset_control_deassert(host->rstc); 674 + } 675 + 676 + value = readl(host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG); 677 + value &= ~SPMMC_MEDIA_TYPE; 678 + value |= FIELD_PREP(SPMMC_MEDIA_TYPE, SPMMC_MEDIA_SD); 679 + writel(value, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG); 680 + } 681 + 682 + /* 683 + * 1. unmap scatterlist if needed; 684 + * 2. get response & check error conditions; 685 + * 3. notify mmc layer the request is done 686 + */ 687 + static void spmmc_finish_request(struct spmmc_host *host, struct mmc_request *mrq) 688 + { 689 + struct mmc_command *cmd; 690 + struct mmc_data *data; 691 + 692 + if (!mrq) 693 + return; 694 + 695 + cmd = mrq->cmd; 696 + data = mrq->data; 697 + 698 + if (data && SPMMC_DMA_MODE == host->dmapio_mode) { 699 + dma_unmap_sg(host->mmc->parent, data->sg, data->sg_len, mmc_get_dma_dir(data)); 700 + host->dma_use_int = 0; 701 + } 702 + 703 + spmmc_get_rsp(host, cmd); 704 + spmmc_check_error(host, mrq); 705 + if (mrq->stop) 706 + spmmc_send_stop_cmd(host); 707 + 708 + host->mrq = NULL; 709 + mmc_request_done(host->mmc, mrq); 710 + } 711 + 712 + /* Interrupt Service Routine */ 713 + static irqreturn_t spmmc_irq(int irq, void *dev_id) 714 + { 715 + struct spmmc_host *host = dev_id; 716 + u32 value = readl(host->base + SPMMC_SD_INT_REG); 717 + 718 + if ((value & SPMMC_SDINT_SDCMP) && (value & SPMMC_SDINT_SDCMPEN)) { 719 + value &= ~SPMMC_SDINT_SDCMPEN; 720 + value |= SPMMC_SDINT_SDCMPCLR; 721 + writel(value, host->base + SPMMC_SD_INT_REG); 722 + return IRQ_WAKE_THREAD; 723 + } 724 + return IRQ_HANDLED; 725 + } 726 + 727 + static void spmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 728 + { 729 + struct spmmc_host *host = mmc_priv(mmc); 730 + struct mmc_data *data; 731 + struct mmc_command *cmd; 732 + 733 + host->mrq = mrq; 734 + data = mrq->data; 735 + cmd = mrq->cmd; 736 + 737 + spmmc_prepare_cmd(host, cmd); 738 + /* we need manually read response R2. */ 739 + if (cmd->flags & MMC_RSP_136) { 740 + spmmc_trigger_transaction(host); 741 + spmmc_get_rsp(host, cmd); 742 + spmmc_wait_finish(host); 743 + spmmc_check_error(host, mrq); 744 + host->mrq = NULL; 745 + mmc_request_done(host->mmc, mrq); 746 + } else { 747 + if (data) 748 + spmmc_prepare_data(host, data); 749 + 750 + if (host->dmapio_mode == SPMMC_PIO_MODE && data) { 751 + u32 value; 752 + /* pio data transfer do not use interrupt */ 753 + value = readl(host->base + SPMMC_SD_INT_REG); 754 + value &= ~SPMMC_SDINT_SDCMPEN; 755 + writel(value, host->base + SPMMC_SD_INT_REG); 756 + spmmc_trigger_transaction(host); 757 + spmmc_xfer_data_pio(host, data); 758 + spmmc_wait_finish(host); 759 + spmmc_finish_request(host, mrq); 760 + } else { 761 + if (host->dma_use_int) { 762 + spmmc_trigger_transaction(host); 763 + } else { 764 + spmmc_trigger_transaction(host); 765 + spmmc_wait_finish(host); 766 + spmmc_finish_request(host, mrq); 767 + } 768 + } 769 + } 770 + } 771 + 772 + static void spmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 773 + { 774 + struct spmmc_host *host = (struct spmmc_host *)mmc_priv(mmc); 775 + 776 + spmmc_set_bus_clk(host, ios->clock); 777 + spmmc_set_bus_timing(host, ios->timing); 778 + spmmc_set_bus_width(host, ios->bus_width); 779 + /* ensure mode is correct, because we might have hw reset the controller */ 780 + spmmc_set_sdmmc_mode(host); 781 + } 782 + 783 + /* 784 + * Return values for the get_cd callback should be: 785 + * 0 for a absent card 786 + * 1 for a present card 787 + * -ENOSYS when not supported (equal to NULL callback) 788 + * or a negative errno value when something bad happened 789 + */ 790 + static int spmmc_get_cd(struct mmc_host *mmc) 791 + { 792 + int ret = 0; 793 + 794 + if (mmc_can_gpio_cd(mmc)) 795 + ret = mmc_gpio_get_cd(mmc); 796 + 797 + if (ret < 0) 798 + ret = 0; 799 + 800 + return ret; 801 + } 802 + 803 + static int spmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 804 + { 805 + struct spmmc_host *host = mmc_priv(mmc); 806 + u8 smpl_dly = 0, candidate_dly = 0; 807 + u32 value; 808 + 809 + host->tuning_info.enable_tuning = 0; 810 + do { 811 + value = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG); 812 + value &= ~SPMMC_SD_READ_RESPONSE_DELAY; 813 + value |= FIELD_PREP(SPMMC_SD_READ_RESPONSE_DELAY, smpl_dly); 814 + value &= ~SPMMC_SD_READ_DATA_DELAY; 815 + value |= FIELD_PREP(SPMMC_SD_READ_DATA_DELAY, smpl_dly); 816 + value &= ~SPMMC_SD_READ_CRC_DELAY; 817 + value |= FIELD_PREP(SPMMC_SD_READ_CRC_DELAY, smpl_dly); 818 + writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG); 819 + 820 + if (!mmc_send_tuning(mmc, opcode, NULL)) { 821 + candidate_dly |= (1 << smpl_dly); 822 + break; 823 + } 824 + } while (smpl_dly++ <= SPMMC_MAX_TUNABLE_DLY); 825 + host->tuning_info.enable_tuning = 1; 826 + 827 + if (candidate_dly) { 828 + smpl_dly = spmmc_find_best_delay(candidate_dly); 829 + value = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG); 830 + value &= ~SPMMC_SD_READ_RESPONSE_DELAY; 831 + value |= FIELD_PREP(SPMMC_SD_READ_RESPONSE_DELAY, smpl_dly); 832 + value &= ~SPMMC_SD_READ_DATA_DELAY; 833 + value |= FIELD_PREP(SPMMC_SD_READ_DATA_DELAY, smpl_dly); 834 + value &= ~SPMMC_SD_READ_CRC_DELAY; 835 + value |= FIELD_PREP(SPMMC_SD_READ_CRC_DELAY, smpl_dly); 836 + writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG); 837 + return 0; 838 + } 839 + 840 + return -EIO; 841 + } 842 + 843 + static const struct mmc_host_ops spmmc_ops = { 844 + .request = spmmc_request, 845 + .set_ios = spmmc_set_ios, 846 + .get_cd = spmmc_get_cd, 847 + .execute_tuning = spmmc_execute_tuning, 848 + }; 849 + 850 + static irqreturn_t spmmc_func_finish_req(int irq, void *dev_id) 851 + { 852 + struct spmmc_host *host = dev_id; 853 + 854 + spmmc_finish_request(host, host->mrq); 855 + 856 + return IRQ_HANDLED; 857 + } 858 + 859 + static int spmmc_drv_probe(struct platform_device *pdev) 860 + { 861 + struct mmc_host *mmc; 862 + struct resource *res; 863 + struct spmmc_host *host; 864 + int ret = 0; 865 + 866 + mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 867 + if (!mmc) { 868 + ret = -ENOMEM; 869 + goto probe_free_host; 870 + } 871 + 872 + host = mmc_priv(mmc); 873 + host->mmc = mmc; 874 + host->dmapio_mode = SPMMC_DMA_MODE; 875 + host->dma_int_threshold = 1024; 876 + 877 + host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 878 + if (IS_ERR(host->base)) 879 + return PTR_ERR(host->base); 880 + 881 + host->clk = devm_clk_get(&pdev->dev, NULL); 882 + if (IS_ERR(host->clk)) 883 + return dev_err_probe(&pdev->dev, PTR_ERR(host->clk), "clk get fail\n"); 884 + 885 + host->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 886 + if (IS_ERR(host->rstc)) 887 + return dev_err_probe(&pdev->dev, PTR_ERR(host->rstc), "rst get fail\n"); 888 + 889 + host->irq = platform_get_irq(pdev, 0); 890 + if (host->irq <= 0) 891 + return host->irq; 892 + 893 + ret = devm_request_threaded_irq(&pdev->dev, host->irq, 894 + spmmc_irq, spmmc_func_finish_req, IRQF_SHARED, 895 + NULL, host); 896 + if (ret) 897 + return ret; 898 + 899 + ret = clk_prepare_enable(host->clk); 900 + if (ret) 901 + return dev_err_probe(&pdev->dev, ret, "failed to enable clk\n"); 902 + 903 + ret = mmc_of_parse(mmc); 904 + if (ret) 905 + goto probe_free_host; 906 + 907 + mmc->ops = &spmmc_ops; 908 + mmc->f_min = SPMMC_MIN_CLK; 909 + if (mmc->f_max > SPMMC_MAX_CLK) 910 + mmc->f_max = SPMMC_MAX_CLK; 911 + 912 + ret = mmc_regulator_get_supply(mmc); 913 + if (ret) 914 + goto probe_free_host; 915 + 916 + if (!mmc->ocr_avail) 917 + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 918 + mmc->max_seg_size = SPMMC_MAX_BLK_COUNT * 512; 919 + mmc->max_segs = SPMMC_MAX_DMA_MEMORY_SECTORS; 920 + mmc->max_req_size = SPMMC_MAX_BLK_COUNT * 512; 921 + mmc->max_blk_size = 512; 922 + mmc->max_blk_count = SPMMC_MAX_BLK_COUNT; 923 + 924 + dev_set_drvdata(&pdev->dev, host); 925 + spmmc_controller_init(host); 926 + spmmc_set_sdmmc_mode(host); 927 + host->tuning_info.enable_tuning = 1; 928 + pm_runtime_set_active(&pdev->dev); 929 + pm_runtime_enable(&pdev->dev); 930 + mmc_add_host(mmc); 931 + 932 + return ret; 933 + 934 + probe_free_host: 935 + if (mmc) 936 + mmc_free_host(mmc); 937 + 938 + return ret; 939 + } 940 + 941 + static int spmmc_drv_remove(struct platform_device *dev) 942 + { 943 + struct spmmc_host *host = platform_get_drvdata(dev); 944 + 945 + mmc_remove_host(host->mmc); 946 + pm_runtime_get_sync(&dev->dev); 947 + clk_disable_unprepare(host->clk); 948 + pm_runtime_put_noidle(&dev->dev); 949 + pm_runtime_disable(&dev->dev); 950 + platform_set_drvdata(dev, NULL); 951 + mmc_free_host(host->mmc); 952 + 953 + return 0; 954 + } 955 + 956 + static int spmmc_pm_runtime_suspend(struct device *dev) 957 + { 958 + struct spmmc_host *host; 959 + 960 + host = dev_get_drvdata(dev); 961 + clk_disable_unprepare(host->clk); 962 + 963 + return 0; 964 + } 965 + 966 + static int spmmc_pm_runtime_resume(struct device *dev) 967 + { 968 + struct spmmc_host *host; 969 + 970 + host = dev_get_drvdata(dev); 971 + 972 + return clk_prepare_enable(host->clk); 973 + } 974 + 975 + static DEFINE_RUNTIME_DEV_PM_OPS(spmmc_pm_ops, spmmc_pm_runtime_suspend, 976 + spmmc_pm_runtime_resume, NULL); 977 + 978 + static const struct of_device_id spmmc_of_table[] = { 979 + { 980 + .compatible = "sunplus,sp7021-mmc", 981 + }, 982 + {/* sentinel */} 983 + }; 984 + MODULE_DEVICE_TABLE(of, spmmc_of_table); 985 + 986 + static struct platform_driver spmmc_driver = { 987 + .probe = spmmc_drv_probe, 988 + .remove = spmmc_drv_remove, 989 + .driver = { 990 + .name = "spmmc", 991 + .pm = pm_ptr(&spmmc_pm_ops), 992 + .of_match_table = spmmc_of_table, 993 + }, 994 + }; 995 + module_platform_driver(spmmc_driver); 996 + 997 + MODULE_AUTHOR("Tony Huang <tonyhuang.sunplus@gmail.com>"); 998 + MODULE_AUTHOR("Li-hao Kuo <lhjeff911@gmail.com>"); 999 + MODULE_DESCRIPTION("Sunplus MMC controller driver"); 1000 + MODULE_LICENSE("GPL");

+10 -18

drivers/mmc/host/tifm_sd.c

··· 116 116 unsigned char *buf; 117 117 unsigned int pos = 0, val; 118 118 119 - buf = kmap_atomic(pg) + off; 119 + buf = kmap_local_page(pg) + off; 120 120 if (host->cmd_flags & DATA_CARRY) { 121 121 buf[pos++] = host->bounce_buf_data[0]; 122 122 host->cmd_flags &= ~DATA_CARRY; ··· 132 132 } 133 133 buf[pos++] = (val >> 8) & 0xff; 134 134 } 135 - kunmap_atomic(buf - off); 135 + kunmap_local(buf - off); 136 136 } 137 137 138 138 static void tifm_sd_write_fifo(struct tifm_sd *host, struct page *pg, ··· 142 142 unsigned char *buf; 143 143 unsigned int pos = 0, val; 144 144 145 - buf = kmap_atomic(pg) + off; 145 + buf = kmap_local_page(pg) + off; 146 146 if (host->cmd_flags & DATA_CARRY) { 147 147 val = host->bounce_buf_data[0] | ((buf[pos++] << 8) & 0xff00); 148 148 writel(val, sock->addr + SOCK_MMCSD_DATA); ··· 159 159 val |= (buf[pos++] << 8) & 0xff00; 160 160 writel(val, sock->addr + SOCK_MMCSD_DATA); 161 161 } 162 - kunmap_atomic(buf - off); 162 + kunmap_local(buf - off); 163 163 } 164 164 165 165 static void tifm_sd_transfer_data(struct tifm_sd *host) ··· 210 210 struct page *src, unsigned int src_off, 211 211 unsigned int count) 212 212 { 213 - unsigned char *src_buf = kmap_atomic(src) + src_off; 214 - unsigned char *dst_buf = kmap_atomic(dst) + dst_off; 213 + unsigned char *src_buf = kmap_local_page(src) + src_off; 214 + unsigned char *dst_buf = kmap_local_page(dst) + dst_off; 215 215 216 216 memcpy(dst_buf, src_buf, count); 217 217 218 - kunmap_atomic(dst_buf - dst_off); 219 - kunmap_atomic(src_buf - src_off); 218 + kunmap_local(dst_buf - dst_off); 219 + kunmap_local(src_buf - src_off); 220 220 } 221 221 222 222 static void tifm_sd_bounce_block(struct tifm_sd *host, struct mmc_data *r_data) ··· 264 264 unsigned int t_size = TIFM_DMA_TSIZE * r_data->blksz; 265 265 unsigned int dma_len, dma_blk_cnt, dma_off; 266 266 struct scatterlist *sg = NULL; 267 - unsigned long flags; 268 267 269 268 if (host->sg_pos == host->sg_len) 270 269 return 1; 271 270 272 271 if (host->cmd_flags & DATA_CARRY) { 273 272 host->cmd_flags &= ~DATA_CARRY; 274 - local_irq_save(flags); 275 273 tifm_sd_bounce_block(host, r_data); 276 - local_irq_restore(flags); 277 274 if (host->sg_pos == host->sg_len) 278 275 return 1; 279 276 } ··· 297 300 if (dma_blk_cnt) 298 301 sg = &r_data->sg[host->sg_pos]; 299 302 else if (dma_len) { 300 - if (r_data->flags & MMC_DATA_WRITE) { 301 - local_irq_save(flags); 303 + if (r_data->flags & MMC_DATA_WRITE) 302 304 tifm_sd_bounce_block(host, r_data); 303 - local_irq_restore(flags); 304 - } else 305 + else 305 306 host->cmd_flags |= DATA_CARRY; 306 307 307 308 sg = &host->bounce_buf; ··· 501 506 unsigned int host_status = 0; 502 507 int cmd_error = 0; 503 508 struct mmc_command *cmd = NULL; 504 - unsigned long flags; 505 509 506 510 spin_lock(&sock->lock); 507 511 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock)); ··· 564 570 565 571 if (host_status & (TIFM_MMCSD_AE | TIFM_MMCSD_AF 566 572 | TIFM_MMCSD_BRS)) { 567 - local_irq_save(flags); 568 573 tifm_sd_transfer_data(host); 569 - local_irq_restore(flags); 570 574 host_status &= ~TIFM_MMCSD_AE; 571 575 } 572 576 }

+1 -14

drivers/mmc/host/tmio_mmc.h

··· 128 128 129 129 /* optional */ 130 130 void (*end)(struct tmio_mmc_host *host); /* held host->lock */ 131 + bool (*dma_irq)(struct tmio_mmc_host *host); 131 132 }; 132 133 133 134 struct tmio_mmc_host { ··· 204 203 void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i); 205 204 void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i); 206 205 irqreturn_t tmio_mmc_irq(int irq, void *devid); 207 - 208 - static inline char *tmio_mmc_kmap_atomic(struct scatterlist *sg, 209 - unsigned long *flags) 210 - { 211 - local_irq_save(*flags); 212 - return kmap_atomic(sg_page(sg)) + sg->offset; 213 - } 214 - 215 - static inline void tmio_mmc_kunmap_atomic(struct scatterlist *sg, 216 - unsigned long *flags, void *virt) 217 - { 218 - kunmap_atomic(virt - sg->offset); 219 - local_irq_restore(*flags); 220 - } 221 206 222 207 #ifdef CONFIG_PM 223 208 int tmio_mmc_host_runtime_suspend(struct device *dev);

+10 -8

drivers/mmc/host/tmio_mmc_core.c

··· 412 412 void *sg_virt; 413 413 unsigned short *buf; 414 414 unsigned int count; 415 - unsigned long flags; 416 415 417 416 if (host->dma_on) { 418 417 pr_err("PIO IRQ in DMA mode!\n"); ··· 421 422 return; 422 423 } 423 424 424 - sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags); 425 - buf = (unsigned short *)(sg_virt + host->sg_off); 425 + sg_virt = kmap_local_page(sg_page(host->sg_ptr)); 426 + buf = (unsigned short *)(sg_virt + host->sg_ptr->offset + host->sg_off); 426 427 427 428 count = host->sg_ptr->length - host->sg_off; 428 429 if (count > data->blksz) ··· 436 437 437 438 host->sg_off += count; 438 439 439 - tmio_mmc_kunmap_atomic(host->sg_ptr, &flags, sg_virt); 440 + kunmap_local(sg_virt); 440 441 441 442 if (host->sg_off == host->sg_ptr->length) 442 443 tmio_mmc_next_sg(host); ··· 445 446 static void tmio_mmc_check_bounce_buffer(struct tmio_mmc_host *host) 446 447 { 447 448 if (host->sg_ptr == &host->bounce_sg) { 448 - unsigned long flags; 449 - void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags); 449 + void *sg_virt = kmap_local_page(sg_page(host->sg_orig)); 450 450 451 - memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length); 452 - tmio_mmc_kunmap_atomic(host->sg_orig, &flags, sg_vaddr); 451 + memcpy(sg_virt + host->sg_orig->offset, host->bounce_buf, 452 + host->bounce_sg.length); 453 + kunmap_local(sg_virt); 453 454 } 454 455 } 455 456 ··· 668 669 tmio_mmc_data_irq(host, status); 669 670 return true; 670 671 } 672 + 673 + if (host->dma_ops && host->dma_ops->dma_irq && host->dma_ops->dma_irq(host)) 674 + return true; 671 675 672 676 return false; 673 677 }

+5 -1

drivers/mmc/host/toshsd.c

··· 651 651 if (ret) 652 652 goto unmap; 653 653 654 - mmc_add_host(mmc); 654 + ret = mmc_add_host(mmc); 655 + if (ret) 656 + goto free_irq; 655 657 656 658 base = pci_resource_start(pdev, 0); 657 659 dev_dbg(&pdev->dev, "MMIO %pa, IRQ %d\n", &base, pdev->irq); ··· 662 660 663 661 return 0; 664 662 663 + free_irq: 664 + free_irq(pdev->irq, host); 665 665 unmap: 666 666 pci_iounmap(pdev, host->ioaddr); 667 667 release:

+3 -1

drivers/mmc/host/via-sdmmc.c

··· 1151 1151 pcidev->subsystem_device == 0x3891) 1152 1152 sdhost->quirks = VIA_CRDR_QUIRK_300MS_PWRDELAY; 1153 1153 1154 - mmc_add_host(mmc); 1154 + ret = mmc_add_host(mmc); 1155 + if (ret) 1156 + goto unmap; 1155 1157 1156 1158 return 0; 1157 1159

+10 -3

drivers/mmc/host/vub300.c

··· 2049 2049 return; 2050 2050 kref_get(&vub300->kref); 2051 2051 if (enable) { 2052 + set_current_state(TASK_RUNNING); 2052 2053 mutex_lock(&vub300->irq_mutex); 2053 2054 if (vub300->irqs_queued) { 2054 2055 vub300->irqs_queued -= 1; ··· 2065 2064 vub300_queue_poll_work(vub300, 0); 2066 2065 } 2067 2066 mutex_unlock(&vub300->irq_mutex); 2067 + set_current_state(TASK_INTERRUPTIBLE); 2068 2068 } else { 2069 2069 vub300->irq_enabled = 0; 2070 2070 } ··· 2301 2299 0x0000, 0x0000, &vub300->system_port_status, 2302 2300 sizeof(vub300->system_port_status), 1000); 2303 2301 if (retval < 0) { 2304 - goto error4; 2302 + goto error5; 2305 2303 } else if (sizeof(vub300->system_port_status) == retval) { 2306 2304 vub300->card_present = 2307 2305 (0x0001 & vub300->system_port_status.port_flags) ? 1 : 0; 2308 2306 vub300->read_only = 2309 2307 (0x0010 & vub300->system_port_status.port_flags) ? 1 : 0; 2310 2308 } else { 2311 - goto error4; 2309 + goto error5; 2312 2310 } 2313 2311 usb_set_intfdata(interface, vub300); 2314 2312 INIT_DELAYED_WORK(&vub300->pollwork, vub300_pollwork_thread); ··· 2331 2329 "USB vub300 remote SDIO host controller[%d]" 2332 2330 "connected with no SD/SDIO card inserted\n", 2333 2331 interface_to_InterfaceNumber(interface)); 2334 - mmc_add_host(mmc); 2332 + retval = mmc_add_host(mmc); 2333 + if (retval) 2334 + goto error6; 2335 + 2335 2336 return 0; 2337 + error6: 2338 + del_timer_sync(&vub300->inactivity_timer); 2336 2339 error5: 2337 2340 mmc_free_host(mmc); 2338 2341 /*

+16 -6

drivers/mmc/host/wbsd.c

··· 267 267 268 268 static inline char *wbsd_map_sg(struct wbsd_host *host) 269 269 { 270 - return kmap_atomic(sg_page(host->cur_sg)) + host->cur_sg->offset; 270 + return kmap_local_page(sg_page(host->cur_sg)) + host->cur_sg->offset; 271 271 } 272 272 273 273 static inline void wbsd_sg_to_dma(struct wbsd_host *host, struct mmc_data *data) ··· 439 439 * End of scatter list entry? 440 440 */ 441 441 if (host->remain == 0) { 442 - kunmap_atomic(buffer); 442 + kunmap_local(buffer); 443 443 /* 444 444 * Get next entry. Check if last. 445 445 */ ··· 451 451 } 452 452 } 453 453 } 454 - kunmap_atomic(buffer); 454 + kunmap_local(buffer); 455 455 456 456 /* 457 457 * This is a very dirty hack to solve a ··· 505 505 * End of scatter list entry? 506 506 */ 507 507 if (host->remain == 0) { 508 - kunmap_atomic(buffer); 508 + kunmap_local(buffer); 509 509 /* 510 510 * Get next entry. Check if last. 511 511 */ ··· 517 517 } 518 518 } 519 519 } 520 - kunmap_atomic(buffer); 520 + kunmap_local(buffer); 521 521 522 522 /* 523 523 * The controller stops sending interrupts for ··· 1698 1698 */ 1699 1699 wbsd_init_device(host); 1700 1700 1701 - mmc_add_host(mmc); 1701 + ret = mmc_add_host(mmc); 1702 + if (ret) { 1703 + if (!pnp) 1704 + wbsd_chip_poweroff(host); 1705 + 1706 + wbsd_release_resources(host); 1707 + wbsd_free_mmc(dev); 1708 + 1709 + mmc_free_host(mmc); 1710 + return ret; 1711 + } 1702 1712 1703 1713 pr_info("%s: W83L51xD", mmc_hostname(mmc)); 1704 1714 if (host->chip_id != 0)

+5 -1

drivers/mmc/host/wmt-sdmmc.c

··· 856 856 /* configure the controller to a known 'ready' state */ 857 857 wmt_reset_hardware(mmc); 858 858 859 - mmc_add_host(mmc); 859 + ret = mmc_add_host(mmc); 860 + if (ret) 861 + goto fail7; 860 862 861 863 dev_info(&pdev->dev, "WMT SDHC Controller initialized\n"); 862 864 863 865 return 0; 866 + fail7: 867 + clk_disable_unprepare(priv->clk_sdmmc); 864 868 fail6: 865 869 clk_put(priv->clk_sdmmc); 866 870 fail5_and_a_half:

+25

include/linux/iommu.h

··· 605 605 * @flags: IOMMU_FWSPEC_* flags 606 606 * @num_ids: number of associated device IDs 607 607 * @ids: IDs which this device may present to the IOMMU 608 + * 609 + * Note that the IDs (and any other information, really) stored in this structure should be 610 + * considered private to the IOMMU device driver and are not to be used directly by IOMMU 611 + * consumers. 608 612 */ 609 613 struct iommu_fwspec { 610 614 const struct iommu_ops *ops; ··· 1102 1098 } 1103 1099 1104 1100 #endif /* CONFIG_IOMMU_DMA */ 1101 + 1102 + /* 1103 + * Newer generations of Tegra SoCs require devices' stream IDs to be directly programmed into 1104 + * some registers. These are always paired with a Tegra SMMU or ARM SMMU, for which the contents 1105 + * of the struct iommu_fwspec are known. Use this helper to formalize access to these internals. 1106 + */ 1107 + #define TEGRA_STREAM_ID_BYPASS 0x7f 1108 + 1109 + static inline bool tegra_dev_iommu_get_stream_id(struct device *dev, u32 *stream_id) 1110 + { 1111 + #ifdef CONFIG_IOMMU_API 1112 + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 1113 + 1114 + if (fwspec && fwspec->num_ids == 1) { 1115 + *stream_id = fwspec->ids[0] & 0xffff; 1116 + return true; 1117 + } 1118 + #endif 1119 + 1120 + return false; 1121 + } 1105 1122 1106 1123 #endif /* __LINUX_IOMMU_H */

-1

include/linux/mfd/tmio.h

··· 102 102 unsigned long capabilities2; 103 103 unsigned long flags; 104 104 u32 ocr_mask; /* available voltages */ 105 - int alignment_shift; 106 105 dma_addr_t dma_rx_offset; 107 106 unsigned int max_blk_count; 108 107 unsigned short max_segs;

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