Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: save UMC global channel index to eeprom
Save the global channel index returned by RAS TA to eeprom.
We can get memory physical address by MCA address and channel index.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Tao Zhou
and committed by
Alex Deucher
71a0e963
07dd49e1
+13
-11
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+2
-5
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+2
-5
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
···
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int amdgpu_umc_mca_to_addr(struct amdgpu_device *adev,
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uint64_t err_addr, uint32_t ch, uint32_t umc,
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uint32_t node, uint32_t socket,
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-
uint64_t *addr, bool dump_addr)
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+
struct ta_ras_query_address_output *addr_out, bool dump_addr)
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{
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struct ta_ras_query_address_input addr_in;
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-
struct ta_ras_query_address_output addr_out;
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int ret;
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memset(&addr_in, 0, sizeof(addr_in));
···
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if (adev->umc.ras && adev->umc.ras->convert_ras_err_addr) {
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ret = adev->umc.ras->convert_ras_err_addr(adev, NULL, &addr_in,
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-
&addr_out, dump_addr);
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+
addr_out, dump_addr);
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if (ret)
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return ret;
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} else {
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return 0;
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}
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-
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-
*addr = addr_out.pa.pa;
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return 0;
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}
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+8
-5
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
+8
-5
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
···
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bool dump_addr)
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{
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uint32_t col, col_lower, row, row_lower, bank;
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-
uint32_t channel_index, umc_inst = 0;
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+
uint32_t channel_index = 0, umc_inst = 0;
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uint32_t i, loop_bits[UMC_V12_0_RETIRE_LOOP_BITS];
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uint64_t soc_pa, column, err_addr;
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struct ta_ras_query_address_output addr_out_tmp;
···
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else
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paddr_out = addr_out;
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-
err_addr = bank = channel_index = 0;
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err_addr = bank = 0;
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if (addr_in) {
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err_addr = addr_in->ma.err_addr;
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addr_in->addr_type = TA_RAS_MCA_TO_PA;
···
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}
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bank = paddr_out->pa.bank;
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-
channel_index = paddr_out->pa.channel_idx;
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/* no need to care about umc inst if addr_in is NULL */
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umc_inst = addr_in->ma.umc_inst;
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}
···
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}
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soc_pa = paddr_out->pa.pa;
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channel_index = paddr_out->pa.channel_idx;
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/* clear loop bits in soc physical address */
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for (i = 0; i < UMC_V12_0_RETIRE_LOOP_BITS; i++)
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soc_pa &= ~BIT_ULL(loop_bits[i]);
···
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uint64_t page_pfn[UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL];
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uint64_t err_addr, pa_addr = 0;
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struct ras_ecc_err *ecc_err;
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+
struct ta_ras_query_address_output addr_out;
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int count, ret, i;
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hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID);
···
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ret = amdgpu_umc_mca_to_addr(adev,
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err_addr, MCA_IPID_2_UMC_CH(ipid),
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MCA_IPID_2_UMC_INST(ipid), MCA_IPID_2_DIE_ID(ipid),
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-
MCA_IPID_2_SOCKET_ID(ipid), &pa_addr, true);
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+
MCA_IPID_2_SOCKET_ID(ipid), &addr_out, true);
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if (ret)
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return ret;
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···
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if (!ecc_err)
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return -ENOMEM;
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+
pa_addr = addr_out.pa.pa;
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ecc_err->status = status;
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ecc_err->ipid = ipid;
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ecc_err->addr = addr;
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ecc_err->pa_pfn = pa_addr >> AMDGPU_GPU_PAGE_SHIFT;
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+
ecc_err->channel_idx = addr_out.pa.channel_idx;
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/* If converted pa_pfn is 0, use pa C4 pfn. */
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if (!ecc_err->pa_pfn)
···
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ret = amdgpu_umc_fill_error_record(err_data,
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ecc_err->addr,
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page_pfn[i] << AMDGPU_GPU_PAGE_SHIFT,
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MCA_IPID_2_UMC_CH(ecc_err->ipid),
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+
ecc_err->channel_idx,
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MCA_IPID_2_UMC_INST(ecc_err->ipid));
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if (ret)
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break;