Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
amdgpu/vce: use amdgpu_gtt_mgr_alloc_entries
Instead of reserving a number of GTT pages for VCE 1.0 this
commit now uses amdgpu_gtt_mgr_alloc_entries to allocate
the pages when initializing vce 1.0.
While at it remove the "does the VCPU BO already have a
32-bit address" check as suggested by Timur.
This decouples vce init from gtt init.
---
v7: renamed variables (Christian)
---
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Pierre-Eric Pelloux-Prayer
and committed by
Alex Deucher
71aec08f
866eedef
+18
-36
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
···
332
332
ttm_resource_manager_init(man, &adev->mman.bdev, gtt_size);
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start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS;
335
-
start += amdgpu_vce_required_gart_pages(adev);
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size = (adev->gmc.gart_size >> PAGE_SHIFT) - start;
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drm_mm_init(&mgr->mm, start, size);
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spin_lock_init(&mgr->lock);
-18
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-18
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
···
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451
}
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/**
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-
* amdgpu_vce_required_gart_pages() - gets number of GART pages required by VCE
455
-
*
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* @adev: amdgpu_device pointer
457
-
*
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* Returns how many GART pages we need before GTT for the VCE IP block.
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* For VCE1, see vce_v1_0_ensure_vcpu_bo_32bit_addr for details.
460
-
* For VCE2+, this is not needed so return zero.
461
-
*/
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-
u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev)
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-
{
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-
/* VCE IP block not added yet, so can't use amdgpu_ip_version */
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-
if (adev->family == AMDGPU_FAMILY_SI)
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-
return 512;
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-
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-
return 0;
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-
}
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-
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-
/**
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* amdgpu_vce_get_create_msg - generate a VCE create msg
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*
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* @ring: ring we should submit the msg to
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
···
52
52
uint32_t srbm_soft_reset;
53
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unsigned num_rings;
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54
uint32_t keyselect;
55
+
struct drm_mm_node gart_node;
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};
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int amdgpu_vce_early_init(struct amdgpu_device *adev);
···
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int amdgpu_vce_suspend(struct amdgpu_device *adev);
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int amdgpu_vce_resume(struct amdgpu_device *adev);
64
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void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
65
-
u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev);
66
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int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, struct amdgpu_job *job,
67
65
struct amdgpu_ib *ib);
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int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p,
+17
-16
drivers/gpu/drm/amd/amdgpu/vce_v1_0.c
+17
-16
drivers/gpu/drm/amd/amdgpu/vce_v1_0.c
···
47
47
#define VCE_V1_0_DATA_SIZE (7808 * (AMDGPU_MAX_VCE_HANDLES + 1))
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#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02
49
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-
#define VCE_V1_0_GART_PAGE_START \
51
-
(AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS)
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-
#define VCE_V1_0_GART_ADDR_START \
53
-
(VCE_V1_0_GART_PAGE_START * AMDGPU_GPU_PAGE_SIZE)
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-
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static void vce_v1_0_set_ring_funcs(struct amdgpu_device *adev);
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static void vce_v1_0_set_irq_funcs(struct amdgpu_device *adev);
57
52
···
530
535
*/
531
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static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct amdgpu_device *adev)
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{
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-
u64 gpu_addr = amdgpu_bo_gpu_offset(adev->vce.vcpu_bo);
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u64 bo_size = amdgpu_bo_size(adev->vce.vcpu_bo);
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u64 max_vcpu_bo_addr = 0xffffffff - bo_size;
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u64 num_pages = ALIGN(bo_size, AMDGPU_GPU_PAGE_SIZE) / AMDGPU_GPU_PAGE_SIZE;
537
541
u64 pa = amdgpu_gmc_vram_pa(adev, adev->vce.vcpu_bo);
538
542
u64 flags = AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | AMDGPU_PTE_VALID;
543
+
u64 vce_gart_start_offs;
544
+
int r;
539
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-
/*
541
-
* Check if the VCPU BO already has a 32-bit address.
542
-
* Eg. if MC is configured to put VRAM in the low address range.
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-
*/
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-
if (gpu_addr <= max_vcpu_bo_addr)
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-
return 0;
546
+
r = amdgpu_gtt_mgr_alloc_entries(&adev->mman.gtt_mgr,
547
+
&adev->vce.gart_node, num_pages,
548
+
DRM_MM_INSERT_LOW);
549
+
if (r)
550
+
return r;
551
+
552
+
vce_gart_start_offs = amdgpu_gtt_node_to_byte_offset(&adev->vce.gart_node);
546
553
547
554
/* Check if we can map the VCPU BO in GART to a 32-bit address. */
548
-
if (adev->gmc.gart_start + VCE_V1_0_GART_ADDR_START > max_vcpu_bo_addr)
555
+
if (adev->gmc.gart_start + vce_gart_start_offs > max_vcpu_bo_addr)
549
556
return -EINVAL;
550
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551
-
amdgpu_gart_map_vram_range(adev, pa, VCE_V1_0_GART_PAGE_START,
558
+
amdgpu_gart_map_vram_range(adev, pa, adev->vce.gart_node.start,
552
559
num_pages, flags, adev->gart.ptr);
553
-
adev->vce.gpu_addr = adev->gmc.gart_start + VCE_V1_0_GART_ADDR_START;
560
+
adev->vce.gpu_addr = adev->gmc.gart_start + vce_gart_start_offs;
554
561
if (adev->vce.gpu_addr > max_vcpu_bo_addr)
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return -EINVAL;
556
563
···
607
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if (r)
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return r;
609
612
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-
return amdgpu_vce_sw_fini(adev);
613
+
r = amdgpu_vce_sw_fini(adev);
614
+
615
+
amdgpu_gtt_mgr_free_entries(&adev->mman.gtt_mgr, &adev->vce.gart_node);
616
+
617
+
return r;
611
618
}
612
619
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/**