Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
powercap: intel_rapl: Use GENMASK() and BIT() macros
Replace hardcoded bitmasks and bit shift operations with standard
GENMASK(), GENMASK_ULL(), BIT(), and BIT_ULL() macros for better
readability and to follow kernel coding conventions.
No functional changes.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Acked-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Link: https://patch.msgid.link/20260212233044.329790-7-sathyanarayanan.kuppuswamy@linux.intel.com
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
authored by
Kuppuswamy Sathyanarayanan
and committed by
Rafael J. Wysocki
71bb2c50
923860a8
+30
-30
+30
-30
drivers/powercap/intel_rapl_common.c
+30
-30
drivers/powercap/intel_rapl_common.c
···
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#include <asm/msr.h>
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/* bitmasks for RAPL MSRs, used by primitive access functions */
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-
#define ENERGY_STATUS_MASK 0xffffffff
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+
#define ENERGY_STATUS_MASK GENMASK(31, 0)
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-
#define POWER_LIMIT1_MASK 0x7FFF
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+
#define POWER_LIMIT1_MASK GENMASK(14, 0)
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#define POWER_LIMIT1_ENABLE BIT(15)
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#define POWER_LIMIT1_CLAMP BIT(16)
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-
#define POWER_LIMIT2_MASK (0x7FFFULL<<32)
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#define POWER_LIMIT2_MASK GENMASK_ULL(46, 32)
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#define POWER_LIMIT2_ENABLE BIT_ULL(47)
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#define POWER_LIMIT2_CLAMP BIT_ULL(48)
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#define POWER_HIGH_LOCK BIT_ULL(63)
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#define POWER_LOW_LOCK BIT(31)
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-
#define POWER_LIMIT4_MASK 0x1FFF
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+
#define POWER_LIMIT4_MASK GENMASK(12, 0)
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-
#define TIME_WINDOW1_MASK (0x7FULL<<17)
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-
#define TIME_WINDOW2_MASK (0x7FULL<<49)
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+
#define TIME_WINDOW1_MASK GENMASK_ULL(23, 17)
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#define TIME_WINDOW2_MASK GENMASK_ULL(55, 49)
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#define POWER_UNIT_OFFSET 0x00
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#define POWER_UNIT_MASK 0x0F
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#define POWER_UNIT_MASK GENMASK(3, 0)
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#define ENERGY_UNIT_OFFSET 0x08
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#define ENERGY_UNIT_MASK 0x1F00
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#define ENERGY_UNIT_MASK GENMASK(12, 8)
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#define TIME_UNIT_OFFSET 0x10
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#define TIME_UNIT_MASK 0xF0000
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#define TIME_UNIT_MASK GENMASK(19, 16)
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#define POWER_INFO_MAX_MASK (0x7fffULL<<32)
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#define POWER_INFO_MIN_MASK (0x7fffULL<<16)
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#define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48)
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#define POWER_INFO_THERMAL_SPEC_MASK 0x7fff
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#define POWER_INFO_MAX_MASK GENMASK_ULL(46, 32)
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#define POWER_INFO_MIN_MASK GENMASK_ULL(30, 16)
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#define POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48)
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#define POWER_INFO_THERMAL_SPEC_MASK GENMASK(14, 0)
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#define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff
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#define PP_POLICY_MASK 0x1F
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+
#define PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0)
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+
#define PP_POLICY_MASK GENMASK(4, 0)
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/*
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* SPR has different layout for Psys Domain PowerLimit registers.
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* There are 17 bits of PL1 and PL2 instead of 15 bits.
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* The Enable bits and TimeWindow bits are also shifted as a result.
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*/
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#define PSYS_POWER_LIMIT1_MASK 0x1FFFF
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#define PSYS_POWER_LIMIT1_MASK GENMASK_ULL(16, 0)
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#define PSYS_POWER_LIMIT1_ENABLE BIT(17)
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-
#define PSYS_POWER_LIMIT2_MASK (0x1FFFFULL<<32)
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#define PSYS_POWER_LIMIT2_MASK GENMASK_ULL(48, 32)
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#define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49)
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#define PSYS_TIME_WINDOW1_MASK (0x7FULL<<19)
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#define PSYS_TIME_WINDOW2_MASK (0x7FULL<<51)
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#define PSYS_TIME_WINDOW1_MASK GENMASK_ULL(25, 19)
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#define PSYS_TIME_WINDOW2_MASK GENMASK_ULL(57, 51)
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/* bitmasks for RAPL TPMI, used by primitive access functions */
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#define TPMI_POWER_LIMIT_MASK 0x3FFFF
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#define TPMI_POWER_LIMIT_MASK GENMASK_ULL(17, 0)
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#define TPMI_POWER_LIMIT_ENABLE BIT_ULL(62)
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#define TPMI_TIME_WINDOW_MASK (0x7FULL<<18)
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#define TPMI_INFO_SPEC_MASK 0x3FFFF
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-
#define TPMI_INFO_MIN_MASK (0x3FFFFULL << 18)
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#define TPMI_INFO_MAX_MASK (0x3FFFFULL << 36)
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-
#define TPMI_INFO_MAX_TIME_WIN_MASK (0x7FULL << 54)
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+
#define TPMI_TIME_WINDOW_MASK GENMASK_ULL(24, 18)
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#define TPMI_INFO_SPEC_MASK GENMASK_ULL(17, 0)
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#define TPMI_INFO_MIN_MASK GENMASK_ULL(35, 18)
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#define TPMI_INFO_MAX_MASK GENMASK_ULL(53, 36)
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#define TPMI_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(60, 54)
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/* Non HW constants */
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#define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */
···
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#define TPMI_POWER_UNIT_OFFSET POWER_UNIT_OFFSET
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#define TPMI_POWER_UNIT_MASK POWER_UNIT_MASK
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#define TPMI_ENERGY_UNIT_OFFSET 0x06
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-
#define TPMI_ENERGY_UNIT_MASK 0x7C0
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#define TPMI_ENERGY_UNIT_MASK GENMASK_ULL(10, 6)
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#define TPMI_TIME_UNIT_OFFSET 0x0C
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#define TPMI_TIME_UNIT_MASK 0xF000
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#define TPMI_TIME_UNIT_MASK GENMASK_ULL(15, 12)
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#define RAPL_EVENT_MASK GENMASK(7, 0)
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···
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&power_ctrl_orig_val);
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mdata = power_ctrl_orig_val;
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if (enable) {
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-
mdata &= ~(0x7f << 8);
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-
mdata |= 1 << 8;
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+
mdata &= ~GENMASK(14, 8);
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+
mdata |= BIT(8);
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}
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iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE,
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1109
defaults->floor_freq_reg_addr, mdata);
···
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if (y > 0x1f)
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return 0x7f;
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-
f = div64_u64(4 * (value - (1ULL << y)), 1ULL << y);
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+
f = div64_u64(4 * (value - BIT_ULL(y)), BIT_ULL(y));
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value = (y & 0x1f) | ((f & 0x3) << 5);
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}
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return value;