Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'net-stmmac-ingenic-convert-to-set_phy_intf_sel'
Russell King says:
====================
net: stmmac: ingenic: convert to set_phy_intf_sel()
Convert ingenic to use the new ->set_phy_intf_sel() method that was
recently introduced in net-next.
This is the largest of the conversions, as there is scope for cleanups
along with the conversion.
====================
Link: https://patch.msgid.link/aQ2tgEu-dudzlZlg@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+45
-120
+45
-120
drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c
+45
-120
drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c
···
35
35
#define MACPHYC_RX_DELAY_MASK GENMASK(10, 4)
36
36
#define MACPHYC_SOFT_RST_MASK GENMASK(3, 3)
37
37
#define MACPHYC_PHY_INFT_MASK GENMASK(2, 0)
38
-
#define MACPHYC_PHY_INFT_RMII 0x4
39
-
#define MACPHYC_PHY_INFT_RGMII 0x1
40
-
#define MACPHYC_PHY_INFT_GMII 0x0
41
-
#define MACPHYC_PHY_INFT_MII 0x0
42
38
43
39
#define MACPHYC_TX_DELAY_PS_MAX 2496
44
40
#define MACPHYC_TX_DELAY_PS_MIN 20
···
64
68
enum ingenic_mac_version version;
65
69
u32 mask;
66
70
67
-
int (*set_mode)(struct plat_stmmacenet_data *plat_dat);
71
+
int (*set_mode)(struct ingenic_mac *mac, u8 phy_intf_sel);
72
+
73
+
u8 valid_phy_intf_sel;
68
74
};
69
75
70
-
static int ingenic_mac_init(struct platform_device *pdev, void *bsp_priv)
76
+
static int jz4775_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel)
71
77
{
72
-
struct ingenic_mac *mac = bsp_priv;
73
-
int ret;
74
-
75
-
if (mac->soc_info->set_mode) {
76
-
ret = mac->soc_info->set_mode(mac->plat_dat);
77
-
if (ret)
78
-
return ret;
79
-
}
80
-
81
-
return 0;
82
-
}
83
-
84
-
static int jz4775_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
85
-
{
86
-
struct ingenic_mac *mac = plat_dat->bsp_priv;
87
78
unsigned int val;
88
79
89
-
switch (plat_dat->phy_interface) {
90
-
case PHY_INTERFACE_MODE_MII:
91
-
val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) |
92
-
FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_MII);
93
-
dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_MII\n");
94
-
break;
95
-
96
-
case PHY_INTERFACE_MODE_GMII:
97
-
val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) |
98
-
FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_GMII);
99
-
dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_GMII\n");
100
-
break;
101
-
102
-
case PHY_INTERFACE_MODE_RMII:
103
-
val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) |
104
-
FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII);
105
-
dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
106
-
break;
107
-
108
-
case PHY_INTERFACE_MODE_RGMII:
109
-
case PHY_INTERFACE_MODE_RGMII_ID:
110
-
case PHY_INTERFACE_MODE_RGMII_TXID:
111
-
case PHY_INTERFACE_MODE_RGMII_RXID:
112
-
val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) |
113
-
FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RGMII);
114
-
dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RGMII\n");
115
-
break;
116
-
117
-
default:
118
-
dev_err(mac->dev, "Unsupported interface %s\n",
119
-
phy_modes(plat_dat->phy_interface));
120
-
return -EINVAL;
121
-
}
80
+
val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel) |
81
+
FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT);
122
82
123
83
/* Update MAC PHY control register */
124
84
return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);
125
85
}
126
86
127
-
static int x1000_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
87
+
static int x1000_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel)
128
88
{
129
-
struct ingenic_mac *mac = plat_dat->bsp_priv;
130
-
131
-
switch (plat_dat->phy_interface) {
132
-
case PHY_INTERFACE_MODE_RMII:
133
-
dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
134
-
break;
135
-
136
-
default:
137
-
dev_err(mac->dev, "Unsupported interface %s\n",
138
-
phy_modes(plat_dat->phy_interface));
139
-
return -EINVAL;
140
-
}
141
-
142
89
/* Update MAC PHY control register */
143
90
return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, 0);
144
91
}
145
92
146
-
static int x1600_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
93
+
static int x1600_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel)
147
94
{
148
-
struct ingenic_mac *mac = plat_dat->bsp_priv;
149
95
unsigned int val;
150
96
151
-
switch (plat_dat->phy_interface) {
152
-
case PHY_INTERFACE_MODE_RMII:
153
-
val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII);
154
-
dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
155
-
break;
156
-
157
-
default:
158
-
dev_err(mac->dev, "Unsupported interface %s\n",
159
-
phy_modes(plat_dat->phy_interface));
160
-
return -EINVAL;
161
-
}
97
+
val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel);
162
98
163
99
/* Update MAC PHY control register */
164
100
return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);
165
101
}
166
102
167
-
static int x1830_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
103
+
static int x1830_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel)
168
104
{
169
-
struct ingenic_mac *mac = plat_dat->bsp_priv;
170
105
unsigned int val;
171
106
172
-
switch (plat_dat->phy_interface) {
173
-
case PHY_INTERFACE_MODE_RMII:
174
-
val = FIELD_PREP(MACPHYC_MODE_SEL_MASK, MACPHYC_MODE_SEL_RMII) |
175
-
FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII);
176
-
dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
177
-
break;
178
-
179
-
default:
180
-
dev_err(mac->dev, "Unsupported interface %s\n",
181
-
phy_modes(plat_dat->phy_interface));
182
-
return -EINVAL;
183
-
}
107
+
val = FIELD_PREP(MACPHYC_MODE_SEL_MASK, MACPHYC_MODE_SEL_RMII) |
108
+
FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel);
184
109
185
110
/* Update MAC PHY control register */
186
111
return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);
187
112
}
188
113
189
-
static int x2000_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
114
+
static int x2000_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel)
190
115
{
191
-
struct ingenic_mac *mac = plat_dat->bsp_priv;
192
116
unsigned int val;
193
117
194
-
switch (plat_dat->phy_interface) {
195
-
case PHY_INTERFACE_MODE_RMII:
196
-
val = FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN) |
197
-
FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN) |
198
-
FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII);
199
-
dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
200
-
break;
118
+
val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel);
201
119
202
-
case PHY_INTERFACE_MODE_RGMII:
203
-
case PHY_INTERFACE_MODE_RGMII_ID:
204
-
case PHY_INTERFACE_MODE_RGMII_TXID:
205
-
case PHY_INTERFACE_MODE_RGMII_RXID:
206
-
val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RGMII);
207
-
120
+
if (phy_intf_sel == PHY_INTF_SEL_RMII) {
121
+
val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN) |
122
+
FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN);
123
+
} else if (phy_intf_sel == PHY_INTF_SEL_RGMII) {
208
124
if (mac->tx_delay == 0)
209
125
val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN);
210
126
else
211
127
val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_DELAY) |
212
-
FIELD_PREP(MACPHYC_TX_DELAY_MASK, (mac->tx_delay + 9750) / 19500 - 1);
128
+
FIELD_PREP(MACPHYC_TX_DELAY_MASK, (mac->tx_delay + 9750) / 19500 - 1);
213
129
214
130
if (mac->rx_delay == 0)
215
131
val |= FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN);
216
132
else
217
133
val |= FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_DELAY) |
218
134
FIELD_PREP(MACPHYC_RX_DELAY_MASK, (mac->rx_delay + 9750) / 19500 - 1);
219
-
220
-
dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RGMII\n");
221
-
break;
222
-
223
-
default:
224
-
dev_err(mac->dev, "Unsupported interface %s\n",
225
-
phy_modes(plat_dat->phy_interface));
226
-
return -EINVAL;
227
135
}
228
136
229
137
/* Update MAC PHY control register */
230
138
return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);
139
+
}
140
+
141
+
static int ingenic_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel)
142
+
{
143
+
struct ingenic_mac *mac = bsp_priv;
144
+
145
+
if (!mac->soc_info->set_mode)
146
+
return 0;
147
+
148
+
if (phy_intf_sel >= BITS_PER_BYTE ||
149
+
~mac->soc_info->valid_phy_intf_sel & BIT(phy_intf_sel))
150
+
return -EINVAL;
151
+
152
+
dev_dbg(mac->dev, "MAC PHY control register: interface %s\n",
153
+
phy_modes(mac->plat_dat->phy_interface));
154
+
155
+
return mac->soc_info->set_mode(mac, phy_intf_sel);
231
156
}
232
157
233
158
static int ingenic_mac_probe(struct platform_device *pdev)
···
210
293
mac->plat_dat = plat_dat;
211
294
212
295
plat_dat->bsp_priv = mac;
213
-
plat_dat->init = ingenic_mac_init;
296
+
plat_dat->set_phy_intf_sel = ingenic_set_phy_intf_sel;
214
297
215
298
return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
216
299
}
···
220
303
.mask = MACPHYC_TXCLK_SEL_MASK | MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,
221
304
222
305
.set_mode = jz4775_mac_set_mode,
306
+
.valid_phy_intf_sel = BIT(PHY_INTF_SEL_GMII_MII) |
307
+
BIT(PHY_INTF_SEL_RGMII) |
308
+
BIT(PHY_INTF_SEL_RMII),
223
309
};
224
310
225
311
static struct ingenic_soc_info x1000_soc_info = {
···
230
310
.mask = MACPHYC_SOFT_RST_MASK,
231
311
232
312
.set_mode = x1000_mac_set_mode,
313
+
.valid_phy_intf_sel = BIT(PHY_INTF_SEL_RMII),
233
314
};
234
315
235
316
static struct ingenic_soc_info x1600_soc_info = {
···
238
317
.mask = MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,
239
318
240
319
.set_mode = x1600_mac_set_mode,
320
+
.valid_phy_intf_sel = BIT(PHY_INTF_SEL_RMII),
241
321
};
242
322
243
323
static struct ingenic_soc_info x1830_soc_info = {
···
246
324
.mask = MACPHYC_MODE_SEL_MASK | MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,
247
325
248
326
.set_mode = x1830_mac_set_mode,
327
+
.valid_phy_intf_sel = BIT(PHY_INTF_SEL_RMII),
249
328
};
250
329
251
330
static struct ingenic_soc_info x2000_soc_info = {
···
255
332
MACPHYC_RX_DELAY_MASK | MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,
256
333
257
334
.set_mode = x2000_mac_set_mode,
335
+
.valid_phy_intf_sel = BIT(PHY_INTF_SEL_RGMII) |
336
+
BIT(PHY_INTF_SEL_RMII),
258
337
};
259
338
260
339
static const struct of_device_id ingenic_mac_of_matches[] = {