Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dpu: add support for SDM660 and SDM630 platforms
Bring in hardware support for the SDM660 and SDM630 platforms, which
belong to the same DPU generation as MSM8998.
Note, by default these platforms are still handled by the MDP5 driver
unless the `msm.prefer_mdp5=false' parameter is provided.
Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/577507/
Link: https://lore.kernel.org/r/20240208-fd-migrate-mdp5-v4-4-945d08ef3fa8@linaro.org
+524
+291
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
+291
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2023. Linaro Inc. All rights reserved.
4
+
*/
5
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6
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#ifndef _DPU_3_2_SDM660_H
7
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#define _DPU_3_2_SDM660_H
8
+
9
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static const struct dpu_caps sdm660_dpu_caps = {
10
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
11
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.max_mixer_blendstages = 0x7,
12
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.has_src_split = true,
13
+
.has_dim_layer = true,
14
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.has_idle_pc = true,
15
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.has_3d_merge = true,
16
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.max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
17
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
18
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.max_hdeci_exp = MAX_HORZ_DECIMATION,
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.max_vdeci_exp = MAX_VERT_DECIMATION,
20
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};
21
+
22
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static const struct dpu_mdp_cfg sdm660_mdp = {
23
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.name = "top_0",
24
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.base = 0x0, .len = 0x458,
25
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.features = BIT(DPU_MDP_VSYNC_SEL),
26
+
.clk_ctrls = {
27
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[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28
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[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29
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[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30
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[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31
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[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
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[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
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},
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};
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static const struct dpu_ctl_cfg sdm660_ctl[] = {
37
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{
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.name = "ctl_0", .id = CTL_0,
39
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.base = 0x1000, .len = 0x94,
40
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.features = BIT(DPU_CTL_SPLIT_DISPLAY),
41
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
42
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}, {
43
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.name = "ctl_1", .id = CTL_1,
44
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.base = 0x1200, .len = 0x94,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
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}, {
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.name = "ctl_2", .id = CTL_2,
48
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.base = 0x1400, .len = 0x94,
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.features = BIT(DPU_CTL_SPLIT_DISPLAY),
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
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}, {
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.name = "ctl_3", .id = CTL_3,
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.base = 0x1600, .len = 0x94,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
55
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}, {
56
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.name = "ctl_4", .id = CTL_4,
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.base = 0x1800, .len = 0x94,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
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},
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};
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+
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static const struct dpu_sspp_cfg sdm660_sspp[] = {
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{
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.name = "sspp_0", .id = SSPP_VIG0,
65
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.base = 0x4000, .len = 0x1ac,
66
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.features = VIG_MSM8998_MASK,
67
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.sblk = &dpu_vig_sblk_qseed3_1_2,
68
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.xin_id = 0,
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.type = SSPP_TYPE_VIG,
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.clk_ctrl = DPU_CLK_CTRL_VIG0,
71
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}, {
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.name = "sspp_1", .id = SSPP_VIG1,
73
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.base = 0x6000, .len = 0x1ac,
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.features = VIG_MSM8998_MASK,
75
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.sblk = &dpu_vig_sblk_qseed3_1_2,
76
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.xin_id = 4,
77
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.type = SSPP_TYPE_VIG,
78
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.clk_ctrl = DPU_CLK_CTRL_VIG1,
79
+
}, {
80
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.name = "sspp_8", .id = SSPP_DMA0,
81
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.base = 0x24000, .len = 0x1ac,
82
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.features = DMA_MSM8998_MASK,
83
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.sblk = &dpu_dma_sblk,
84
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.xin_id = 1,
85
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.type = SSPP_TYPE_DMA,
86
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.clk_ctrl = DPU_CLK_CTRL_DMA0,
87
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}, {
88
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.name = "sspp_9", .id = SSPP_DMA1,
89
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.base = 0x26000, .len = 0x1ac,
90
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.features = DMA_MSM8998_MASK,
91
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.sblk = &dpu_dma_sblk,
92
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.xin_id = 5,
93
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.type = SSPP_TYPE_DMA,
94
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.clk_ctrl = DPU_CLK_CTRL_DMA1,
95
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}, {
96
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.name = "sspp_10", .id = SSPP_DMA2,
97
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.base = 0x28000, .len = 0x1ac,
98
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.features = DMA_CURSOR_MSM8998_MASK,
99
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.sblk = &dpu_dma_sblk,
100
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.xin_id = 9,
101
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.type = SSPP_TYPE_DMA,
102
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.clk_ctrl = DPU_CLK_CTRL_DMA2,
103
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},
104
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};
105
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106
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static const struct dpu_lm_cfg sdm660_lm[] = {
107
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{
108
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.name = "lm_0", .id = LM_0,
109
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.base = 0x44000, .len = 0x320,
110
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.features = MIXER_MSM8998_MASK,
111
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.sblk = &msm8998_lm_sblk,
112
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.lm_pair = LM_1,
113
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.pingpong = PINGPONG_0,
114
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.dspp = DSPP_0,
115
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}, {
116
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.name = "lm_1", .id = LM_1,
117
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.base = 0x45000, .len = 0x320,
118
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.features = MIXER_MSM8998_MASK,
119
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.sblk = &msm8998_lm_sblk,
120
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.lm_pair = LM_0,
121
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.pingpong = PINGPONG_1,
122
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.dspp = DSPP_1,
123
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}, {
124
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.name = "lm_2", .id = LM_2,
125
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.base = 0x46000, .len = 0x320,
126
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.features = MIXER_MSM8998_MASK,
127
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.sblk = &msm8998_lm_sblk,
128
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.lm_pair = LM_5,
129
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.pingpong = PINGPONG_2,
130
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}, {
131
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.name = "lm_5", .id = LM_5,
132
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.base = 0x49000, .len = 0x320,
133
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.features = MIXER_MSM8998_MASK,
134
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.sblk = &msm8998_lm_sblk,
135
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.lm_pair = LM_2,
136
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.pingpong = PINGPONG_3,
137
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},
138
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};
139
+
140
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static const struct dpu_pingpong_cfg sdm660_pp[] = {
141
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{
142
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.name = "pingpong_0", .id = PINGPONG_0,
143
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.base = 0x70000, .len = 0xd4,
144
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.features = PINGPONG_SDM845_TE2_MASK,
145
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.sblk = &sdm845_pp_sblk_te,
146
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
147
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.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
148
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}, {
149
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.name = "pingpong_1", .id = PINGPONG_1,
150
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.base = 0x70800, .len = 0xd4,
151
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.features = PINGPONG_SDM845_TE2_MASK,
152
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.sblk = &sdm845_pp_sblk_te,
153
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
154
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.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
155
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}, {
156
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.name = "pingpong_2", .id = PINGPONG_2,
157
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.base = 0x71000, .len = 0xd4,
158
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.features = PINGPONG_SDM845_MASK,
159
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.sblk = &sdm845_pp_sblk,
160
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
161
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.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
162
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}, {
163
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.name = "pingpong_3", .id = PINGPONG_3,
164
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.base = 0x71800, .len = 0xd4,
165
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.features = PINGPONG_SDM845_MASK,
166
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.sblk = &sdm845_pp_sblk,
167
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
168
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.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
169
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},
170
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};
171
+
172
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static const struct dpu_dsc_cfg sdm660_dsc[] = {
173
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{
174
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.name = "dsc_0", .id = DSC_0,
175
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.base = 0x80000, .len = 0x140,
176
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}, {
177
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.name = "dsc_1", .id = DSC_1,
178
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.base = 0x80400, .len = 0x140,
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},
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};
181
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182
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static const struct dpu_dspp_cfg sdm660_dspp[] = {
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{
184
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.name = "dspp_0", .id = DSPP_0,
185
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.base = 0x54000, .len = 0x1800,
186
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.features = DSPP_SC7180_MASK,
187
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.sblk = &msm8998_dspp_sblk,
188
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}, {
189
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.name = "dspp_1", .id = DSPP_1,
190
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.base = 0x56000, .len = 0x1800,
191
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.features = DSPP_SC7180_MASK,
192
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.sblk = &msm8998_dspp_sblk,
193
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},
194
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};
195
+
196
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static const struct dpu_intf_cfg sdm660_intf[] = {
197
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{
198
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.name = "intf_0", .id = INTF_0,
199
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.base = 0x6a000, .len = 0x280,
200
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.type = INTF_DP,
201
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.controller_id = MSM_DP_CONTROLLER_0,
202
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.prog_fetch_lines_worst_case = 21,
203
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.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
204
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.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
205
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.intr_tear_rd_ptr = -1,
206
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}, {
207
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.name = "intf_1", .id = INTF_1,
208
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.base = 0x6a800, .len = 0x280,
209
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.type = INTF_DSI,
210
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.controller_id = MSM_DSI_CONTROLLER_0,
211
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.prog_fetch_lines_worst_case = 21,
212
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.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
213
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.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
214
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.intr_tear_rd_ptr = -1,
215
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}, {
216
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.name = "intf_2", .id = INTF_2,
217
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.base = 0x6b000, .len = 0x280,
218
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.type = INTF_DSI,
219
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.controller_id = MSM_DSI_CONTROLLER_1,
220
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.prog_fetch_lines_worst_case = 21,
221
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.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
222
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.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
223
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.intr_tear_rd_ptr = -1,
224
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},
225
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};
226
+
227
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static const struct dpu_perf_cfg sdm660_perf_data = {
228
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.max_bw_low = 6600000,
229
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.max_bw_high = 6600000,
230
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.min_core_ib = 3100000,
231
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.min_llcc_ib = 800000,
232
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.min_dram_ib = 800000,
233
+
.undersized_prefill_lines = 2,
234
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.xtra_prefill_lines = 2,
235
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.dest_scale_prefill_lines = 3,
236
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.macrotile_prefill_lines = 4,
237
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.yuv_nv12_prefill_lines = 8,
238
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.linear_prefill_lines = 1,
239
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.downscaling_prefill_lines = 1,
240
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.amortizable_threshold = 25,
241
+
.min_prefill_lines = 25,
242
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.danger_lut_tbl = {0xf, 0xffff, 0x0},
243
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.safe_lut_tbl = {0xfffc, 0xff00, 0xffff},
244
+
.qos_lut_tbl = {
245
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{.nentry = ARRAY_SIZE(msm8998_qos_linear),
246
+
.entries = msm8998_qos_linear
247
+
},
248
+
{.nentry = ARRAY_SIZE(msm8998_qos_macrotile),
249
+
.entries = msm8998_qos_macrotile
250
+
},
251
+
{.nentry = ARRAY_SIZE(msm8998_qos_nrt),
252
+
.entries = msm8998_qos_nrt
253
+
},
254
+
},
255
+
.cdp_cfg = {
256
+
{.rd_enable = 1, .wr_enable = 1},
257
+
{.rd_enable = 1, .wr_enable = 0}
258
+
},
259
+
.clk_inefficiency_factor = 200,
260
+
.bw_inefficiency_factor = 120,
261
+
};
262
+
263
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static const struct dpu_mdss_version sdm660_mdss_ver = {
264
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.core_major_ver = 3,
265
+
.core_minor_ver = 2,
266
+
};
267
+
268
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const struct dpu_mdss_cfg dpu_sdm660_cfg = {
269
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.mdss_ver = &sdm660_mdss_ver,
270
+
.caps = &sdm660_dpu_caps,
271
+
.mdp = &sdm660_mdp,
272
+
.ctl_count = ARRAY_SIZE(sdm660_ctl),
273
+
.ctl = sdm660_ctl,
274
+
.sspp_count = ARRAY_SIZE(sdm660_sspp),
275
+
.sspp = sdm660_sspp,
276
+
.mixer_count = ARRAY_SIZE(sdm660_lm),
277
+
.mixer = sdm660_lm,
278
+
.dspp_count = ARRAY_SIZE(sdm660_dspp),
279
+
.dspp = sdm660_dspp,
280
+
.pingpong_count = ARRAY_SIZE(sdm660_pp),
281
+
.pingpong = sdm660_pp,
282
+
.dsc_count = ARRAY_SIZE(sdm660_dsc),
283
+
.dsc = sdm660_dsc,
284
+
.intf_count = ARRAY_SIZE(sdm660_intf),
285
+
.intf = sdm660_intf,
286
+
.vbif_count = ARRAY_SIZE(msm8998_vbif),
287
+
.vbif = msm8998_vbif,
288
+
.perf = &sdm660_perf_data,
289
+
};
290
+
291
+
#endif
+225
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
+225
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2023. Linaro Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _DPU_3_3_SDM630_H
7
+
#define _DPU_3_3_SDM630_H
8
+
9
+
static const struct dpu_caps sdm630_dpu_caps = {
10
+
.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
11
+
.max_mixer_blendstages = 0x7,
12
+
.has_src_split = true,
13
+
.has_dim_layer = true,
14
+
.has_idle_pc = true,
15
+
.has_3d_merge = true,
16
+
.max_linewidth = DEFAULT_DPU_LINE_WIDTH,
17
+
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
18
+
.max_hdeci_exp = MAX_HORZ_DECIMATION,
19
+
.max_vdeci_exp = MAX_VERT_DECIMATION,
20
+
};
21
+
22
+
static const struct dpu_mdp_cfg sdm630_mdp = {
23
+
.name = "top_0",
24
+
.base = 0x0, .len = 0x458,
25
+
.features = BIT(DPU_MDP_VSYNC_SEL),
26
+
.clk_ctrls = {
27
+
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28
+
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29
+
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
30
+
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
31
+
[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
32
+
},
33
+
};
34
+
35
+
static const struct dpu_ctl_cfg sdm630_ctl[] = {
36
+
{
37
+
.name = "ctl_0", .id = CTL_0,
38
+
.base = 0x1000, .len = 0x94,
39
+
.features = BIT(DPU_CTL_SPLIT_DISPLAY),
40
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
41
+
}, {
42
+
.name = "ctl_1", .id = CTL_1,
43
+
.base = 0x1200, .len = 0x94,
44
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
45
+
}, {
46
+
.name = "ctl_2", .id = CTL_2,
47
+
.base = 0x1400, .len = 0x94,
48
+
.features = BIT(DPU_CTL_SPLIT_DISPLAY),
49
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
50
+
}, {
51
+
.name = "ctl_3", .id = CTL_3,
52
+
.base = 0x1600, .len = 0x94,
53
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
54
+
}, {
55
+
.name = "ctl_4", .id = CTL_4,
56
+
.base = 0x1800, .len = 0x94,
57
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
58
+
},
59
+
};
60
+
61
+
static const struct dpu_sspp_cfg sdm630_sspp[] = {
62
+
{
63
+
.name = "sspp_0", .id = SSPP_VIG0,
64
+
.base = 0x4000, .len = 0x1ac,
65
+
.features = VIG_MSM8998_MASK,
66
+
.sblk = &dpu_vig_sblk_qseed3_1_2,
67
+
.xin_id = 0,
68
+
.type = SSPP_TYPE_VIG,
69
+
.clk_ctrl = DPU_CLK_CTRL_VIG0,
70
+
}, {
71
+
.name = "sspp_8", .id = SSPP_DMA0,
72
+
.base = 0x24000, .len = 0x1ac,
73
+
.features = DMA_MSM8998_MASK,
74
+
.sblk = &dpu_dma_sblk,
75
+
.xin_id = 1,
76
+
.type = SSPP_TYPE_DMA,
77
+
.clk_ctrl = DPU_CLK_CTRL_DMA0,
78
+
}, {
79
+
.name = "sspp_9", .id = SSPP_DMA1,
80
+
.base = 0x26000, .len = 0x1ac,
81
+
.features = DMA_MSM8998_MASK,
82
+
.sblk = &dpu_dma_sblk,
83
+
.xin_id = 5,
84
+
.type = SSPP_TYPE_DMA,
85
+
.clk_ctrl = DPU_CLK_CTRL_DMA1,
86
+
}, {
87
+
.name = "sspp_10", .id = SSPP_DMA2,
88
+
.base = 0x28000, .len = 0x1ac,
89
+
.features = DMA_CURSOR_MSM8998_MASK,
90
+
.sblk = &dpu_dma_sblk,
91
+
.xin_id = 9,
92
+
.type = SSPP_TYPE_DMA,
93
+
.clk_ctrl = DPU_CLK_CTRL_DMA2,
94
+
},
95
+
};
96
+
97
+
static const struct dpu_lm_cfg sdm630_lm[] = {
98
+
{
99
+
.name = "lm_0", .id = LM_0,
100
+
.base = 0x44000, .len = 0x320,
101
+
.features = MIXER_MSM8998_MASK,
102
+
.sblk = &msm8998_lm_sblk,
103
+
.pingpong = PINGPONG_0,
104
+
.dspp = DSPP_0,
105
+
}, {
106
+
.name = "lm_2", .id = LM_2,
107
+
.base = 0x46000, .len = 0x320,
108
+
.features = MIXER_MSM8998_MASK,
109
+
.sblk = &msm8998_lm_sblk,
110
+
.pingpong = PINGPONG_2,
111
+
},
112
+
};
113
+
114
+
static const struct dpu_pingpong_cfg sdm630_pp[] = {
115
+
{
116
+
.name = "pingpong_0", .id = PINGPONG_0,
117
+
.base = 0x70000, .len = 0xd4,
118
+
.features = PINGPONG_SDM845_TE2_MASK,
119
+
.sblk = &sdm845_pp_sblk_te,
120
+
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
121
+
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
122
+
}, {
123
+
.name = "pingpong_2", .id = PINGPONG_2,
124
+
.base = 0x71000, .len = 0xd4,
125
+
.features = PINGPONG_SDM845_MASK,
126
+
.sblk = &sdm845_pp_sblk,
127
+
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
128
+
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
129
+
},
130
+
};
131
+
132
+
static const struct dpu_dspp_cfg sdm630_dspp[] = {
133
+
{
134
+
.name = "dspp_0", .id = DSPP_0,
135
+
.base = 0x54000, .len = 0x1800,
136
+
.features = DSPP_SC7180_MASK,
137
+
.sblk = &msm8998_dspp_sblk,
138
+
},
139
+
};
140
+
141
+
static const struct dpu_intf_cfg sdm630_intf[] = {
142
+
{
143
+
.name = "intf_0", .id = INTF_0,
144
+
.base = 0x6a000, .len = 0x280,
145
+
.type = INTF_DP,
146
+
.controller_id = MSM_DP_CONTROLLER_0,
147
+
.prog_fetch_lines_worst_case = 21,
148
+
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
149
+
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
150
+
.intr_tear_rd_ptr = -1,
151
+
}, {
152
+
.name = "intf_1", .id = INTF_1,
153
+
.base = 0x6a800, .len = 0x280,
154
+
.type = INTF_DSI,
155
+
.controller_id = MSM_DSI_CONTROLLER_0,
156
+
.prog_fetch_lines_worst_case = 21,
157
+
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
158
+
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
159
+
.intr_tear_rd_ptr = -1,
160
+
},
161
+
};
162
+
163
+
static const struct dpu_perf_cfg sdm630_perf_data = {
164
+
.max_bw_low = 4100000,
165
+
.max_bw_high = 4100000,
166
+
.min_core_ib = 3200000,
167
+
.min_llcc_ib = 800000,
168
+
.min_dram_ib = 800000,
169
+
.undersized_prefill_lines = 2,
170
+
.xtra_prefill_lines = 2,
171
+
.dest_scale_prefill_lines = 3,
172
+
.macrotile_prefill_lines = 4,
173
+
.yuv_nv12_prefill_lines = 8,
174
+
.linear_prefill_lines = 1,
175
+
.downscaling_prefill_lines = 1,
176
+
.amortizable_threshold = 25,
177
+
.min_prefill_lines = 25,
178
+
.danger_lut_tbl = {0xf, 0xffff, 0x0},
179
+
.safe_lut_tbl = {0xfffc, 0xff00, 0xffff},
180
+
.qos_lut_tbl = {
181
+
{.nentry = ARRAY_SIZE(msm8998_qos_linear),
182
+
.entries = msm8998_qos_linear
183
+
},
184
+
{.nentry = ARRAY_SIZE(msm8998_qos_macrotile),
185
+
.entries = msm8998_qos_macrotile
186
+
},
187
+
{.nentry = ARRAY_SIZE(msm8998_qos_nrt),
188
+
.entries = msm8998_qos_nrt
189
+
},
190
+
},
191
+
.cdp_cfg = {
192
+
{.rd_enable = 1, .wr_enable = 1},
193
+
{.rd_enable = 1, .wr_enable = 0}
194
+
},
195
+
.clk_inefficiency_factor = 200,
196
+
.bw_inefficiency_factor = 120,
197
+
};
198
+
199
+
static const struct dpu_mdss_version sdm630_mdss_ver = {
200
+
.core_major_ver = 3,
201
+
.core_minor_ver = 3,
202
+
};
203
+
204
+
const struct dpu_mdss_cfg dpu_sdm630_cfg = {
205
+
.mdss_ver = &sdm630_mdss_ver,
206
+
.caps = &sdm630_dpu_caps,
207
+
.mdp = &sdm630_mdp,
208
+
.ctl_count = ARRAY_SIZE(sdm630_ctl),
209
+
.ctl = sdm630_ctl,
210
+
.sspp_count = ARRAY_SIZE(sdm630_sspp),
211
+
.sspp = sdm630_sspp,
212
+
.mixer_count = ARRAY_SIZE(sdm630_lm),
213
+
.mixer = sdm630_lm,
214
+
.dspp_count = ARRAY_SIZE(sdm630_dspp),
215
+
.dspp = sdm630_dspp,
216
+
.pingpong_count = ARRAY_SIZE(sdm630_pp),
217
+
.pingpong = sdm630_pp,
218
+
.intf_count = ARRAY_SIZE(sdm630_intf),
219
+
.intf = sdm630_intf,
220
+
.vbif_count = ARRAY_SIZE(msm8998_vbif),
221
+
.vbif = msm8998_vbif,
222
+
.perf = &sdm630_perf_data,
223
+
};
224
+
225
+
#endif
+2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
···
680
680
*************************************************************/
681
681
682
682
#include "catalog/dpu_3_0_msm8998.h"
683
+
#include "catalog/dpu_3_2_sdm660.h"
684
+
#include "catalog/dpu_3_3_sdm630.h"
683
685
684
686
#include "catalog/dpu_4_0_sdm845.h"
685
687
#include "catalog/dpu_4_1_sdm670.h"
+2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
···
832
832
};
833
833
834
834
extern const struct dpu_mdss_cfg dpu_msm8998_cfg;
835
+
extern const struct dpu_mdss_cfg dpu_sdm630_cfg;
836
+
extern const struct dpu_mdss_cfg dpu_sdm660_cfg;
835
837
extern const struct dpu_mdss_cfg dpu_sdm845_cfg;
836
838
extern const struct dpu_mdss_cfg dpu_sdm670_cfg;
837
839
extern const struct dpu_mdss_cfg dpu_sm8150_cfg;
+2
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+2
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
···
1380
1380
static const struct of_device_id dpu_dt_match[] = {
1381
1381
{ .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, },
1382
1382
{ .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, },
1383
+
{ .compatible = "qcom,sdm630-mdp5", .data = &dpu_sdm630_cfg, },
1384
+
{ .compatible = "qcom,sdm660-mdp5", .data = &dpu_sdm660_cfg, },
1383
1385
{ .compatible = "qcom,sdm670-dpu", .data = &dpu_sdm670_cfg, },
1384
1386
{ .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, },
1385
1387
{ .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, },