tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'riscv/for-v5.5-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Paul Walmsley:
"Several fixes, and one cleanup, for RISC-V.

Fixes:

- Fix an error in a Kconfig file that resulted in an undefined
Kconfig option "CONFIG_CONFIG_MMU"

- Fix undefined Kconfig option "CONFIG_CONFIG_MMU"

- Fix scratch register clearing in M-mode (affects nommu users)

- Fix a mismerge on my part that broke the build for
CONFIG_SPARSEMEM_VMEMMAP users

Cleanup:

- Move SiFive L2 cache-related code to drivers/soc, per request"

* tag 'riscv/for-v5.5-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: move sifive_l2_cache.c to drivers/soc
riscv: define vmemmap before pfn_to_page calls
riscv: fix scratch register clearing in M-mode.
riscv: Fix use of undefined config option CONFIG_CONFIG_MMU

Linus Torvalds 7214618c 78bac77b

+40 -21
+1
MAINTAINERS
··· 6027 6027 L: linux-edac@vger.kernel.org 6028 6028 S: Supported 6029 6029 F: drivers/edac/sifive_edac.c 6030 + F: drivers/soc/sifive_l2_cache.c 6030 6031 6031 6032 EDAC-SKYLAKE 6032 6033 M: Tony Luck <tony.luck@intel.com>
+1 -1
arch/riscv/Kconfig
··· 154 154 def_bool y 155 155 156 156 config FIX_EARLYCON_MEM 157 - def_bool CONFIG_MMU 157 + def_bool MMU 158 158 159 159 config PGTABLE_LEVELS 160 160 int
+21 -17
arch/riscv/include/asm/pgtable.h
··· 90 90 #define __S110 PAGE_SHARED_EXEC 91 91 #define __S111 PAGE_SHARED_EXEC 92 92 93 + #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 94 + #define VMALLOC_END (PAGE_OFFSET - 1) 95 + #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) 96 + 97 + /* 98 + * Roughly size the vmemmap space to be large enough to fit enough 99 + * struct pages to map half the virtual address space. Then 100 + * position vmemmap directly below the VMALLOC region. 101 + */ 102 + #define VMEMMAP_SHIFT \ 103 + (CONFIG_VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) 104 + #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) 105 + #define VMEMMAP_END (VMALLOC_START - 1) 106 + #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) 107 + 108 + /* 109 + * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel 110 + * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled. 111 + */ 112 + #define vmemmap ((struct page *)VMEMMAP_START) 113 + 93 114 static inline int pmd_present(pmd_t pmd) 94 115 { 95 116 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); ··· 420 399 421 400 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 422 401 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 423 - 424 - #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 425 - #define VMALLOC_END (PAGE_OFFSET - 1) 426 - #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) 427 - 428 - /* 429 - * Roughly size the vmemmap space to be large enough to fit enough 430 - * struct pages to map half the virtual address space. Then 431 - * position vmemmap directly below the VMALLOC region. 432 - */ 433 - #define VMEMMAP_SHIFT \ 434 - (CONFIG_VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) 435 - #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) 436 - #define VMEMMAP_END (VMALLOC_START - 1) 437 - #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) 438 - 439 - #define vmemmap ((struct page *)VMEMMAP_START) 440 402 441 403 #define PCI_IO_SIZE SZ_16M 442 404 #define PCI_IO_END VMEMMAP_START
+1 -1
arch/riscv/kernel/head.S
··· 246 246 li t4, 0 247 247 li t5, 0 248 248 li t6, 0 249 - csrw sscratch, 0 249 + csrw CSR_SCRATCH, 0 250 250 251 251 #ifdef CONFIG_FPU 252 252 csrr t0, CSR_MISA
-1
arch/riscv/mm/Makefile
··· 10 10 obj-$(CONFIG_MMU) += fault.o 11 11 obj-y += cacheflush.o 12 12 obj-y += context.o 13 - obj-y += sifive_l2_cache.o 14 13 15 14 ifeq ($(CONFIG_MMU),y) 16 15 obj-$(CONFIG_SMP) += tlbflush.o
arch/riscv/mm/sifive_l2_cache.c drivers/soc/sifive/sifive_l2_cache.c
+1 -1
drivers/edac/Kconfig
··· 462 462 463 463 config EDAC_SIFIVE 464 464 bool "Sifive platform EDAC driver" 465 - depends on EDAC=y && RISCV 465 + depends on EDAC=y && SIFIVE_L2 466 466 help 467 467 Support for error detection and correction on the SiFive SoCs. 468 468
+1
drivers/soc/Kconfig
··· 14 14 source "drivers/soc/renesas/Kconfig" 15 15 source "drivers/soc/rockchip/Kconfig" 16 16 source "drivers/soc/samsung/Kconfig" 17 + source "drivers/soc/sifive/Kconfig" 17 18 source "drivers/soc/sunxi/Kconfig" 18 19 source "drivers/soc/tegra/Kconfig" 19 20 source "drivers/soc/ti/Kconfig"
+1
drivers/soc/Makefile
··· 20 20 obj-y += renesas/ 21 21 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ 22 22 obj-$(CONFIG_SOC_SAMSUNG) += samsung/ 23 + obj-$(CONFIG_SOC_SIFIVE) += sifive/ 23 24 obj-y += sunxi/ 24 25 obj-$(CONFIG_ARCH_TEGRA) += tegra/ 25 26 obj-y += ti/
+10
drivers/soc/sifive/Kconfig
··· 1 + # SPDX-License-Identifier: GPL-2.0 2 + 3 + if SOC_SIFIVE 4 + 5 + config SIFIVE_L2 6 + bool "Sifive L2 Cache controller" 7 + help 8 + Support for the L2 cache controller on SiFive platforms. 9 + 10 + endif
+3
drivers/soc/sifive/Makefile
··· 1 + # SPDX-License-Identifier: GPL-2.0 2 + 3 + obj-$(CONFIG_SIFIVE_L2) += sifive_l2_cache.o