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drm/i915/color: Place 3D LUT after CSC in plane color pipeline

Move the 3D LUT block to its correct position in the plane
color pipeline:

[Pre-CSC] -> [CSC] -> [3DLUT] -> [Post-CSC]

Fixes: 65db7a1f9cf7 ("drm/i915/color: Add 3D LUT to color pipeline")
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/20260113102303.724205-2-chaitanya.kumar.borah@intel.com

authored by

Chaitanya Kumar Borah and committed by
Maarten Lankhorst 7261305d 604826ac

+9 -9
+9 -9
drivers/gpu/drm/i915/display/intel_color_pipeline.c
··· 39 39 /* TODO: handle failures and clean up */ 40 40 prev_op = &colorop->base; 41 41 42 + colorop = intel_colorop_create(INTEL_PLANE_CB_CSC); 43 + ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane, 44 + DRM_COLOROP_FLAG_ALLOW_BYPASS); 45 + if (ret) 46 + return ret; 47 + 48 + drm_colorop_set_next_property(prev_op, &colorop->base); 49 + prev_op = &colorop->base; 50 + 42 51 if (DISPLAY_VER(display) >= 35 && 43 52 intel_color_crtc_has_3dlut(display, pipe) && 44 53 plane->type == DRM_PLANE_TYPE_PRIMARY) { ··· 63 54 64 55 prev_op = &colorop->base; 65 56 } 66 - 67 - colorop = intel_colorop_create(INTEL_PLANE_CB_CSC); 68 - ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane, 69 - DRM_COLOROP_FLAG_ALLOW_BYPASS); 70 - if (ret) 71 - return ret; 72 - 73 - drm_colorop_set_next_property(prev_op, &colorop->base); 74 - prev_op = &colorop->base; 75 57 76 58 colorop = intel_colorop_create(INTEL_PLANE_CB_POST_CSC_LUT); 77 59 ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane,