Merge tag 'pci-v5.13-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

+44

arch/x86/pci/fixup.c

··· 779 779 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar); 780 780 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar); 781 781 782 + #define RS690_LOWER_TOP_OF_DRAM2 0x30 783 + #define RS690_LOWER_TOP_OF_DRAM2_VALID 0x1 784 + #define RS690_UPPER_TOP_OF_DRAM2 0x31 785 + #define RS690_HTIU_NB_INDEX 0xA8 786 + #define RS690_HTIU_NB_INDEX_WR_ENABLE 0x100 787 + #define RS690_HTIU_NB_DATA 0xAC 788 + 789 + /* 790 + * Some BIOS implementations support RAM above 4GB, but do not configure the 791 + * PCI host to respond to bus master accesses for these addresses. These 792 + * implementations set the TOP_OF_DRAM_SLOT1 register correctly, so PCI DMA 793 + * works as expected for addresses below 4GB. 794 + * 795 + * Reference: "AMD RS690 ASIC Family Register Reference Guide" (pg. 2-57) 796 + * https://www.amd.com/system/files/TechDocs/43372_rs690_rrg_3.00o.pdf 797 + */ 798 + static void rs690_fix_64bit_dma(struct pci_dev *pdev) 799 + { 800 + u32 val = 0; 801 + phys_addr_t top_of_dram = __pa(high_memory - 1) + 1; 802 + 803 + if (top_of_dram <= (1ULL << 32)) 804 + return; 805 + 806 + pci_write_config_dword(pdev, RS690_HTIU_NB_INDEX, 807 + RS690_LOWER_TOP_OF_DRAM2); 808 + pci_read_config_dword(pdev, RS690_HTIU_NB_DATA, &val); 809 + 810 + if (val) 811 + return; 812 + 813 + pci_info(pdev, "Adjusting top of DRAM to %pa for 64-bit DMA support\n", &top_of_dram); 814 + 815 + pci_write_config_dword(pdev, RS690_HTIU_NB_INDEX, 816 + RS690_UPPER_TOP_OF_DRAM2 | RS690_HTIU_NB_INDEX_WR_ENABLE); 817 + pci_write_config_dword(pdev, RS690_HTIU_NB_DATA, top_of_dram >> 32); 818 + 819 + pci_write_config_dword(pdev, RS690_HTIU_NB_INDEX, 820 + RS690_LOWER_TOP_OF_DRAM2 | RS690_HTIU_NB_INDEX_WR_ENABLE); 821 + pci_write_config_dword(pdev, RS690_HTIU_NB_DATA, 822 + top_of_dram | RS690_LOWER_TOP_OF_DRAM2_VALID); 823 + } 824 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7910, rs690_fix_64bit_dma); 825 + 782 826 #endif

+2 -1

drivers/pci/controller/dwc/Makefile

··· 18 18 obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o 19 19 obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o 20 20 obj-$(CONFIG_PCI_MESON) += pci-meson.o 21 + obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o 21 22 obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o 22 23 obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o 23 24 ··· 39 38 ifdef CONFIG_PCI_QUIRKS 40 39 obj-$(CONFIG_ARM64) += pcie-al.o 41 40 obj-$(CONFIG_ARM64) += pcie-hisi.o 42 - obj-$(CONFIG_ARM64) += pcie-tegra194.o 41 + obj-$(CONFIG_ARM64) += pcie-tegra194-acpi.o 43 42 endif 44 43 endif

+108

drivers/pci/controller/dwc/pcie-tegra194-acpi.c

··· 1 + // SPDX-License-Identifier: GPL-2.0+ 2 + /* 3 + * ACPI quirks for Tegra194 PCIe host controller 4 + * 5 + * Copyright (C) 2021 NVIDIA Corporation. 6 + * 7 + * Author: Vidya Sagar <vidyas@nvidia.com> 8 + */ 9 + 10 + #include <linux/pci.h> 11 + #include <linux/pci-acpi.h> 12 + #include <linux/pci-ecam.h> 13 + 14 + #include "pcie-designware.h" 15 + 16 + struct tegra194_pcie_ecam { 17 + void __iomem *config_base; 18 + void __iomem *iatu_base; 19 + void __iomem *dbi_base; 20 + }; 21 + 22 + static int tegra194_acpi_init(struct pci_config_window *cfg) 23 + { 24 + struct device *dev = cfg->parent; 25 + struct tegra194_pcie_ecam *pcie_ecam; 26 + 27 + pcie_ecam = devm_kzalloc(dev, sizeof(*pcie_ecam), GFP_KERNEL); 28 + if (!pcie_ecam) 29 + return -ENOMEM; 30 + 31 + pcie_ecam->config_base = cfg->win; 32 + pcie_ecam->iatu_base = cfg->win + SZ_256K; 33 + pcie_ecam->dbi_base = cfg->win + SZ_512K; 34 + cfg->priv = pcie_ecam; 35 + 36 + return 0; 37 + } 38 + 39 + static void atu_reg_write(struct tegra194_pcie_ecam *pcie_ecam, int index, 40 + u32 val, u32 reg) 41 + { 42 + u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 43 + 44 + writel(val, pcie_ecam->iatu_base + offset + reg); 45 + } 46 + 47 + static void program_outbound_atu(struct tegra194_pcie_ecam *pcie_ecam, 48 + int index, int type, u64 cpu_addr, 49 + u64 pci_addr, u64 size) 50 + { 51 + atu_reg_write(pcie_ecam, index, lower_32_bits(cpu_addr), 52 + PCIE_ATU_LOWER_BASE); 53 + atu_reg_write(pcie_ecam, index, upper_32_bits(cpu_addr), 54 + PCIE_ATU_UPPER_BASE); 55 + atu_reg_write(pcie_ecam, index, lower_32_bits(pci_addr), 56 + PCIE_ATU_LOWER_TARGET); 57 + atu_reg_write(pcie_ecam, index, lower_32_bits(cpu_addr + size - 1), 58 + PCIE_ATU_LIMIT); 59 + atu_reg_write(pcie_ecam, index, upper_32_bits(pci_addr), 60 + PCIE_ATU_UPPER_TARGET); 61 + atu_reg_write(pcie_ecam, index, type, PCIE_ATU_CR1); 62 + atu_reg_write(pcie_ecam, index, PCIE_ATU_ENABLE, PCIE_ATU_CR2); 63 + } 64 + 65 + static void __iomem *tegra194_map_bus(struct pci_bus *bus, 66 + unsigned int devfn, int where) 67 + { 68 + struct pci_config_window *cfg = bus->sysdata; 69 + struct tegra194_pcie_ecam *pcie_ecam = cfg->priv; 70 + u32 busdev; 71 + int type; 72 + 73 + if (bus->number < cfg->busr.start || bus->number > cfg->busr.end) 74 + return NULL; 75 + 76 + if (bus->number == cfg->busr.start) { 77 + if (PCI_SLOT(devfn) == 0) 78 + return pcie_ecam->dbi_base + where; 79 + else 80 + return NULL; 81 + } 82 + 83 + busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | 84 + PCIE_ATU_FUNC(PCI_FUNC(devfn)); 85 + 86 + if (bus->parent->number == cfg->busr.start) { 87 + if (PCI_SLOT(devfn) == 0) 88 + type = PCIE_ATU_TYPE_CFG0; 89 + else 90 + return NULL; 91 + } else { 92 + type = PCIE_ATU_TYPE_CFG1; 93 + } 94 + 95 + program_outbound_atu(pcie_ecam, 0, type, cfg->res.start, busdev, 96 + SZ_256K); 97 + 98 + return pcie_ecam->config_base + where; 99 + } 100 + 101 + const struct pci_ecam_ops tegra194_pcie_ops = { 102 + .init = tegra194_acpi_init, 103 + .pci_ops = { 104 + .map_bus = tegra194_map_bus, 105 + .read = pci_generic_config_read, 106 + .write = pci_generic_config_write, 107 + } 108 + };

+18 -120

drivers/pci/controller/dwc/pcie-tegra194.c

··· 22 22 #include <linux/of_irq.h> 23 23 #include <linux/of_pci.h> 24 24 #include <linux/pci.h> 25 - #include <linux/pci-acpi.h> 26 - #include <linux/pci-ecam.h> 27 25 #include <linux/phy/phy.h> 28 26 #include <linux/pinctrl/consumer.h> 29 27 #include <linux/platform_device.h> ··· 245 247 GEN4_CORE_CLK_FREQ 246 248 }; 247 249 248 - static const u32 event_cntr_ctrl_offset[] = { 249 - 0x1d8, 250 - 0x1a8, 251 - 0x1a8, 252 - 0x1a8, 253 - 0x1c4, 254 - 0x1d8 255 - }; 256 - 257 - static const u32 event_cntr_data_offset[] = { 258 - 0x1dc, 259 - 0x1ac, 260 - 0x1ac, 261 - 0x1ac, 262 - 0x1c8, 263 - 0x1dc 264 - }; 265 - 266 250 struct tegra_pcie_dw { 267 251 struct device *dev; 268 252 struct resource *appl_res; ··· 292 312 struct tegra_pcie_dw_of_data { 293 313 enum dw_pcie_device_mode mode; 294 314 }; 295 - 296 - #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) 297 - struct tegra194_pcie_ecam { 298 - void __iomem *config_base; 299 - void __iomem *iatu_base; 300 - void __iomem *dbi_base; 301 - }; 302 - 303 - static int tegra194_acpi_init(struct pci_config_window *cfg) 304 - { 305 - struct device *dev = cfg->parent; 306 - struct tegra194_pcie_ecam *pcie_ecam; 307 - 308 - pcie_ecam = devm_kzalloc(dev, sizeof(*pcie_ecam), GFP_KERNEL); 309 - if (!pcie_ecam) 310 - return -ENOMEM; 311 - 312 - pcie_ecam->config_base = cfg->win; 313 - pcie_ecam->iatu_base = cfg->win + SZ_256K; 314 - pcie_ecam->dbi_base = cfg->win + SZ_512K; 315 - cfg->priv = pcie_ecam; 316 - 317 - return 0; 318 - } 319 - 320 - static void atu_reg_write(struct tegra194_pcie_ecam *pcie_ecam, int index, 321 - u32 val, u32 reg) 322 - { 323 - u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 324 - 325 - writel(val, pcie_ecam->iatu_base + offset + reg); 326 - } 327 - 328 - static void program_outbound_atu(struct tegra194_pcie_ecam *pcie_ecam, 329 - int index, int type, u64 cpu_addr, 330 - u64 pci_addr, u64 size) 331 - { 332 - atu_reg_write(pcie_ecam, index, lower_32_bits(cpu_addr), 333 - PCIE_ATU_LOWER_BASE); 334 - atu_reg_write(pcie_ecam, index, upper_32_bits(cpu_addr), 335 - PCIE_ATU_UPPER_BASE); 336 - atu_reg_write(pcie_ecam, index, lower_32_bits(pci_addr), 337 - PCIE_ATU_LOWER_TARGET); 338 - atu_reg_write(pcie_ecam, index, lower_32_bits(cpu_addr + size - 1), 339 - PCIE_ATU_LIMIT); 340 - atu_reg_write(pcie_ecam, index, upper_32_bits(pci_addr), 341 - PCIE_ATU_UPPER_TARGET); 342 - atu_reg_write(pcie_ecam, index, type, PCIE_ATU_CR1); 343 - atu_reg_write(pcie_ecam, index, PCIE_ATU_ENABLE, PCIE_ATU_CR2); 344 - } 345 - 346 - static void __iomem *tegra194_map_bus(struct pci_bus *bus, 347 - unsigned int devfn, int where) 348 - { 349 - struct pci_config_window *cfg = bus->sysdata; 350 - struct tegra194_pcie_ecam *pcie_ecam = cfg->priv; 351 - u32 busdev; 352 - int type; 353 - 354 - if (bus->number < cfg->busr.start || bus->number > cfg->busr.end) 355 - return NULL; 356 - 357 - if (bus->number == cfg->busr.start) { 358 - if (PCI_SLOT(devfn) == 0) 359 - return pcie_ecam->dbi_base + where; 360 - else 361 - return NULL; 362 - } 363 - 364 - busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | 365 - PCIE_ATU_FUNC(PCI_FUNC(devfn)); 366 - 367 - if (bus->parent->number == cfg->busr.start) { 368 - if (PCI_SLOT(devfn) == 0) 369 - type = PCIE_ATU_TYPE_CFG0; 370 - else 371 - return NULL; 372 - } else { 373 - type = PCIE_ATU_TYPE_CFG1; 374 - } 375 - 376 - program_outbound_atu(pcie_ecam, 0, type, cfg->res.start, busdev, 377 - SZ_256K); 378 - 379 - return pcie_ecam->config_base + where; 380 - } 381 - 382 - const struct pci_ecam_ops tegra194_pcie_ops = { 383 - .init = tegra194_acpi_init, 384 - .pci_ops = { 385 - .map_bus = tegra194_map_bus, 386 - .read = pci_generic_config_read, 387 - .write = pci_generic_config_write, 388 - } 389 - }; 390 - #endif /* defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) */ 391 - 392 - #ifdef CONFIG_PCIE_TEGRA194 393 315 394 316 static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci) 395 317 { ··· 576 694 }; 577 695 578 696 #if defined(CONFIG_PCIEASPM) 697 + static const u32 event_cntr_ctrl_offset[] = { 698 + 0x1d8, 699 + 0x1a8, 700 + 0x1a8, 701 + 0x1a8, 702 + 0x1c4, 703 + 0x1d8 704 + }; 705 + 706 + static const u32 event_cntr_data_offset[] = { 707 + 0x1dc, 708 + 0x1ac, 709 + 0x1ac, 710 + 0x1ac, 711 + 0x1c8, 712 + 0x1dc 713 + }; 714 + 579 715 static void disable_aspm_l11(struct tegra_pcie_dw *pcie) 580 716 { 581 717 u32 val; ··· 2311 2411 MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>"); 2312 2412 MODULE_DESCRIPTION("NVIDIA PCIe host controller driver"); 2313 2413 MODULE_LICENSE("GPL v2"); 2314 - 2315 - #endif /* CONFIG_PCIE_TEGRA194 */

+40 -9

drivers/pci/controller/pci-aardvark.c

··· 514 514 udelay(PIO_RETRY_DELAY); 515 515 } 516 516 517 - dev_err(dev, "config read/write timed out\n"); 517 + dev_err(dev, "PIO read/write transfer time out\n"); 518 518 return -ETIMEDOUT; 519 519 } 520 520 ··· 657 657 return true; 658 658 } 659 659 660 + static bool advk_pcie_pio_is_running(struct advk_pcie *pcie) 661 + { 662 + struct device *dev = &pcie->pdev->dev; 663 + 664 + /* 665 + * Trying to start a new PIO transfer when previous has not completed 666 + * cause External Abort on CPU which results in kernel panic: 667 + * 668 + * SError Interrupt on CPU0, code 0xbf000002 -- SError 669 + * Kernel panic - not syncing: Asynchronous SError Interrupt 670 + * 671 + * Functions advk_pcie_rd_conf() and advk_pcie_wr_conf() are protected 672 + * by raw_spin_lock_irqsave() at pci_lock_config() level to prevent 673 + * concurrent calls at the same time. But because PIO transfer may take 674 + * about 1.5s when link is down or card is disconnected, it means that 675 + * advk_pcie_wait_pio() does not always have to wait for completion. 676 + * 677 + * Some versions of ARM Trusted Firmware handles this External Abort at 678 + * EL3 level and mask it to prevent kernel panic. Relevant TF-A commit: 679 + * https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50 680 + */ 681 + if (advk_readl(pcie, PIO_START)) { 682 + dev_err(dev, "Previous PIO read/write transfer is still running\n"); 683 + return true; 684 + } 685 + 686 + return false; 687 + } 688 + 660 689 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, 661 690 int where, int size, u32 *val) 662 691 { ··· 702 673 return pci_bridge_emul_conf_read(&pcie->bridge, where, 703 674 size, val); 704 675 705 - /* Start PIO */ 706 - advk_writel(pcie, 0, PIO_START); 707 - advk_writel(pcie, 1, PIO_ISR); 676 + if (advk_pcie_pio_is_running(pcie)) { 677 + *val = 0xffffffff; 678 + return PCIBIOS_SET_FAILED; 679 + } 708 680 709 681 /* Program the control register */ 710 682 reg = advk_readl(pcie, PIO_CTRL); ··· 724 694 /* Program the data strobe */ 725 695 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); 726 696 727 - /* Start the transfer */ 697 + /* Clear PIO DONE ISR and start the transfer */ 698 + advk_writel(pcie, 1, PIO_ISR); 728 699 advk_writel(pcie, 1, PIO_START); 729 700 730 701 ret = advk_pcie_wait_pio(pcie); ··· 765 734 if (where % size) 766 735 return PCIBIOS_SET_FAILED; 767 736 768 - /* Start PIO */ 769 - advk_writel(pcie, 0, PIO_START); 770 - advk_writel(pcie, 1, PIO_ISR); 737 + if (advk_pcie_pio_is_running(pcie)) 738 + return PCIBIOS_SET_FAILED; 771 739 772 740 /* Program the control register */ 773 741 reg = advk_readl(pcie, PIO_CTRL); ··· 793 763 /* Program the data strobe */ 794 764 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); 795 765 796 - /* Start the transfer */ 766 + /* Clear PIO DONE ISR and start the transfer */ 767 + advk_writel(pcie, 1, PIO_ISR); 797 768 advk_writel(pcie, 1, PIO_START); 798 769 799 770 ret = advk_pcie_wait_pio(pcie);

+2

drivers/pci/of.c

··· 353 353 dev_warn(dev, "More than one I/O resource converted for %pOF. CPU base address for old range lost!\n", 354 354 dev_node); 355 355 *io_base = range.cpu_addr; 356 + } else if (resource_type(res) == IORESOURCE_MEM) { 357 + res->flags &= ~IORESOURCE_MEM_64; 356 358 } 357 359 358 360 pci_add_resource_offset(resources, res, res->start - range.pci_addr);

+92 -1

drivers/pci/quirks.c

··· 3547 3547 } 3548 3548 3549 3549 /* 3550 + * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be 3551 + * prevented for those affected devices. 3552 + */ 3553 + static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) 3554 + { 3555 + if ((dev->device & 0xffc0) == 0x2340) 3556 + quirk_no_bus_reset(dev); 3557 + } 3558 + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 3559 + quirk_nvidia_no_bus_reset); 3560 + 3561 + /* 3550 3562 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3551 3563 * The device will throw a Link Down error on AER-capable systems and 3552 3564 * regardless of AER, config space of the device is never accessible again ··· 3577 3565 * accesses to the child may fail. 3578 3566 */ 3579 3567 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 3568 + 3569 + /* 3570 + * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS 3571 + * automatically disables LTSSM when Secondary Bus Reset is received and 3572 + * the device stops working. Prevent bus reset for these devices. With 3573 + * this change, the device can be assigned to VMs with VFIO, but it will 3574 + * leak state between VMs. Reference 3575 + * https://e2e.ti.com/support/processors/f/791/t/954382 3576 + */ 3577 + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset); 3580 3578 3581 3579 static void quirk_no_pm_reset(struct pci_dev *dev) 3582 3580 { ··· 3923 3901 return 0; 3924 3902 } 3925 3903 3904 + #define PCI_DEVICE_ID_HINIC_VF 0x375E 3905 + #define HINIC_VF_FLR_TYPE 0x1000 3906 + #define HINIC_VF_FLR_CAP_BIT (1UL << 30) 3907 + #define HINIC_VF_OP 0xE80 3908 + #define HINIC_VF_FLR_PROC_BIT (1UL << 18) 3909 + #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */ 3910 + 3911 + /* Device-specific reset method for Huawei Intelligent NIC virtual functions */ 3912 + static int reset_hinic_vf_dev(struct pci_dev *pdev, int probe) 3913 + { 3914 + unsigned long timeout; 3915 + void __iomem *bar; 3916 + u32 val; 3917 + 3918 + if (probe) 3919 + return 0; 3920 + 3921 + bar = pci_iomap(pdev, 0, 0); 3922 + if (!bar) 3923 + return -ENOTTY; 3924 + 3925 + /* Get and check firmware capabilities */ 3926 + val = ioread32be(bar + HINIC_VF_FLR_TYPE); 3927 + if (!(val & HINIC_VF_FLR_CAP_BIT)) { 3928 + pci_iounmap(pdev, bar); 3929 + return -ENOTTY; 3930 + } 3931 + 3932 + /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */ 3933 + val = ioread32be(bar + HINIC_VF_OP); 3934 + val = val | HINIC_VF_FLR_PROC_BIT; 3935 + iowrite32be(val, bar + HINIC_VF_OP); 3936 + 3937 + pcie_flr(pdev); 3938 + 3939 + /* 3940 + * The device must recapture its Bus and Device Numbers after FLR 3941 + * in order generate Completions. Issue a config write to let the 3942 + * device capture this information. 3943 + */ 3944 + pci_write_config_word(pdev, PCI_VENDOR_ID, 0); 3945 + 3946 + /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */ 3947 + timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT); 3948 + do { 3949 + val = ioread32be(bar + HINIC_VF_OP); 3950 + if (!(val & HINIC_VF_FLR_PROC_BIT)) 3951 + goto reset_complete; 3952 + msleep(20); 3953 + } while (time_before(jiffies, timeout)); 3954 + 3955 + val = ioread32be(bar + HINIC_VF_OP); 3956 + if (!(val & HINIC_VF_FLR_PROC_BIT)) 3957 + goto reset_complete; 3958 + 3959 + pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val); 3960 + 3961 + reset_complete: 3962 + pci_iounmap(pdev, bar); 3963 + 3964 + return 0; 3965 + } 3966 + 3926 3967 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 3927 3968 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 3928 3969 reset_intel_82599_sfp_virtfn }, ··· 3998 3913 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr }, 3999 3914 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4000 3915 reset_chelsio_generic_dev }, 3916 + { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF, 3917 + reset_hinic_vf_dev }, 4001 3918 { 0 } 4002 3919 }; 4003 3920 ··· 4840 4753 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, 4841 4754 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, 4842 4755 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, 4756 + /* Broadcom multi-function device */ 4757 + { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs }, 4843 4758 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs }, 4844 4759 /* Amazon Annapurna Labs */ 4845 4760 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs }, ··· 5243 5154 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev) 5244 5155 { 5245 5156 if ((pdev->device == 0x7312 && pdev->revision != 0x00) || 5246 - (pdev->device == 0x7340 && pdev->revision != 0xc5)) 5157 + (pdev->device == 0x7340 && pdev->revision != 0xc5) || 5158 + (pdev->device == 0x7341 && pdev->revision != 0x00)) 5247 5159 return; 5248 5160 5249 5161 if (pdev->device == 0x15d8) { ··· 5271 5181 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats); 5272 5182 /* AMD Navi14 dGPU */ 5273 5183 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats); 5184 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats); 5274 5185 /* AMD Raven platform iGPU */ 5275 5186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats); 5276 5187 #endif /* CONFIG_PCI_ATS */

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