Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fixes from Will Deacon:
"Here are some arm64 fixes for -rc5.
The only non-trivial change (in terms of the diffstat) is fixing our
SVE ptrace API for big-endian machines, but the majority of this is
actually the addition of much-needed comments and updates to the
documentation to try to avoid this mess biting us again in future.
There are still a couple of small things on the horizon, but nothing
major at this point.
Summary:
- Fix broken SVE ptrace API when running in a big-endian configuration
- Fix performance regression due to off-by-one in TLBI range checking
- Fix build regression when using Clang"
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64/sve: Fix missing SVE/FPSIMD endianness conversions
arm64: tlbflush: Ensure start/end of address range are aligned to stride
arm64: Don't unconditionally add -Wno-psabi to KBUILD_CFLAGS
+78
-10
+16
Documentation/arm64/sve.txt
+16
Documentation/arm64/sve.txt
···
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is to connect to a target process first and then attempt a
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ptrace(PTRACE_GETREGSET, pid, NT_ARM_SVE, &iov).
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+
* Whenever SVE scalable register values (Zn, Pn, FFR) are exchanged in memory
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+
between userspace and the kernel, the register value is encoded in memory in
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+
an endianness-invariant layout, with bits [(8 * i + 7) : (8 * i)] encoded at
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byte offset i from the start of the memory representation. This affects for
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example the signal frame (struct sve_context) and ptrace interface
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(struct user_sve_header) and associated data.
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+
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+
Beware that on big-endian systems this results in a different byte order than
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for the FPSIMD V-registers, which are stored as single host-endian 128-bit
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values, with bits [(127 - 8 * i) : (120 - 8 * i)] of the register encoded at
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byte offset i. (struct fpsimd_context, struct user_fpsimd_state).
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+
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2. Vector length terminology
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-----------------------------
···
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* If the registers are present, the remainder of the record has a vl-dependent
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size and layout. Macros SVE_SIG_* are defined [1] to facilitate access to
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the members.
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+
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* Each scalable register (Zn, Pn, FFR) is stored in an endianness-invariant
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layout, with bits [(8 * i + 7) : (8 * i)] stored at byte offset i from the
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+
start of the register's representation in memory.
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* If the SVE context is too big to fit in sigcontext.__reserved[], then extra
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space is allocated on the stack, an extra_context record is written in
+1
-1
arch/arm64/Makefile
+1
-1
arch/arm64/Makefile
···
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KBUILD_CFLAGS += -mgeneral-regs-only $(lseinstr) $(brokengasinst)
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KBUILD_CFLAGS += -fno-asynchronous-unwind-tables
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-
KBUILD_CFLAGS += -Wno-psabi
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+
KBUILD_CFLAGS += $(call cc-disable-warning, psabi)
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KBUILD_AFLAGS += $(lseinstr) $(brokengasinst)
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KBUILD_CFLAGS += $(call cc-option,-mabi=lp64)
+3
arch/arm64/include/asm/tlbflush.h
+3
arch/arm64/include/asm/tlbflush.h
+7
arch/arm64/include/uapi/asm/kvm.h
+7
arch/arm64/include/uapi/asm/kvm.h
···
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KVM_REG_SIZE_U256 | \
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((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
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+
/*
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* Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and
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* KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness-
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* invariant layout which differs from the layout used for the FPSIMD
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* V-registers on big-endian systems: see sigcontext.h for more explanation.
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+
*/
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+
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#define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN
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#define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX
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+4
arch/arm64/include/uapi/asm/ptrace.h
+4
arch/arm64/include/uapi/asm/ptrace.h
···
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* FPCR uint32_t FPCR
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*
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* Additional data might be appended in the future.
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+
*
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* The Z-, P- and FFR registers are represented in memory in an endianness-
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* invariant layout which differs from the layout used for the FPSIMD
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+
* V-registers on big-endian systems: see sigcontext.h for more explanation.
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*/
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#define SVE_PT_SVE_ZREG_SIZE(vq) __SVE_ZREG_SIZE(vq)
+14
arch/arm64/include/uapi/asm/sigcontext.h
+14
arch/arm64/include/uapi/asm/sigcontext.h
···
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__uint128_t vregs[32];
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};
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+
/*
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* Note: similarly to all other integer fields, each V-register is stored in an
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+
* endianness-dependent format, with the byte at offset i from the start of the
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+
* in-memory representation of the register value containing
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+
*
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* bits [(7 + 8 * i) : (8 * i)] of the register on little-endian hosts; or
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+
* bits [(127 - 8 * i) : (120 - 8 * i)] on big-endian hosts.
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+
*/
88
+
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/* ESR_EL1 context */
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90
#define ESR_MAGIC 0x45535201
82
91
···
213
204
* FFR uint16_t[vq] first-fault status register
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*
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* Additional data might be appended in the future.
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+
*
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+
* Unlike vregs[] in fpsimd_context, each SVE scalable register (Z-, P- or FFR)
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+
* is encoded in memory in an endianness-invariant format, with the byte at
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+
* offset i from the start of the in-memory representation containing bits
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+
* [(7 + 8 * i) : (8 * i)] of the register value.
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*/
217
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#define SVE_SIG_ZREG_SIZE(vq) __SVE_ZREG_SIZE(vq)
+33
-9
arch/arm64/kernel/fpsimd.c
+33
-9
arch/arm64/kernel/fpsimd.c
···
39
39
#include <linux/slab.h>
40
40
#include <linux/stddef.h>
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41
#include <linux/sysctl.h>
42
+
#include <linux/swab.h>
42
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#include <asm/esr.h>
44
45
#include <asm/fpsimd.h>
···
353
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#define ZREG(sve_state, vq, n) ((char *)(sve_state) + \
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(SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET))
355
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+
#ifdef CONFIG_CPU_BIG_ENDIAN
356
+
static __uint128_t arm64_cpu_to_le128(__uint128_t x)
357
+
{
358
+
u64 a = swab64(x);
359
+
u64 b = swab64(x >> 64);
360
+
361
+
return ((__uint128_t)a << 64) | b;
362
+
}
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+
#else
364
+
static __uint128_t arm64_cpu_to_le128(__uint128_t x)
365
+
{
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+
return x;
367
+
}
368
+
#endif
369
+
370
+
#define arm64_le128_to_cpu(x) arm64_cpu_to_le128(x)
371
+
356
372
/*
357
373
* Transfer the FPSIMD state in task->thread.uw.fpsimd_state to
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374
* task->thread.sve_state.
···
387
369
void *sst = task->thread.sve_state;
388
370
struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state;
389
371
unsigned int i;
372
+
__uint128_t *p;
390
373
391
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if (!system_supports_sve())
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return;
393
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377
vq = sve_vq_from_vl(task->thread.sve_vl);
395
-
for (i = 0; i < 32; ++i)
396
-
memcpy(ZREG(sst, vq, i), &fst->vregs[i],
397
-
sizeof(fst->vregs[i]));
378
+
for (i = 0; i < 32; ++i) {
379
+
p = (__uint128_t *)ZREG(sst, vq, i);
380
+
*p = arm64_cpu_to_le128(fst->vregs[i]);
381
+
}
398
382
}
399
383
400
384
/*
···
415
395
void const *sst = task->thread.sve_state;
416
396
struct user_fpsimd_state *fst = &task->thread.uw.fpsimd_state;
417
397
unsigned int i;
398
+
__uint128_t const *p;
418
399
419
400
if (!system_supports_sve())
420
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return;
421
402
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403
vq = sve_vq_from_vl(task->thread.sve_vl);
423
-
for (i = 0; i < 32; ++i)
424
-
memcpy(&fst->vregs[i], ZREG(sst, vq, i),
425
-
sizeof(fst->vregs[i]));
404
+
for (i = 0; i < 32; ++i) {
405
+
p = (__uint128_t const *)ZREG(sst, vq, i);
406
+
fst->vregs[i] = arm64_le128_to_cpu(*p);
407
+
}
426
408
}
427
409
428
410
#ifdef CONFIG_ARM64_SVE
···
513
491
void *sst = task->thread.sve_state;
514
492
struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state;
515
493
unsigned int i;
494
+
__uint128_t *p;
516
495
517
496
if (!test_tsk_thread_flag(task, TIF_SVE))
518
497
return;
···
522
499
523
500
memset(sst, 0, SVE_SIG_REGS_SIZE(vq));
524
501
525
-
for (i = 0; i < 32; ++i)
526
-
memcpy(ZREG(sst, vq, i), &fst->vregs[i],
527
-
sizeof(fst->vregs[i]));
502
+
for (i = 0; i < 32; ++i) {
503
+
p = (__uint128_t *)ZREG(sst, vq, i);
504
+
*p = arm64_cpu_to_le128(fst->vregs[i]);
505
+
}
528
506
}
529
507
530
508
int sve_set_vector_length(struct task_struct *task,