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iio: adc: mcp3911: add support for the whole MCP39xx family

Microchip does have many similar chips, add support for those.

The new supported chips are:
- microchip,mcp3910
- microchip,mcp3912
- microchip,mcp3913
- microchip,mcp3914
- microchip,mcp3918
- microchip,mcp3919

Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20230822192259.1125792-7-marcus.folkesson@gmail.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

authored by

Marcus Folkesson and committed by
Jonathan Cameron 732ad342 593d7362

+415 -57
+4 -2
drivers/iio/adc/Kconfig
··· 785 785 select IIO_BUFFER 786 786 select IIO_TRIGGERED_BUFFER 787 787 help 788 - Say yes here to build support for Microchip Technology's MCP3911 789 - analog to digital converter. 788 + Say yes here to build support for one of the following 789 + Microchip Technology's analog to digital converters: 790 + MCP3910, MCP3911, MCP3912, MCP3913, MCP3914, 791 + MCP3918 and MCP3919. 790 792 791 793 This driver can also be built as a module. If so, the module will be 792 794 called mcp3911.
+411 -55
drivers/iio/adc/mcp3911.c
··· 61 61 #define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 6) | (0 << 0)) & 0xff) 62 62 #define MCP3911_REG_MASK GENMASK(4, 1) 63 63 64 - #define MCP3911_NUM_CHANNELS 2 65 64 #define MCP3911_NUM_SCALES 6 65 + 66 + /* Registers compatible with MCP3910 */ 67 + #define MCP3910_REG_STATUSCOM 0x0c 68 + #define MCP3910_STATUSCOM_READ GENMASK(23, 22) 69 + #define MCP3910_STATUSCOM_DRHIZ BIT(20) 70 + 71 + #define MCP3910_REG_GAIN 0x0b 72 + 73 + #define MCP3910_REG_CONFIG0 0x0d 74 + #define MCP3910_CONFIG0_EN_OFFCAL BIT(23) 75 + #define MCP3910_CONFIG0_OSR GENMASK(15, 13) 76 + 77 + #define MCP3910_REG_CONFIG1 0x0e 78 + #define MCP3910_CONFIG1_CLKEXT BIT(6) 79 + #define MCP3910_CONFIG1_VREFEXT BIT(7) 80 + 81 + #define MCP3910_REG_OFFCAL_CH0 0x0f 82 + #define MCP3910_OFFCAL(ch) (MCP3910_REG_OFFCAL_CH0 + (ch) * 6) 83 + 84 + /* Maximal number of channels used by the MCP39XX family */ 85 + #define MCP39XX_MAX_NUM_CHANNELS 8 66 86 67 87 static const int mcp3911_osr_table[] = { 32, 64, 128, 256, 512, 1024, 2048, 4096 }; 68 88 static u32 mcp3911_scale_table[MCP3911_NUM_SCALES][2]; 89 + 90 + enum mcp3911_id { 91 + MCP3910, 92 + MCP3911, 93 + MCP3912, 94 + MCP3913, 95 + MCP3914, 96 + MCP3918, 97 + MCP3919, 98 + }; 99 + 100 + struct mcp3911; 101 + struct mcp3911_chip_info { 102 + const struct iio_chan_spec *channels; 103 + unsigned int num_channels; 104 + 105 + int (*config)(struct mcp3911 *adc); 106 + int (*get_osr)(struct mcp3911 *adc, u32 *val); 107 + int (*set_osr)(struct mcp3911 *adc, u32 val); 108 + int (*enable_offset)(struct mcp3911 *adc, bool enable); 109 + int (*get_offset)(struct mcp3911 *adc, int channel, int *val); 110 + int (*set_offset)(struct mcp3911 *adc, int channel, int val); 111 + int (*set_scale)(struct mcp3911 *adc, int channel, u32 val); 112 + }; 69 113 70 114 struct mcp3911 { 71 115 struct spi_device *spi; ··· 118 74 struct clk *clki; 119 75 u32 dev_addr; 120 76 struct iio_trigger *trig; 121 - u32 gain[MCP3911_NUM_CHANNELS]; 77 + u32 gain[MCP39XX_MAX_NUM_CHANNELS]; 78 + const struct mcp3911_chip_info *chip; 122 79 struct { 123 - u32 channels[MCP3911_NUM_CHANNELS]; 80 + u32 channels[MCP39XX_MAX_NUM_CHANNELS]; 124 81 s64 ts __aligned(8); 125 82 } scan; 126 83 127 84 u8 tx_buf __aligned(IIO_DMA_MINALIGN); 128 - u8 rx_buf[MCP3911_NUM_CHANNELS * 3]; 85 + u8 rx_buf[MCP39XX_MAX_NUM_CHANNELS * 3]; 129 86 }; 130 87 131 88 static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len) ··· 168 123 val &= mask; 169 124 val |= tmp & ~mask; 170 125 return mcp3911_write(adc, reg, val, len); 126 + } 127 + 128 + static int mcp3910_enable_offset(struct mcp3911 *adc, bool enable) 129 + { 130 + unsigned int mask = MCP3910_CONFIG0_EN_OFFCAL; 131 + unsigned int value = enable ? mask : 0; 132 + 133 + return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, value, 3); 134 + } 135 + 136 + static int mcp3910_get_offset(struct mcp3911 *adc, int channel, int *val) 137 + { 138 + return mcp3911_read(adc, MCP3910_OFFCAL(channel), val, 3); 139 + } 140 + 141 + static int mcp3910_set_offset(struct mcp3911 *adc, int channel, int val) 142 + { 143 + int ret; 144 + 145 + ret = mcp3911_write(adc, MCP3910_OFFCAL(channel), val, 3); 146 + if (ret) 147 + return ret; 148 + 149 + return adc->chip->enable_offset(adc, 1); 150 + } 151 + 152 + static int mcp3911_enable_offset(struct mcp3911 *adc, bool enable) 153 + { 154 + unsigned int mask = MCP3911_STATUSCOM_EN_OFFCAL; 155 + unsigned int value = enable ? mask : 0; 156 + 157 + return mcp3911_update(adc, MCP3911_REG_STATUSCOM, mask, value, 2); 158 + } 159 + 160 + static int mcp3911_get_offset(struct mcp3911 *adc, int channel, int *val) 161 + { 162 + return mcp3911_read(adc, MCP3911_OFFCAL(channel), val, 3); 163 + } 164 + 165 + static int mcp3911_set_offset(struct mcp3911 *adc, int channel, int val) 166 + { 167 + int ret; 168 + 169 + ret = mcp3911_write(adc, MCP3911_OFFCAL(channel), val, 3); 170 + if (ret) 171 + return ret; 172 + 173 + return adc->chip->enable_offset(adc, 1); 174 + } 175 + 176 + static int mcp3910_get_osr(struct mcp3911 *adc, u32 *val) 177 + { 178 + int ret; 179 + unsigned int osr; 180 + 181 + ret = mcp3911_read(adc, MCP3910_REG_CONFIG0, val, 3); 182 + if (ret) 183 + return ret; 184 + 185 + osr = FIELD_GET(MCP3910_CONFIG0_OSR, *val); 186 + *val = 32 << osr; 187 + return 0; 188 + } 189 + 190 + static int mcp3910_set_osr(struct mcp3911 *adc, u32 val) 191 + { 192 + unsigned int osr = FIELD_PREP(MCP3910_CONFIG0_OSR, val); 193 + unsigned int mask = MCP3910_CONFIG0_OSR; 194 + 195 + return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, osr, 3); 196 + } 197 + 198 + static int mcp3911_set_osr(struct mcp3911 *adc, u32 val) 199 + { 200 + unsigned int osr = FIELD_PREP(MCP3911_CONFIG_OSR, val); 201 + unsigned int mask = MCP3911_CONFIG_OSR; 202 + 203 + return mcp3911_update(adc, MCP3911_REG_CONFIG, mask, osr, 2); 204 + } 205 + 206 + static int mcp3911_get_osr(struct mcp3911 *adc, u32 *val) 207 + { 208 + int ret; 209 + unsigned int osr; 210 + 211 + ret = mcp3911_read(adc, MCP3911_REG_CONFIG, val, 2); 212 + if (ret) 213 + return ret; 214 + 215 + osr = FIELD_GET(MCP3911_CONFIG_OSR, *val); 216 + *val = 32 << osr; 217 + return ret; 218 + } 219 + 220 + static int mcp3910_set_scale(struct mcp3911 *adc, int channel, u32 val) 221 + { 222 + return mcp3911_update(adc, MCP3910_REG_GAIN, 223 + MCP3911_GAIN_MASK(channel), 224 + MCP3911_GAIN_VAL(channel, val), 3); 225 + } 226 + 227 + static int mcp3911_set_scale(struct mcp3911 *adc, int channel, u32 val) 228 + { 229 + return mcp3911_update(adc, MCP3911_REG_GAIN, 230 + MCP3911_GAIN_MASK(channel), 231 + MCP3911_GAIN_VAL(channel, val), 1); 171 232 } 172 233 173 234 static int mcp3911_write_raw_get_fmt(struct iio_dev *indio_dev, ··· 332 181 break; 333 182 334 183 case IIO_CHAN_INFO_OFFSET: 335 - ret = mcp3911_read(adc, 336 - MCP3911_OFFCAL(channel->channel), val, 3); 184 + 185 + ret = adc->chip->get_offset(adc, channel->channel, val); 337 186 if (ret) 338 187 goto out; 339 188 340 189 ret = IIO_VAL_INT; 341 190 break; 342 191 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 343 - ret = mcp3911_read(adc, MCP3911_REG_CONFIG, val, 2); 192 + ret = adc->chip->get_osr(adc, val); 344 193 if (ret) 345 194 goto out; 346 195 347 - *val = FIELD_GET(MCP3911_CONFIG_OSR, *val); 348 - *val = 32 << *val; 349 196 ret = IIO_VAL_INT; 350 197 break; 351 198 ··· 374 225 val2 == mcp3911_scale_table[i][1]) { 375 226 376 227 adc->gain[channel->channel] = BIT(i); 377 - ret = mcp3911_update(adc, MCP3911_REG_GAIN, 378 - MCP3911_GAIN_MASK(channel->channel), 379 - MCP3911_GAIN_VAL(channel->channel, i), 1); 228 + ret = adc->chip->set_scale(adc, channel->channel, i); 380 229 } 381 230 } 382 231 break; ··· 384 237 goto out; 385 238 } 386 239 387 - /* Write offset */ 388 - ret = mcp3911_write(adc, MCP3911_OFFCAL(channel->channel), val, 389 - 3); 390 - if (ret) 391 - goto out; 392 - 393 - /* Enable offset*/ 394 - ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM, 395 - MCP3911_STATUSCOM_EN_OFFCAL, 396 - MCP3911_STATUSCOM_EN_OFFCAL, 2); 240 + ret = adc->chip->set_offset(adc, channel->channel, val); 397 241 break; 398 242 399 243 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 400 244 for (int i = 0; i < ARRAY_SIZE(mcp3911_osr_table); i++) { 401 245 if (val == mcp3911_osr_table[i]) { 402 - val = FIELD_PREP(MCP3911_CONFIG_OSR, i); 403 - ret = mcp3911_update(adc, MCP3911_REG_CONFIG, MCP3911_CONFIG_OSR, 404 - val, 2); 246 + ret = adc->chip->set_osr(adc, i); 405 247 break; 406 248 } 407 249 } ··· 459 323 }, \ 460 324 } 461 325 326 + static const struct iio_chan_spec mcp3910_channels[] = { 327 + MCP3911_CHAN(0), 328 + MCP3911_CHAN(1), 329 + IIO_CHAN_SOFT_TIMESTAMP(2), 330 + }; 331 + 462 332 static const struct iio_chan_spec mcp3911_channels[] = { 463 333 MCP3911_CHAN(0), 464 334 MCP3911_CHAN(1), 465 335 IIO_CHAN_SOFT_TIMESTAMP(2), 336 + }; 337 + 338 + static const struct iio_chan_spec mcp3912_channels[] = { 339 + MCP3911_CHAN(0), 340 + MCP3911_CHAN(1), 341 + MCP3911_CHAN(2), 342 + MCP3911_CHAN(3), 343 + IIO_CHAN_SOFT_TIMESTAMP(4), 344 + }; 345 + 346 + static const struct iio_chan_spec mcp3913_channels[] = { 347 + MCP3911_CHAN(0), 348 + MCP3911_CHAN(1), 349 + MCP3911_CHAN(2), 350 + MCP3911_CHAN(3), 351 + MCP3911_CHAN(4), 352 + MCP3911_CHAN(5), 353 + IIO_CHAN_SOFT_TIMESTAMP(6), 354 + }; 355 + 356 + static const struct iio_chan_spec mcp3914_channels[] = { 357 + MCP3911_CHAN(0), 358 + MCP3911_CHAN(1), 359 + MCP3911_CHAN(2), 360 + MCP3911_CHAN(3), 361 + MCP3911_CHAN(4), 362 + MCP3911_CHAN(5), 363 + MCP3911_CHAN(6), 364 + MCP3911_CHAN(7), 365 + IIO_CHAN_SOFT_TIMESTAMP(8), 366 + }; 367 + 368 + static const struct iio_chan_spec mcp3918_channels[] = { 369 + MCP3911_CHAN(0), 370 + IIO_CHAN_SOFT_TIMESTAMP(1), 371 + }; 372 + 373 + static const struct iio_chan_spec mcp3919_channels[] = { 374 + MCP3911_CHAN(0), 375 + MCP3911_CHAN(1), 376 + MCP3911_CHAN(2), 377 + IIO_CHAN_SOFT_TIMESTAMP(3), 466 378 }; 467 379 468 380 static irqreturn_t mcp3911_trigger_handler(int irq, void *p) ··· 525 341 .len = 1, 526 342 }, { 527 343 .rx_buf = adc->rx_buf, 528 - .len = sizeof(adc->rx_buf), 344 + .len = (adc->chip->num_channels - 1) * 3, 529 345 }, 530 346 }; 531 347 int scan_index; ··· 568 384 u32 regval; 569 385 int ret; 570 386 571 - ret = device_property_read_u32(dev, "microchip,device-addr", &adc->dev_addr); 572 - 573 - /* 574 - * Fallback to "device-addr" due to historical mismatch between 575 - * dt-bindings and implementation 576 - */ 577 - if (ret) 578 - device_property_read_u32(dev, "device-addr", &adc->dev_addr); 579 - if (adc->dev_addr > 3) { 580 - return dev_err_probe(dev, -EINVAL, 581 - "invalid device address (%i). Must be in range 0-3.\n", 582 - adc->dev_addr); 583 - } 584 - dev_dbg(dev, "use device address %i\n", adc->dev_addr); 585 - 586 387 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, &regval, 2); 587 388 if (ret) 588 389 return ret; ··· 602 433 regval &= ~MCP3911_STATUSCOM_READ; 603 434 regval |= FIELD_PREP(MCP3911_STATUSCOM_READ, 0x02); 604 435 605 - return mcp3911_write(adc, MCP3911_REG_STATUSCOM, regval, 2); 436 + regval &= ~MCP3911_STATUSCOM_DRHIZ; 437 + if (device_property_read_bool(dev, "microchip,data-ready-hiz")) 438 + regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 0); 439 + else 440 + regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 1); 441 + 442 + /* Disable offset to ignore any old values in offset register */ 443 + regval &= ~MCP3911_STATUSCOM_EN_OFFCAL; 444 + 445 + ret = mcp3911_write(adc, MCP3911_REG_STATUSCOM, regval, 2); 446 + if (ret) 447 + return ret; 448 + 449 + /* Set gain to 1 for all channels */ 450 + ret = mcp3911_read(adc, MCP3911_REG_GAIN, &regval, 1); 451 + if (ret) 452 + return ret; 453 + 454 + for (int i = 0; i < adc->chip->num_channels - 1; i++) { 455 + adc->gain[i] = 1; 456 + regval &= ~MCP3911_GAIN_MASK(i); 457 + } 458 + 459 + return mcp3911_write(adc, MCP3911_REG_GAIN, regval, 1); 460 + } 461 + 462 + static int mcp3910_config(struct mcp3911 *adc) 463 + { 464 + struct device *dev = &adc->spi->dev; 465 + u32 regval; 466 + int ret; 467 + 468 + ret = mcp3911_read(adc, MCP3910_REG_CONFIG1, &regval, 3); 469 + if (ret) 470 + return ret; 471 + 472 + regval &= ~MCP3910_CONFIG1_VREFEXT; 473 + if (adc->vref) { 474 + dev_dbg(dev, "use external voltage reference\n"); 475 + regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 1); 476 + } else { 477 + dev_dbg(dev, "use internal voltage reference (1.2V)\n"); 478 + regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 0); 479 + } 480 + 481 + regval &= ~MCP3910_CONFIG1_CLKEXT; 482 + if (adc->clki) { 483 + dev_dbg(dev, "use external clock as clocksource\n"); 484 + regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 1); 485 + } else { 486 + dev_dbg(dev, "use crystal oscillator as clocksource\n"); 487 + regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 0); 488 + } 489 + 490 + ret = mcp3911_write(adc, MCP3910_REG_CONFIG1, regval, 3); 491 + if (ret) 492 + return ret; 493 + 494 + ret = mcp3911_read(adc, MCP3910_REG_STATUSCOM, &regval, 3); 495 + if (ret) 496 + return ret; 497 + 498 + /* Address counter incremented, cycle through register types */ 499 + regval &= ~MCP3910_STATUSCOM_READ; 500 + regval |= FIELD_PREP(MCP3910_STATUSCOM_READ, 0x02); 501 + 502 + regval &= ~MCP3910_STATUSCOM_DRHIZ; 503 + if (device_property_read_bool(dev, "microchip,data-ready-hiz")) 504 + regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 0); 505 + else 506 + regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 1); 507 + 508 + ret = mcp3911_write(adc, MCP3910_REG_STATUSCOM, regval, 3); 509 + if (ret) 510 + return ret; 511 + 512 + /* Set gain to 1 for all channels */ 513 + ret = mcp3911_read(adc, MCP3910_REG_GAIN, &regval, 3); 514 + if (ret) 515 + return ret; 516 + 517 + for (int i = 0; i < adc->chip->num_channels - 1; i++) { 518 + adc->gain[i] = 1; 519 + regval &= ~MCP3911_GAIN_MASK(i); 520 + } 521 + ret = mcp3911_write(adc, MCP3910_REG_GAIN, regval, 3); 522 + if (ret) 523 + return ret; 524 + 525 + /* Disable offset to ignore any old values in offset register */ 526 + return adc->chip->enable_offset(adc, 0); 606 527 } 607 528 608 529 static void mcp3911_cleanup_regulator(void *vref) ··· 730 471 731 472 adc = iio_priv(indio_dev); 732 473 adc->spi = spi; 474 + adc->chip = spi_get_device_match_data(spi); 733 475 734 476 adc->vref = devm_regulator_get_optional(dev, "vref"); 735 477 if (IS_ERR(adc->vref)) { ··· 759 499 } 760 500 } 761 501 762 - ret = mcp3911_config(adc); 502 + /* 503 + * Fallback to "device-addr" due to historical mismatch between 504 + * dt-bindings and implementation. 505 + */ 506 + ret = device_property_read_u32(dev, "microchip,device-addr", &adc->dev_addr); 763 507 if (ret) 764 - return ret; 508 + device_property_read_u32(dev, "device-addr", &adc->dev_addr); 509 + if (adc->dev_addr > 3) { 510 + return dev_err_probe(dev, -EINVAL, 511 + "invalid device address (%i). Must be in range 0-3.\n", 512 + adc->dev_addr); 513 + } 514 + dev_dbg(dev, "use device address %i\n", adc->dev_addr); 765 515 766 - if (device_property_read_bool(dev, "microchip,data-ready-hiz")) 767 - ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM, MCP3911_STATUSCOM_DRHIZ, 768 - 0, 2); 769 - else 770 - ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM, MCP3911_STATUSCOM_DRHIZ, 771 - MCP3911_STATUSCOM_DRHIZ, 2); 516 + ret = adc->chip->config(adc); 772 517 if (ret) 773 518 return ret; 774 519 ··· 782 517 return ret; 783 518 784 519 /* Set gain to 1 for all channels */ 785 - for (int i = 0; i < MCP3911_NUM_CHANNELS; i++) { 520 + for (int i = 0; i < adc->chip->num_channels - 1; i++) { 786 521 adc->gain[i] = 1; 787 522 ret = mcp3911_update(adc, MCP3911_REG_GAIN, 788 523 MCP3911_GAIN_MASK(i), ··· 796 531 indio_dev->info = &mcp3911_info; 797 532 spi_set_drvdata(spi, indio_dev); 798 533 799 - indio_dev->channels = mcp3911_channels; 800 - indio_dev->num_channels = ARRAY_SIZE(mcp3911_channels); 534 + indio_dev->channels = adc->chip->channels; 535 + indio_dev->num_channels = adc->chip->num_channels; 801 536 802 537 mutex_init(&adc->lock); 803 538 ··· 833 568 return devm_iio_device_register(dev, indio_dev); 834 569 } 835 570 571 + static const struct mcp3911_chip_info mcp3911_chip_info[] = { 572 + [MCP3910] = { 573 + .channels = mcp3910_channels, 574 + .num_channels = ARRAY_SIZE(mcp3910_channels), 575 + .config = mcp3910_config, 576 + .get_osr = mcp3910_get_osr, 577 + .set_osr = mcp3910_set_osr, 578 + .enable_offset = mcp3910_enable_offset, 579 + .get_offset = mcp3910_get_offset, 580 + .set_offset = mcp3910_set_offset, 581 + .set_scale = mcp3910_set_scale, 582 + }, 583 + [MCP3911] = { 584 + .channels = mcp3911_channels, 585 + .num_channels = ARRAY_SIZE(mcp3911_channels), 586 + .config = mcp3911_config, 587 + .get_osr = mcp3911_get_osr, 588 + .set_osr = mcp3911_set_osr, 589 + .enable_offset = mcp3911_enable_offset, 590 + .get_offset = mcp3911_get_offset, 591 + .set_offset = mcp3911_set_offset, 592 + .set_scale = mcp3911_set_scale, 593 + }, 594 + [MCP3912] = { 595 + .channels = mcp3912_channels, 596 + .num_channels = ARRAY_SIZE(mcp3912_channels), 597 + .config = mcp3910_config, 598 + .get_osr = mcp3910_get_osr, 599 + .set_osr = mcp3910_set_osr, 600 + .enable_offset = mcp3910_enable_offset, 601 + .get_offset = mcp3910_get_offset, 602 + .set_offset = mcp3910_set_offset, 603 + .set_scale = mcp3910_set_scale, 604 + }, 605 + [MCP3913] = { 606 + .channels = mcp3913_channels, 607 + .num_channels = ARRAY_SIZE(mcp3913_channels), 608 + .config = mcp3910_config, 609 + .get_osr = mcp3910_get_osr, 610 + .set_osr = mcp3910_set_osr, 611 + .enable_offset = mcp3910_enable_offset, 612 + .get_offset = mcp3910_get_offset, 613 + .set_offset = mcp3910_set_offset, 614 + .set_scale = mcp3910_set_scale, 615 + }, 616 + [MCP3914] = { 617 + .channels = mcp3914_channels, 618 + .num_channels = ARRAY_SIZE(mcp3914_channels), 619 + .config = mcp3910_config, 620 + .get_osr = mcp3910_get_osr, 621 + .set_osr = mcp3910_set_osr, 622 + .enable_offset = mcp3910_enable_offset, 623 + .get_offset = mcp3910_get_offset, 624 + .set_offset = mcp3910_set_offset, 625 + .set_scale = mcp3910_set_scale, 626 + }, 627 + [MCP3918] = { 628 + .channels = mcp3918_channels, 629 + .num_channels = ARRAY_SIZE(mcp3918_channels), 630 + .config = mcp3910_config, 631 + .get_osr = mcp3910_get_osr, 632 + .set_osr = mcp3910_set_osr, 633 + .enable_offset = mcp3910_enable_offset, 634 + .get_offset = mcp3910_get_offset, 635 + .set_offset = mcp3910_set_offset, 636 + .set_scale = mcp3910_set_scale, 637 + }, 638 + [MCP3919] = { 639 + .channels = mcp3919_channels, 640 + .num_channels = ARRAY_SIZE(mcp3919_channels), 641 + .config = mcp3910_config, 642 + .get_osr = mcp3910_get_osr, 643 + .set_osr = mcp3910_set_osr, 644 + .enable_offset = mcp3910_enable_offset, 645 + .get_offset = mcp3910_get_offset, 646 + .set_offset = mcp3910_set_offset, 647 + .set_scale = mcp3910_set_scale, 648 + }, 649 + }; 836 650 static const struct of_device_id mcp3911_dt_ids[] = { 837 - { .compatible = "microchip,mcp3911" }, 651 + { .compatible = "microchip,mcp3910", .data = &mcp3911_chip_info[MCP3910] }, 652 + { .compatible = "microchip,mcp3911", .data = &mcp3911_chip_info[MCP3911] }, 653 + { .compatible = "microchip,mcp3912", .data = &mcp3911_chip_info[MCP3912] }, 654 + { .compatible = "microchip,mcp3913", .data = &mcp3911_chip_info[MCP3913] }, 655 + { .compatible = "microchip,mcp3914", .data = &mcp3911_chip_info[MCP3914] }, 656 + { .compatible = "microchip,mcp3918", .data = &mcp3911_chip_info[MCP3918] }, 657 + { .compatible = "microchip,mcp3919", .data = &mcp3911_chip_info[MCP3919] }, 838 658 { } 839 659 }; 840 660 MODULE_DEVICE_TABLE(of, mcp3911_dt_ids); 841 661 842 662 static const struct spi_device_id mcp3911_id[] = { 843 - { "mcp3911", 0 }, 663 + { "mcp3910", (kernel_ulong_t)&mcp3911_chip_info[MCP3910] }, 664 + { "mcp3911", (kernel_ulong_t)&mcp3911_chip_info[MCP3911] }, 665 + { "mcp3912", (kernel_ulong_t)&mcp3911_chip_info[MCP3912] }, 666 + { "mcp3913", (kernel_ulong_t)&mcp3911_chip_info[MCP3913] }, 667 + { "mcp3914", (kernel_ulong_t)&mcp3911_chip_info[MCP3914] }, 668 + { "mcp3918", (kernel_ulong_t)&mcp3911_chip_info[MCP3918] }, 669 + { "mcp3919", (kernel_ulong_t)&mcp3911_chip_info[MCP3919] }, 844 670 { } 845 671 }; 846 672 MODULE_DEVICE_TABLE(spi, mcp3911_id);