Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
spi: spi-fsl-lpspi: fsl_lpspi_set_watermark(): use FIELD_PREP() to encode FIFO Control register
Instead of open coding mask and shift operations and to increase
readability use FIELD_PREP() to encode the FIFO Control register.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Link: https://patch.msgid.link/20260319-spi-fsl-lpspi-cleanups-v2-2-02b56c5d44a8@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Marc Kleine-Budde
and committed by
Mark Brown
732b903e
8292eded
+7
-4
+7
-4
drivers/spi/spi-fsl-lpspi.c
+7
-4
drivers/spi/spi-fsl-lpspi.c
···
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#define CFGR1_PCSPOL_MASK GENMASK(11, 8)
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#define CFGR1_NOSTALL BIT(3)
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#define CFGR1_HOST BIT(0)
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#define FCR_RXWATER GENMASK(18, 16)
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#define FCR_TXWATER GENMASK(2, 0)
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#define FSR_TXCOUNT (0xFF)
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#define RSR_RXEMPTY BIT(1)
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#define TCR_CPOL BIT(31)
···
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static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
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{
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u8 watermark = fsl_lpspi->watermark >> 1;
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u32 temp;
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if (!fsl_lpspi->usedma)
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temp = fsl_lpspi->watermark >> 1 |
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(fsl_lpspi->watermark >> 1) << 16;
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temp = FIELD_PREP(FCR_TXWATER, watermark) |
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FIELD_PREP(FCR_RXWATER, watermark);
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else
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temp = fsl_lpspi->watermark >> 1;
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temp = FIELD_PREP(FCR_TXWATER, watermark);
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writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
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dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
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dev_dbg(fsl_lpspi->dev, "FCR=0x%08x\n", temp);
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}
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static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)