Merge tag 'tty-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty

+1

Documentation/devicetree/bindings/serial/8250.yaml

··· 182 182 - const: ns16550a 183 183 - items: 184 184 - enum: 185 + - loongson,ls3a4000-uart 185 186 - loongson,ls3a5000-uart 186 187 - loongson,ls3a6000-uart 187 188 - loongson,ls2k2000-uart

+1

Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml

··· 56 56 items: 57 57 - enum: 58 58 - amlogic,a4-uart 59 + - amlogic,a9-uart 59 60 - amlogic,s6-uart 60 61 - amlogic,s7-uart 61 62 - amlogic,s7d-uart

+1

Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml

··· 24 24 - const: atmel,at91sam9260-usart 25 25 - items: 26 26 - enum: 27 + - microchip,lan9691-usart 27 28 - microchip,sam9x60-usart 28 29 - microchip,sam9x7-usart 29 30 - microchip,sama7d65-usart

+26

Documentation/devicetree/bindings/serial/renesas,rsci.yaml

··· 14 14 compatible: 15 15 oneOf: 16 16 - enum: 17 + - renesas,r9a08g046-rsci # RZ/G3L 17 18 - renesas,r9a09g047-rsci # RZ/G3E 18 19 - renesas,r9a09g077-rsci # RZ/T2H 19 20 ··· 141 140 clock-names: 142 141 minItems: 5 143 142 maxItems: 6 143 + 144 + required: 145 + - resets 146 + - reset-names 147 + 148 + - if: 149 + properties: 150 + compatible: 151 + contains: 152 + const: renesas,r9a08g046-rsci 153 + then: 154 + properties: 155 + interrupts: 156 + minItems: 6 157 + 158 + interrupt-names: 159 + minItems: 6 160 + 161 + clocks: 162 + minItems: 2 163 + maxItems: 3 164 + 165 + clock-names: 166 + minItems: 2 167 + maxItems: 3 144 168 145 169 required: 146 170 - resets

+1

Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml

··· 71 71 - rockchip,rk3568-uart 72 72 - rockchip,rk3576-uart 73 73 - rockchip,rk3588-uart 74 + - rockchip,rv1103b-uart 74 75 - rockchip,rv1108-uart 75 76 - rockchip,rv1126-uart 76 77 - sophgo,sg2044-uart

+1 -1

drivers/tty/hvc/hvc_iucv.c

··· 130 130 */ 131 131 static struct hvc_iucv_private *hvc_iucv_get_private(uint32_t num) 132 132 { 133 - if (num > hvc_iucv_devices) 133 + if (num >= hvc_iucv_devices) 134 134 return NULL; 135 135 return hvc_iucv_table[num]; 136 136 }

+8 -4

drivers/tty/pty.c

··· 532 532 pty_driver = tty_alloc_driver(legacy_count, 533 533 TTY_DRIVER_RESET_TERMIOS | 534 534 TTY_DRIVER_REAL_RAW | 535 - TTY_DRIVER_DYNAMIC_ALLOC); 535 + TTY_DRIVER_DYNAMIC_ALLOC | 536 + TTY_DRIVER_NO_WORKQUEUE); 536 537 if (IS_ERR(pty_driver)) 537 538 panic("Couldn't allocate pty driver"); 538 539 539 540 pty_slave_driver = tty_alloc_driver(legacy_count, 540 541 TTY_DRIVER_RESET_TERMIOS | 541 542 TTY_DRIVER_REAL_RAW | 542 - TTY_DRIVER_DYNAMIC_ALLOC); 543 + TTY_DRIVER_DYNAMIC_ALLOC | 544 + TTY_DRIVER_NO_WORKQUEUE); 543 545 if (IS_ERR(pty_slave_driver)) 544 546 panic("Couldn't allocate pty slave driver"); 545 547 ··· 851 849 TTY_DRIVER_REAL_RAW | 852 850 TTY_DRIVER_DYNAMIC_DEV | 853 851 TTY_DRIVER_DEVPTS_MEM | 854 - TTY_DRIVER_DYNAMIC_ALLOC); 852 + TTY_DRIVER_DYNAMIC_ALLOC | 853 + TTY_DRIVER_NO_WORKQUEUE); 855 854 if (IS_ERR(ptm_driver)) 856 855 panic("Couldn't allocate Unix98 ptm driver"); 857 856 pts_driver = tty_alloc_driver(NR_UNIX98_PTY_MAX, ··· 860 857 TTY_DRIVER_REAL_RAW | 861 858 TTY_DRIVER_DYNAMIC_DEV | 862 859 TTY_DRIVER_DEVPTS_MEM | 863 - TTY_DRIVER_DYNAMIC_ALLOC); 860 + TTY_DRIVER_DYNAMIC_ALLOC | 861 + TTY_DRIVER_NO_WORKQUEUE); 864 862 if (IS_ERR(pts_driver)) 865 863 panic("Couldn't allocate Unix98 pts driver"); 866 864

+1 -1

drivers/tty/serial/8250/8250_core.c

··· 524 524 525 525 struct uart_driver serial8250_reg = { 526 526 .owner = THIS_MODULE, 527 - .driver_name = "serial", 527 + .driver_name = "serial_8250", 528 528 .dev_name = "ttyS", 529 529 .major = TTY_MAJOR, 530 530 .minor = 64,

+9 -1

drivers/tty/serial/8250/8250_fintek.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /* 3 - * Probe for F81216A LPC to 4 UART 3 + * Probe for F81216A LPC to 4 UART and F81214E LPC/eSPI to 2 UART 4 4 * 5 5 * Copyright (C) 2014-2016 Ricardo Ribalda, Qtechnology A/S 6 6 */ ··· 23 23 #define CHIP_ID_F81216AD 0x1602 24 24 #define CHIP_ID_F81216E 0x1617 25 25 #define CHIP_ID_F81216H 0x0501 26 + #define CHIP_ID_F81214E 0x1417 26 27 #define CHIP_ID_F81216 0x0802 27 28 #define VENDOR_ID1 0x23 28 29 #define VENDOR_ID1_VAL 0x19 ··· 162 161 case CHIP_ID_F81216AD: 163 162 case CHIP_ID_F81216E: 164 163 case CHIP_ID_F81216H: 164 + case CHIP_ID_F81214E: 165 165 case CHIP_ID_F81216: 166 166 break; 167 167 default: ··· 187 185 case CHIP_ID_F81216AD: 188 186 case CHIP_ID_F81216E: 189 187 case CHIP_ID_F81216H: 188 + case CHIP_ID_F81214E: 190 189 case CHIP_ID_F81216: 191 190 *min = F81216_LDN_LOW; 192 191 *max = F81216_LDN_HIGH; ··· 258 255 case CHIP_ID_F81216AD: 259 256 case CHIP_ID_F81216E: 260 257 case CHIP_ID_F81216H: 258 + case CHIP_ID_F81214E: 261 259 case CHIP_ID_F81216: 262 260 sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_SHARE, 263 261 IRQ_SHARE); ··· 273 269 switch (pdata->pid) { 274 270 case CHIP_ID_F81216E: /* 128Bytes FIFO */ 275 271 case CHIP_ID_F81216H: 272 + case CHIP_ID_F81214E: 276 273 case CHIP_ID_F81966: 277 274 case CHIP_ID_F81866: 278 275 sio_write_mask_reg(pdata, FIFO_CTRL, ··· 309 304 switch (pdata->pid) { 310 305 case CHIP_ID_F81216E: 311 306 case CHIP_ID_F81216H: 307 + case CHIP_ID_F81214E: 312 308 reg = RS485; 313 309 break; 314 310 case CHIP_ID_F81966: ··· 360 354 switch (pdata->pid) { 361 355 case CHIP_ID_F81216E: 362 356 case CHIP_ID_F81216H: 357 + case CHIP_ID_F81214E: 363 358 case CHIP_ID_F81966: 364 359 case CHIP_ID_F81866: 365 360 uart->port.set_termios = fintek_8250_set_termios; ··· 453 446 break; 454 447 455 448 case CHIP_ID_F81216E: /* F81216E does not support RS485 delays */ 449 + case CHIP_ID_F81214E: /* F81214E does not support RS485 delays */ 456 450 uart->port.rs485_config = fintek_8250_rs485_config; 457 451 uart->port.rs485_supported = fintek_8250_rs485_supported; 458 452 break;

+51

drivers/tty/serial/8250/8250_pci.c

··· 100 100 #define PCI_DEVICE_ID_ADDIDATA_CPCI7420_NG 0x7025 101 101 #define PCI_DEVICE_ID_ADDIDATA_CPCI7300_NG 0x7026 102 102 103 + #define PCI_VENDOR_ID_SYSTEMBASE 0x14a1 104 + 103 105 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 104 106 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 105 107 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 ··· 2135 2133 return setup_port(priv, port, bar, offset, 0); 2136 2134 } 2137 2135 2136 + #define SB_OPTR_IMR0 0x0c /* Interrupt mask register, p0 to p7 */ 2137 + static int pci_systembase_init(struct pci_dev *dev) 2138 + { 2139 + resource_size_t iobase; 2140 + 2141 + if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 2142 + return serial_8250_warn_need_ioport(dev); 2143 + 2144 + iobase = pci_resource_start(dev, 1); 2145 + 2146 + /* This will support up to 8 ports */ 2147 + outb(0xff, iobase + SB_OPTR_IMR0); 2148 + 2149 + return 0; 2150 + } 2151 + 2152 + static void pci_systembase_exit(struct pci_dev *dev) 2153 + { 2154 + resource_size_t iobase; 2155 + 2156 + if (!IS_ENABLED(CONFIG_HAS_IOPORT)) { 2157 + serial_8250_warn_need_ioport(dev); 2158 + return; 2159 + } 2160 + 2161 + iobase = pci_resource_start(dev, 0); 2162 + outb(0x00, iobase + SB_OPTR_IMR0); 2163 + } 2164 + 2138 2165 /* 2139 2166 * Master list of serial port init/setup/exit quirks. 2140 2167 * This does not describe the general nature of the port. ··· 2511 2480 .subdevice = PCI_ANY_ID, 2512 2481 .init = pci_siig_init, 2513 2482 .setup = pci_siig_setup, 2483 + }, 2484 + /* Systembase */ 2485 + { 2486 + .vendor = PCI_VENDOR_ID_SYSTEMBASE, 2487 + .device = 0x0008, 2488 + .subvendor = PCI_ANY_ID, 2489 + .subdevice = PCI_ANY_ID, 2490 + .init = pci_systembase_init, 2491 + .setup = pci_default_setup, 2492 + .exit = pci_systembase_exit, 2514 2493 }, 2515 2494 /* 2516 2495 * Titan cards ··· 3095 3054 pbn_b0_1_921600, 3096 3055 pbn_b0_2_921600, 3097 3056 pbn_b0_4_921600, 3057 + pbn_b0_8_921600, 3098 3058 3099 3059 pbn_b0_2_1130000, 3100 3060 ··· 3293 3251 [pbn_b0_4_921600] = { 3294 3252 .flags = FL_BASE0, 3295 3253 .num_ports = 4, 3254 + .base_baud = 921600, 3255 + .uart_offset = 8, 3256 + }, 3257 + [pbn_b0_8_921600] = { 3258 + .flags = FL_BASE0, 3259 + .num_ports = 8, 3296 3260 .base_baud = 921600, 3297 3261 .uart_offset = 8, 3298 3262 }, ··· 6216 6168 { PCI_VENDOR_ID_REALTEK, 0x816b, 6217 6169 PCI_ANY_ID, PCI_ANY_ID, 6218 6170 0, 0, pbn_b0_1_115200 }, 6171 + 6172 + /* Systembase Multi I/O cards */ 6173 + { PCI_VDEVICE(SYSTEMBASE, 0x0008), pbn_b0_8_921600 }, 6219 6174 6220 6175 /* Fintek PCI serial cards */ 6221 6176 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },

+2 -2

drivers/tty/serial/8250/8250_port.c

··· 2372 2372 2373 2373 synchronize_irq(port->irq); 2374 2374 2375 - if (up->dma) 2376 - serial8250_release_dma(up); 2375 + serial8250_release_dma(up); 2376 + up->dma = NULL; 2377 2377 2378 2378 scoped_guard(uart_port_lock_irqsave, port) { 2379 2379 if (port->flags & UPF_FOURPORT) {

+5 -4

drivers/tty/serial/8250/Kconfig

··· 465 465 config SERIAL_8250_LOONGSON 466 466 tristate "Loongson 8250 based serial port" 467 467 depends on SERIAL_8250 468 - depends on LOONGARCH || COMPILE_TEST 468 + depends on LOONGARCH || MACH_LOONGSON64 || COMPILE_TEST 469 469 help 470 - If you have a machine based on LoongArch CPU you can enable 471 - its onboard serial ports by enabling this option. The option 472 - is applicable to both devicetree and ACPI, say Y to this option. 470 + If you have a machine based on LoongArch CPU or MIPS-based Loongson 471 + 3A4000 CPU you can enable its onboard serial ports by enabling this 472 + option. The option is applicable to both devicetree and ACPI, say Y 473 + to enable this option. 473 474 If unsure, say N. 474 475 475 476 config SERIAL_8250_LPC18XX

+3 -30

drivers/tty/serial/Kconfig

··· 255 255 256 256 config SERIAL_TEGRA 257 257 tristate "NVIDIA Tegra20/30 SoC serial controller" 258 - depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST 258 + depends on ARCH_TEGRA || COMPILE_TEST 259 259 select SERIAL_CORE 260 260 help 261 261 Support for the on-chip UARTs on the NVIDIA Tegra series SOCs 262 262 providing /dev/ttyTHS0, 1, 2, 3 and 4 (note, some machines may not 263 263 provide all of these ports, depending on how the serial port 264 - are enabled). This driver uses the APB DMA to achieve higher baudrate 265 - and better performance. 264 + are enabled). 266 265 267 266 config SERIAL_TEGRA_TCU 268 267 tristate "NVIDIA Tegra Combined UART" ··· 802 803 803 804 config SERIAL_PIC32 804 805 tristate "Microchip PIC32 serial support" 805 - depends on MACH_PIC32 || (MIPS && COMPILE_TEST) 806 + depends on MACH_PIC32 || COMPILE_TEST 806 807 select SERIAL_CORE 807 808 help 808 809 If you have a PIC32, this driver supports the serial ports. ··· 1591 1592 (/dev/tty0) will still be used as the system console by default, 1592 1593 but you can alter that using a kernel command line option such as 1593 1594 "console=ttyNVTx". 1594 - 1595 - config SERIAL_ESP32 1596 - tristate "Espressif ESP32 UART support" 1597 - depends on XTENSA_PLATFORM_ESP32 || (COMPILE_TEST && OF) 1598 - select SERIAL_CORE 1599 - select SERIAL_CORE_CONSOLE 1600 - select SERIAL_EARLYCON 1601 - help 1602 - Driver for the UART controllers of the Espressif ESP32xx SoCs. 1603 - When earlycon option is enabled the following kernel command line 1604 - snippets may be used: 1605 - earlycon=esp32s3uart,mmio32,0x60000000,115200n8,40000000 1606 - earlycon=esp32uart,mmio32,0x3ff40000,115200n8 1607 - 1608 - config SERIAL_ESP32_ACM 1609 - tristate "Espressif ESP32 USB ACM gadget support" 1610 - depends on XTENSA_PLATFORM_ESP32 || (COMPILE_TEST && OF) 1611 - select SERIAL_CORE 1612 - select SERIAL_CORE_CONSOLE 1613 - select SERIAL_EARLYCON 1614 - help 1615 - Driver for the CDC ACM gadget controller of the Espressif ESP32S3 1616 - SoCs that share separate USB controller with the JTAG adapter. 1617 - When earlycon option is enabled the following kernel command line 1618 - snippet may be used: 1619 - earlycon=esp32s3acm,mmio32,0x60038000 1620 1595 1621 1596 endmenu 1622 1597

-2

drivers/tty/serial/Makefile

··· 37 37 obj-$(CONFIG_SERIAL_CPM) += cpm_uart.o 38 38 obj-$(CONFIG_SERIAL_CONEXANT_DIGICOLOR) += digicolor-usart.o 39 39 obj-$(CONFIG_SERIAL_DZ) += dz.o 40 - obj-$(CONFIG_SERIAL_ESP32) += esp32_uart.o 41 - obj-$(CONFIG_SERIAL_ESP32_ACM) += esp32_acm.o 42 40 obj-$(CONFIG_SERIAL_FSL_LINFLEXUART) += fsl_linflexuart.o 43 41 obj-$(CONFIG_SERIAL_FSL_LPUART) += fsl_lpuart.o 44 42 obj-$(CONFIG_SERIAL_ICOM) += icom.o

+126 -27

drivers/tty/serial/amba-pl011.c

··· 114 114 bool cts_event_workaround; 115 115 bool always_enabled; 116 116 bool fixed_options; 117 + bool skip_ibrd_fbrd; 118 + bool set_uartclk_rate; 117 119 118 120 unsigned int (*get_fifosize)(struct amba_device *dev); 119 121 }; ··· 216 214 .always_enabled = false, 217 215 .fixed_options = false, 218 216 .get_fifosize = get_fifosize_st, 217 + }; 218 + 219 + static unsigned int get_fifosize_nvidia(struct amba_device *dev) 220 + { 221 + return 32; 222 + } 223 + 224 + static struct vendor_data vendor_nvidia = { 225 + .reg_offset = pl011_std_offsets, 226 + .ifls = UART011_IFLS_RX4_8 | UART011_IFLS_TX4_8, 227 + .fr_busy = UART01x_FR_BUSY, 228 + .fr_dsr = UART01x_FR_DSR, 229 + .fr_cts = UART01x_FR_CTS, 230 + .fr_ri = UART011_FR_RI, 231 + .oversampling = false, 232 + .dma_threshold = false, 233 + .cts_event_workaround = false, 234 + .always_enabled = false, 235 + .fixed_options = false, 236 + .skip_ibrd_fbrd = true, 237 + .set_uartclk_rate = true, 238 + .get_fifosize = get_fifosize_nvidia, 219 239 }; 220 240 221 241 /* Deals with DMA transactions */ ··· 649 625 count = PL011_DMA_BUFFER_SIZE; 650 626 651 627 count = kfifo_out_peek(&tport->xmit_fifo, dmatx->buf, count); 628 + 629 + /* 630 + * Align the TX buffer length to the DMA controller's copy_align 631 + * requirements. Some DMA controllers (e.g., Tegra GPC DMA) require 632 + * word-aligned transfers. Unaligned bytes will be sent via PIO. 633 + */ 634 + if (chan->device->copy_align) 635 + count = ALIGN_DOWN(count, 1 << chan->device->copy_align); 636 + 652 637 dmatx->len = count; 653 638 dmatx->dma = dma_map_single(dma_dev->dev, dmatx->buf, count, 654 639 DMA_TO_DEVICE); ··· 2128 2095 unsigned int lcr_h, old_cr; 2129 2096 unsigned long flags; 2130 2097 unsigned int baud, quot, clkdiv; 2098 + unsigned int max_baud; 2131 2099 unsigned int bits; 2132 2100 2133 2101 if (uap->vendor->oversampling) ··· 2136 2102 else 2137 2103 clkdiv = 16; 2138 2104 2105 + max_baud = port->uartclk / clkdiv; 2106 + 2107 + if (uap->vendor->set_uartclk_rate) { 2108 + long max_clkrate = clk_round_rate(uap->clk, UINT_MAX); 2109 + 2110 + /* 2111 + * Clock is reprogrammable - determine max baud from the clock's 2112 + * maximum rate, not the current uartclk. 2113 + */ 2114 + if (max_clkrate > 0) 2115 + max_baud = max_clkrate / clkdiv; 2116 + } 2117 + 2139 2118 /* 2140 2119 * Ask the core to calculate the divisor for us. 2141 2120 */ 2142 - baud = uart_get_baud_rate(port, termios, old, 0, 2143 - port->uartclk / clkdiv); 2121 + baud = uart_get_baud_rate(port, termios, old, 0, max_baud); 2122 + 2123 + if (uap->vendor->set_uartclk_rate) { 2124 + int err; 2125 + 2126 + err = clk_set_rate(uap->clk, baud * clkdiv); 2127 + if (err) { 2128 + dev_err(port->dev, "Failed to set clock rate: %d\n", err); 2129 + return; 2130 + } 2131 + } 2132 + 2144 2133 #ifdef CONFIG_DMA_ENGINE 2145 2134 /* 2146 2135 * Adjust RX DMA polling rate with baud rate if not specified. ··· 2171 2114 if (uap->dmarx.auto_poll_rate) 2172 2115 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); 2173 2116 #endif 2174 - 2175 - if (baud > port->uartclk / 16) 2176 - quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); 2177 - else 2178 - quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); 2179 2117 2180 2118 switch (termios->c_cflag & CSIZE) { 2181 2119 case CS5: ··· 2242 2190 old_cr &= ~ST_UART011_CR_OVSFACT; 2243 2191 } 2244 2192 2245 - /* 2246 - * Workaround for the ST Micro oversampling variants to 2247 - * increase the bitrate slightly, by lowering the divisor, 2248 - * to avoid delayed sampling of start bit at high speeds, 2249 - * else we see data corruption. 2250 - */ 2251 - if (uap->vendor->oversampling) { 2252 - if (baud >= 3000000 && baud < 3250000 && quot > 1) 2253 - quot -= 1; 2254 - else if (baud > 3250000 && quot > 2) 2255 - quot -= 2; 2193 + if (!uap->vendor->skip_ibrd_fbrd) { 2194 + if (baud > port->uartclk / 16) 2195 + quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); 2196 + else 2197 + quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); 2198 + 2199 + /* 2200 + * Workaround for the ST Micro oversampling variants to 2201 + * increase the bitrate slightly, by lowering the divisor, 2202 + * to avoid delayed sampling of start bit at high speeds, 2203 + * else we see data corruption. 2204 + */ 2205 + if (uap->vendor->oversampling) { 2206 + if (baud >= 3000000 && baud < 3250000 && quot > 1) 2207 + quot -= 1; 2208 + else if (baud > 3250000 && quot > 2) 2209 + quot -= 2; 2210 + } 2211 + /* Set baud rate */ 2212 + pl011_write(quot & 0x3f, uap, REG_FBRD); 2213 + pl011_write(quot >> 6, uap, REG_IBRD); 2256 2214 } 2257 - /* Set baud rate */ 2258 - pl011_write(quot & 0x3f, uap, REG_FBRD); 2259 - pl011_write(quot >> 6, uap, REG_IBRD); 2260 2215 2261 2216 /* 2262 2217 * ----------v----------v----------v----------v----- ··· 2433 2374 int *parity, int *bits) 2434 2375 { 2435 2376 unsigned int lcr_h, ibrd, fbrd; 2377 + unsigned int clkdiv; 2436 2378 2437 2379 if (!(pl011_read(uap, REG_CR) & UART01x_CR_UARTEN)) 2438 2380 return; ··· 2453 2393 else 2454 2394 *bits = 8; 2455 2395 2456 - ibrd = pl011_read(uap, REG_IBRD); 2457 - fbrd = pl011_read(uap, REG_FBRD); 2396 + if (uap->vendor->skip_ibrd_fbrd) { 2397 + clkdiv = 64; 2398 + } else { 2399 + ibrd = pl011_read(uap, REG_IBRD); 2400 + fbrd = pl011_read(uap, REG_FBRD); 2401 + clkdiv = 64 * ibrd + fbrd; 2402 + } 2458 2403 2459 - *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); 2404 + *baud = uap->port.uartclk * 4 / clkdiv; 2460 2405 2461 2406 if (uap->vendor->oversampling && 2462 2407 (pl011_read(uap, REG_CR) & ST_UART011_CR_OVSFACT)) ··· 2766 2701 static int __init pl011_early_console_setup(struct earlycon_device *device, 2767 2702 const char *opt) 2768 2703 { 2704 + unsigned int cr; 2705 + 2706 + if (!device->port.membase) 2707 + return -ENODEV; 2708 + 2709 + device->con->write = pl011_early_write; 2710 + device->con->read = pl011_early_read; 2711 + 2712 + if (device->port.iotype == UPIO_MEM32) 2713 + cr = readl(device->port.membase + UART011_CR); 2714 + else 2715 + cr = readw(device->port.membase + UART011_CR); 2716 + cr &= UART011_CR_RTS | UART011_CR_DTR; 2717 + cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; 2718 + if (device->port.iotype == UPIO_MEM32) 2719 + writel(cr, device->port.membase + UART011_CR); 2720 + else 2721 + writew(cr, device->port.membase + UART011_CR); 2722 + 2723 + return 0; 2724 + } 2725 + 2726 + OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); 2727 + 2728 + /* 2729 + * The SBSA UART has no defined control register and is assumed to 2730 + * be pre-enabled by firmware, so we do not write to UART011_CR. 2731 + */ 2732 + static int __init sbsa_uart_early_console_setup(struct earlycon_device *device, 2733 + const char *opt) 2734 + { 2769 2735 if (!device->port.membase) 2770 2736 return -ENODEV; 2771 2737 ··· 2806 2710 return 0; 2807 2711 } 2808 2712 2809 - OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); 2810 - 2811 - OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup); 2713 + OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", sbsa_uart_early_console_setup); 2812 2714 2813 2715 /* 2814 2716 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by ··· 3174 3080 .id = 0x00380802, 3175 3081 .mask = 0x00ffffff, 3176 3082 .data = &vendor_st, 3083 + }, 3084 + { 3085 + .id = 0x0006b011, 3086 + .mask = 0x000fffff, 3087 + .data = &vendor_nvidia, 3177 3088 }, 3178 3089 { 0, 0 }, 3179 3090 };

+1 -1

drivers/tty/serial/apbuart.c

··· 505 505 506 506 static struct uart_driver grlib_apbuart_driver = { 507 507 .owner = THIS_MODULE, 508 - .driver_name = "serial", 508 + .driver_name = "serial_apbuart", 509 509 .dev_name = "ttyS", 510 510 .major = SERIAL_APBUART_MAJOR, 511 511 .minor = SERIAL_APBUART_MINOR,

+1 -1

drivers/tty/serial/atmel_serial.c

··· 1927 1927 atmel_uart_writel(port, ATMEL_US_FMR, fmr); 1928 1928 } 1929 1929 1930 - /* Save current CSR for comparison in atmel_tasklet_func() */ 1930 + /* Save current CSR for comparison in atmel_handle_status() */ 1931 1931 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR); 1932 1932 1933 1933 /*

+1 -1

drivers/tty/serial/dz.c

··· 914 914 915 915 static struct uart_driver dz_reg = { 916 916 .owner = THIS_MODULE, 917 - .driver_name = "serial", 917 + .driver_name = "serial_dz", 918 918 .dev_name = "ttyS", 919 919 .major = TTY_MAJOR, 920 920 .minor = 64,

-459

drivers/tty/serial/esp32_acm.c

··· 1 - // SPDX-License-Identifier: GPL-2.0-or-later 2 - 3 - #include <linux/bitfield.h> 4 - #include <linux/bits.h> 5 - #include <linux/console.h> 6 - #include <linux/delay.h> 7 - #include <linux/io.h> 8 - #include <linux/irq.h> 9 - #include <linux/module.h> 10 - #include <linux/of.h> 11 - #include <linux/platform_device.h> 12 - #include <linux/serial_core.h> 13 - #include <linux/slab.h> 14 - #include <linux/tty_flip.h> 15 - #include <asm/serial.h> 16 - 17 - #define DRIVER_NAME "esp32s3-acm" 18 - #define DEV_NAME "ttyGS" 19 - #define UART_NR 4 20 - 21 - #define ESP32S3_ACM_TX_FIFO_SIZE 64 22 - 23 - #define USB_SERIAL_JTAG_EP1_REG 0x00 24 - #define USB_SERIAL_JTAG_EP1_CONF_REG 0x04 25 - #define USB_SERIAL_JTAG_WR_DONE BIT(0) 26 - #define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE BIT(1) 27 - #define USB_SERIAL_JTAG_INT_ST_REG 0x0c 28 - #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST BIT(2) 29 - #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST BIT(3) 30 - #define USB_SERIAL_JTAG_INT_ENA_REG 0x10 31 - #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA BIT(2) 32 - #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA BIT(3) 33 - #define USB_SERIAL_JTAG_INT_CLR_REG 0x14 34 - #define USB_SERIAL_JTAG_IN_EP1_ST_REG 0x2c 35 - #define USB_SERIAL_JTAG_IN_EP1_WR_ADDR GENMASK(8, 2) 36 - #define USB_SERIAL_JTAG_OUT_EP1_ST_REG 0x3c 37 - #define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT GENMASK(22, 16) 38 - 39 - static const struct of_device_id esp32s3_acm_dt_ids[] = { 40 - { 41 - .compatible = "esp,esp32s3-acm", 42 - }, { /* sentinel */ } 43 - }; 44 - MODULE_DEVICE_TABLE(of, esp32s3_acm_dt_ids); 45 - 46 - static struct uart_port *esp32s3_acm_ports[UART_NR]; 47 - 48 - static void esp32s3_acm_write(struct uart_port *port, unsigned long reg, u32 v) 49 - { 50 - writel(v, port->membase + reg); 51 - } 52 - 53 - static u32 esp32s3_acm_read(struct uart_port *port, unsigned long reg) 54 - { 55 - return readl(port->membase + reg); 56 - } 57 - 58 - static u32 esp32s3_acm_tx_fifo_free(struct uart_port *port) 59 - { 60 - u32 status = esp32s3_acm_read(port, USB_SERIAL_JTAG_EP1_CONF_REG); 61 - 62 - return status & USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE; 63 - } 64 - 65 - static u32 esp32s3_acm_tx_fifo_cnt(struct uart_port *port) 66 - { 67 - u32 status = esp32s3_acm_read(port, USB_SERIAL_JTAG_IN_EP1_ST_REG); 68 - 69 - return FIELD_GET(USB_SERIAL_JTAG_IN_EP1_WR_ADDR, status); 70 - } 71 - 72 - static u32 esp32s3_acm_rx_fifo_cnt(struct uart_port *port) 73 - { 74 - u32 status = esp32s3_acm_read(port, USB_SERIAL_JTAG_OUT_EP1_ST_REG); 75 - 76 - return FIELD_GET(USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT, status); 77 - } 78 - 79 - /* return TIOCSER_TEMT when transmitter is not busy */ 80 - static unsigned int esp32s3_acm_tx_empty(struct uart_port *port) 81 - { 82 - return esp32s3_acm_tx_fifo_cnt(port) == 0 ? TIOCSER_TEMT : 0; 83 - } 84 - 85 - static void esp32s3_acm_set_mctrl(struct uart_port *port, unsigned int mctrl) 86 - { 87 - } 88 - 89 - static unsigned int esp32s3_acm_get_mctrl(struct uart_port *port) 90 - { 91 - return TIOCM_CAR; 92 - } 93 - 94 - static void esp32s3_acm_stop_tx(struct uart_port *port) 95 - { 96 - u32 int_ena; 97 - 98 - int_ena = esp32s3_acm_read(port, USB_SERIAL_JTAG_INT_ENA_REG); 99 - int_ena &= ~USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA; 100 - esp32s3_acm_write(port, USB_SERIAL_JTAG_INT_ENA_REG, int_ena); 101 - } 102 - 103 - static void esp32s3_acm_rxint(struct uart_port *port) 104 - { 105 - struct tty_port *tty_port = &port->state->port; 106 - u32 rx_fifo_cnt = esp32s3_acm_rx_fifo_cnt(port); 107 - unsigned long flags; 108 - u32 i; 109 - 110 - if (!rx_fifo_cnt) 111 - return; 112 - 113 - spin_lock_irqsave(&port->lock, flags); 114 - 115 - for (i = 0; i < rx_fifo_cnt; ++i) { 116 - u32 rx = esp32s3_acm_read(port, USB_SERIAL_JTAG_EP1_REG); 117 - 118 - ++port->icount.rx; 119 - tty_insert_flip_char(tty_port, rx, TTY_NORMAL); 120 - } 121 - spin_unlock_irqrestore(&port->lock, flags); 122 - 123 - tty_flip_buffer_push(tty_port); 124 - } 125 - 126 - static void esp32s3_acm_push(struct uart_port *port) 127 - { 128 - if (esp32s3_acm_tx_fifo_free(port)) 129 - esp32s3_acm_write(port, USB_SERIAL_JTAG_EP1_CONF_REG, 130 - USB_SERIAL_JTAG_WR_DONE); 131 - } 132 - 133 - static void esp32s3_acm_put_char(struct uart_port *port, u8 c) 134 - { 135 - esp32s3_acm_write(port, USB_SERIAL_JTAG_EP1_REG, c); 136 - } 137 - 138 - static void esp32s3_acm_put_char_sync(struct uart_port *port, u8 c) 139 - { 140 - unsigned long timeout = jiffies + HZ; 141 - 142 - while (!esp32s3_acm_tx_fifo_free(port)) { 143 - if (time_after(jiffies, timeout)) { 144 - dev_warn(port->dev, "timeout waiting for TX FIFO\n"); 145 - return; 146 - } 147 - cpu_relax(); 148 - } 149 - esp32s3_acm_put_char(port, c); 150 - esp32s3_acm_push(port); 151 - } 152 - 153 - static void esp32s3_acm_transmit_buffer(struct uart_port *port) 154 - { 155 - u32 tx_fifo_used; 156 - unsigned int pending; 157 - u8 ch; 158 - 159 - if (!esp32s3_acm_tx_fifo_free(port)) 160 - return; 161 - 162 - tx_fifo_used = esp32s3_acm_tx_fifo_cnt(port); 163 - pending = uart_port_tx_limited(port, ch, 164 - ESP32S3_ACM_TX_FIFO_SIZE - tx_fifo_used, 165 - true, esp32s3_acm_put_char(port, ch), 166 - ({})); 167 - if (pending) { 168 - u32 int_ena; 169 - 170 - int_ena = esp32s3_acm_read(port, USB_SERIAL_JTAG_INT_ENA_REG); 171 - int_ena |= USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA; 172 - esp32s3_acm_write(port, USB_SERIAL_JTAG_INT_ENA_REG, int_ena); 173 - } 174 - esp32s3_acm_push(port); 175 - } 176 - 177 - static void esp32s3_acm_txint(struct uart_port *port) 178 - { 179 - esp32s3_acm_transmit_buffer(port); 180 - } 181 - 182 - static irqreturn_t esp32s3_acm_int(int irq, void *dev_id) 183 - { 184 - struct uart_port *port = dev_id; 185 - u32 status; 186 - 187 - status = esp32s3_acm_read(port, USB_SERIAL_JTAG_INT_ST_REG); 188 - esp32s3_acm_write(port, USB_SERIAL_JTAG_INT_CLR_REG, status); 189 - 190 - if (status & USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST) 191 - esp32s3_acm_rxint(port); 192 - if (status & USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST) 193 - esp32s3_acm_txint(port); 194 - 195 - return IRQ_RETVAL(status); 196 - } 197 - 198 - static void esp32s3_acm_start_tx(struct uart_port *port) 199 - { 200 - esp32s3_acm_transmit_buffer(port); 201 - } 202 - 203 - static void esp32s3_acm_stop_rx(struct uart_port *port) 204 - { 205 - u32 int_ena; 206 - 207 - int_ena = esp32s3_acm_read(port, USB_SERIAL_JTAG_INT_ENA_REG); 208 - int_ena &= ~USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA; 209 - esp32s3_acm_write(port, USB_SERIAL_JTAG_INT_ENA_REG, int_ena); 210 - } 211 - 212 - static int esp32s3_acm_startup(struct uart_port *port) 213 - { 214 - int ret; 215 - 216 - ret = request_irq(port->irq, esp32s3_acm_int, 0, DRIVER_NAME, port); 217 - if (ret) 218 - return ret; 219 - esp32s3_acm_write(port, USB_SERIAL_JTAG_INT_ENA_REG, 220 - USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA); 221 - 222 - return 0; 223 - } 224 - 225 - static void esp32s3_acm_shutdown(struct uart_port *port) 226 - { 227 - esp32s3_acm_write(port, USB_SERIAL_JTAG_INT_ENA_REG, 0); 228 - free_irq(port->irq, port); 229 - } 230 - 231 - static void esp32s3_acm_set_termios(struct uart_port *port, 232 - struct ktermios *termios, 233 - const struct ktermios *old) 234 - { 235 - } 236 - 237 - static const char *esp32s3_acm_type(struct uart_port *port) 238 - { 239 - return "ESP32S3 ACM"; 240 - } 241 - 242 - /* configure/auto-configure the port */ 243 - static void esp32s3_acm_config_port(struct uart_port *port, int flags) 244 - { 245 - if (flags & UART_CONFIG_TYPE) 246 - port->type = PORT_GENERIC; 247 - } 248 - 249 - #ifdef CONFIG_CONSOLE_POLL 250 - static void esp32s3_acm_poll_put_char(struct uart_port *port, unsigned char c) 251 - { 252 - esp32s3_acm_put_char_sync(port, c); 253 - } 254 - 255 - static int esp32s3_acm_poll_get_char(struct uart_port *port) 256 - { 257 - if (esp32s3_acm_rx_fifo_cnt(port)) 258 - return esp32s3_acm_read(port, USB_SERIAL_JTAG_EP1_REG); 259 - else 260 - return NO_POLL_CHAR; 261 - } 262 - #endif 263 - 264 - static const struct uart_ops esp32s3_acm_pops = { 265 - .tx_empty = esp32s3_acm_tx_empty, 266 - .set_mctrl = esp32s3_acm_set_mctrl, 267 - .get_mctrl = esp32s3_acm_get_mctrl, 268 - .stop_tx = esp32s3_acm_stop_tx, 269 - .start_tx = esp32s3_acm_start_tx, 270 - .stop_rx = esp32s3_acm_stop_rx, 271 - .startup = esp32s3_acm_startup, 272 - .shutdown = esp32s3_acm_shutdown, 273 - .set_termios = esp32s3_acm_set_termios, 274 - .type = esp32s3_acm_type, 275 - .config_port = esp32s3_acm_config_port, 276 - #ifdef CONFIG_CONSOLE_POLL 277 - .poll_put_char = esp32s3_acm_poll_put_char, 278 - .poll_get_char = esp32s3_acm_poll_get_char, 279 - #endif 280 - }; 281 - 282 - static void esp32s3_acm_string_write(struct uart_port *port, const char *s, 283 - unsigned int count) 284 - { 285 - uart_console_write(port, s, count, esp32s3_acm_put_char_sync); 286 - } 287 - 288 - static void 289 - esp32s3_acm_console_write(struct console *co, const char *s, unsigned int count) 290 - { 291 - struct uart_port *port = esp32s3_acm_ports[co->index]; 292 - unsigned long flags; 293 - bool locked = true; 294 - 295 - if (port->sysrq) 296 - locked = false; 297 - else if (oops_in_progress) 298 - locked = spin_trylock_irqsave(&port->lock, flags); 299 - else 300 - spin_lock_irqsave(&port->lock, flags); 301 - 302 - esp32s3_acm_string_write(port, s, count); 303 - 304 - if (locked) 305 - spin_unlock_irqrestore(&port->lock, flags); 306 - } 307 - 308 - static struct uart_driver esp32s3_acm_reg; 309 - static struct console esp32s3_acm_console = { 310 - .name = DEV_NAME, 311 - .write = esp32s3_acm_console_write, 312 - .device = uart_console_device, 313 - .flags = CON_PRINTBUFFER, 314 - .index = -1, 315 - .data = &esp32s3_acm_reg, 316 - }; 317 - 318 - static void esp32s3_acm_earlycon_write(struct console *con, const char *s, 319 - unsigned int n) 320 - { 321 - struct earlycon_device *dev = con->data; 322 - 323 - uart_console_write(&dev->port, s, n, esp32s3_acm_put_char_sync); 324 - } 325 - 326 - #ifdef CONFIG_CONSOLE_POLL 327 - static int esp32s3_acm_earlycon_read(struct console *con, char *s, unsigned int n) 328 - { 329 - struct earlycon_device *dev = con->data; 330 - unsigned int num_read = 0; 331 - 332 - while (num_read < n) { 333 - int c = esp32s3_acm_poll_get_char(&dev->port); 334 - 335 - if (c == NO_POLL_CHAR) 336 - break; 337 - s[num_read++] = c; 338 - } 339 - return num_read; 340 - } 341 - #endif 342 - 343 - static int __init esp32s3_acm_early_console_setup(struct earlycon_device *device, 344 - const char *options) 345 - { 346 - if (!device->port.membase) 347 - return -ENODEV; 348 - 349 - device->con->write = esp32s3_acm_earlycon_write; 350 - #ifdef CONFIG_CONSOLE_POLL 351 - device->con->read = esp32s3_acm_earlycon_read; 352 - #endif 353 - return 0; 354 - } 355 - 356 - OF_EARLYCON_DECLARE(esp32s3acm, "esp,esp32s3-acm", 357 - esp32s3_acm_early_console_setup); 358 - 359 - static struct uart_driver esp32s3_acm_reg = { 360 - .owner = THIS_MODULE, 361 - .driver_name = DRIVER_NAME, 362 - .dev_name = DEV_NAME, 363 - .nr = ARRAY_SIZE(esp32s3_acm_ports), 364 - .cons = &esp32s3_acm_console, 365 - }; 366 - 367 - static int esp32s3_acm_probe(struct platform_device *pdev) 368 - { 369 - struct device_node *np = pdev->dev.of_node; 370 - struct uart_port *port; 371 - struct resource *res; 372 - int ret; 373 - 374 - port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 375 - if (!port) 376 - return -ENOMEM; 377 - 378 - ret = of_alias_get_id(np, "serial"); 379 - if (ret < 0) { 380 - dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 381 - return ret; 382 - } 383 - if (ret >= UART_NR) { 384 - dev_err(&pdev->dev, "driver limited to %d serial ports\n", 385 - UART_NR); 386 - return -ENOMEM; 387 - } 388 - 389 - port->line = ret; 390 - 391 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 392 - if (!res) 393 - return -ENODEV; 394 - 395 - port->mapbase = res->start; 396 - port->membase = devm_ioremap_resource(&pdev->dev, res); 397 - if (IS_ERR(port->membase)) 398 - return PTR_ERR(port->membase); 399 - 400 - port->dev = &pdev->dev; 401 - port->type = PORT_GENERIC; 402 - port->iotype = UPIO_MEM; 403 - port->irq = platform_get_irq(pdev, 0); 404 - port->ops = &esp32s3_acm_pops; 405 - port->flags = UPF_BOOT_AUTOCONF; 406 - port->has_sysrq = 1; 407 - port->fifosize = ESP32S3_ACM_TX_FIFO_SIZE; 408 - 409 - esp32s3_acm_ports[port->line] = port; 410 - 411 - platform_set_drvdata(pdev, port); 412 - 413 - return uart_add_one_port(&esp32s3_acm_reg, port); 414 - } 415 - 416 - static void esp32s3_acm_remove(struct platform_device *pdev) 417 - { 418 - struct uart_port *port = platform_get_drvdata(pdev); 419 - 420 - uart_remove_one_port(&esp32s3_acm_reg, port); 421 - } 422 - 423 - 424 - static struct platform_driver esp32s3_acm_driver = { 425 - .probe = esp32s3_acm_probe, 426 - .remove = esp32s3_acm_remove, 427 - .driver = { 428 - .name = DRIVER_NAME, 429 - .of_match_table = esp32s3_acm_dt_ids, 430 - }, 431 - }; 432 - 433 - static int __init esp32s3_acm_init(void) 434 - { 435 - int ret; 436 - 437 - ret = uart_register_driver(&esp32s3_acm_reg); 438 - if (ret) 439 - return ret; 440 - 441 - ret = platform_driver_register(&esp32s3_acm_driver); 442 - if (ret) 443 - uart_unregister_driver(&esp32s3_acm_reg); 444 - 445 - return ret; 446 - } 447 - 448 - static void __exit esp32s3_acm_exit(void) 449 - { 450 - platform_driver_unregister(&esp32s3_acm_driver); 451 - uart_unregister_driver(&esp32s3_acm_reg); 452 - } 453 - 454 - module_init(esp32s3_acm_init); 455 - module_exit(esp32s3_acm_exit); 456 - 457 - MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>"); 458 - MODULE_DESCRIPTION("Espressif ESP32 USB ACM gadget support"); 459 - MODULE_LICENSE("GPL");

-779

drivers/tty/serial/esp32_uart.c

··· 1 - // SPDX-License-Identifier: GPL-2.0-or-later 2 - 3 - #include <linux/bitfield.h> 4 - #include <linux/bits.h> 5 - #include <linux/clk.h> 6 - #include <linux/console.h> 7 - #include <linux/delay.h> 8 - #include <linux/io.h> 9 - #include <linux/irq.h> 10 - #include <linux/module.h> 11 - #include <linux/of.h> 12 - #include <linux/platform_device.h> 13 - #include <linux/property.h> 14 - #include <linux/serial_core.h> 15 - #include <linux/slab.h> 16 - #include <linux/tty_flip.h> 17 - #include <asm/serial.h> 18 - 19 - #define DRIVER_NAME "esp32-uart" 20 - #define DEV_NAME "ttyS" 21 - #define UART_NR 3 22 - 23 - #define ESP32_UART_TX_FIFO_SIZE 127 24 - #define ESP32_UART_RX_FIFO_SIZE 127 25 - 26 - #define UART_FIFO_REG 0x00 27 - #define UART_INT_RAW_REG 0x04 28 - #define UART_INT_ST_REG 0x08 29 - #define UART_INT_ENA_REG 0x0c 30 - #define UART_INT_CLR_REG 0x10 31 - #define UART_RXFIFO_FULL_INT BIT(0) 32 - #define UART_TXFIFO_EMPTY_INT BIT(1) 33 - #define UART_BRK_DET_INT BIT(7) 34 - #define UART_CLKDIV_REG 0x14 35 - #define ESP32_UART_CLKDIV GENMASK(19, 0) 36 - #define ESP32S3_UART_CLKDIV GENMASK(11, 0) 37 - #define UART_CLKDIV_SHIFT 0 38 - #define UART_CLKDIV_FRAG GENMASK(23, 20) 39 - #define UART_STATUS_REG 0x1c 40 - #define ESP32_UART_RXFIFO_CNT GENMASK(7, 0) 41 - #define ESP32S3_UART_RXFIFO_CNT GENMASK(9, 0) 42 - #define UART_RXFIFO_CNT_SHIFT 0 43 - #define UART_DSRN BIT(13) 44 - #define UART_CTSN BIT(14) 45 - #define ESP32_UART_TXFIFO_CNT GENMASK(23, 16) 46 - #define ESP32S3_UART_TXFIFO_CNT GENMASK(25, 16) 47 - #define UART_TXFIFO_CNT_SHIFT 16 48 - #define UART_CONF0_REG 0x20 49 - #define UART_PARITY BIT(0) 50 - #define UART_PARITY_EN BIT(1) 51 - #define UART_BIT_NUM GENMASK(3, 2) 52 - #define UART_BIT_NUM_5 0 53 - #define UART_BIT_NUM_6 1 54 - #define UART_BIT_NUM_7 2 55 - #define UART_BIT_NUM_8 3 56 - #define UART_STOP_BIT_NUM GENMASK(5, 4) 57 - #define UART_STOP_BIT_NUM_1 1 58 - #define UART_STOP_BIT_NUM_2 3 59 - #define UART_SW_RTS BIT(6) 60 - #define UART_SW_DTR BIT(7) 61 - #define UART_LOOPBACK BIT(14) 62 - #define UART_TX_FLOW_EN BIT(15) 63 - #define UART_RTS_INV BIT(23) 64 - #define UART_DTR_INV BIT(24) 65 - #define UART_CONF1_REG 0x24 66 - #define UART_RXFIFO_FULL_THRHD_SHIFT 0 67 - #define ESP32_UART_TXFIFO_EMPTY_THRHD_SHIFT 8 68 - #define ESP32S3_UART_TXFIFO_EMPTY_THRHD_SHIFT 10 69 - #define ESP32_UART_RX_FLOW_EN BIT(23) 70 - #define ESP32S3_UART_RX_FLOW_EN BIT(22) 71 - #define ESP32S3_UART_CLK_CONF_REG 0x78 72 - #define ESP32S3_UART_SCLK_DIV_B GENMASK(5, 0) 73 - #define ESP32S3_UART_SCLK_DIV_A GENMASK(11, 6) 74 - #define ESP32S3_UART_SCLK_DIV_NUM GENMASK(19, 12) 75 - #define ESP32S3_UART_SCLK_SEL GENMASK(21, 20) 76 - #define APB_CLK 1 77 - #define RC_FAST_CLK 2 78 - #define XTAL_CLK 3 79 - #define ESP32S3_UART_SCLK_EN BIT(22) 80 - #define ESP32S3_UART_RST_CORE BIT(23) 81 - #define ESP32S3_UART_TX_SCLK_EN BIT(24) 82 - #define ESP32S3_UART_RX_SCLK_EN BIT(25) 83 - #define ESP32S3_UART_TX_RST_CORE BIT(26) 84 - #define ESP32S3_UART_RX_RST_CORE BIT(27) 85 - 86 - #define ESP32S3_UART_CLK_CONF_DEFAULT \ 87 - (ESP32S3_UART_RX_SCLK_EN | \ 88 - ESP32S3_UART_TX_SCLK_EN | \ 89 - ESP32S3_UART_SCLK_EN | \ 90 - FIELD_PREP(ESP32S3_UART_SCLK_SEL, XTAL_CLK)) 91 - 92 - struct esp32_port { 93 - struct uart_port port; 94 - struct clk *clk; 95 - }; 96 - 97 - struct esp32_uart_variant { 98 - u32 clkdiv_mask; 99 - u32 rxfifo_cnt_mask; 100 - u32 txfifo_cnt_mask; 101 - u32 txfifo_empty_thrhd_shift; 102 - u32 rx_flow_en; 103 - const char *type; 104 - bool has_clkconf; 105 - }; 106 - 107 - static const struct esp32_uart_variant esp32_variant = { 108 - .clkdiv_mask = ESP32_UART_CLKDIV, 109 - .rxfifo_cnt_mask = ESP32_UART_RXFIFO_CNT, 110 - .txfifo_cnt_mask = ESP32_UART_TXFIFO_CNT, 111 - .txfifo_empty_thrhd_shift = ESP32_UART_TXFIFO_EMPTY_THRHD_SHIFT, 112 - .rx_flow_en = ESP32_UART_RX_FLOW_EN, 113 - .type = "ESP32 UART", 114 - }; 115 - 116 - static const struct esp32_uart_variant esp32s3_variant = { 117 - .clkdiv_mask = ESP32S3_UART_CLKDIV, 118 - .rxfifo_cnt_mask = ESP32S3_UART_RXFIFO_CNT, 119 - .txfifo_cnt_mask = ESP32S3_UART_TXFIFO_CNT, 120 - .txfifo_empty_thrhd_shift = ESP32S3_UART_TXFIFO_EMPTY_THRHD_SHIFT, 121 - .rx_flow_en = ESP32S3_UART_RX_FLOW_EN, 122 - .type = "ESP32S3 UART", 123 - .has_clkconf = true, 124 - }; 125 - 126 - static const struct of_device_id esp32_uart_dt_ids[] = { 127 - { 128 - .compatible = "esp,esp32-uart", 129 - .data = &esp32_variant, 130 - }, { 131 - .compatible = "esp,esp32s3-uart", 132 - .data = &esp32s3_variant, 133 - }, { /* sentinel */ } 134 - }; 135 - MODULE_DEVICE_TABLE(of, esp32_uart_dt_ids); 136 - 137 - static struct esp32_port *esp32_uart_ports[UART_NR]; 138 - 139 - static const struct esp32_uart_variant *port_variant(struct uart_port *port) 140 - { 141 - return port->private_data; 142 - } 143 - 144 - static void esp32_uart_write(struct uart_port *port, unsigned long reg, u32 v) 145 - { 146 - writel(v, port->membase + reg); 147 - } 148 - 149 - static u32 esp32_uart_read(struct uart_port *port, unsigned long reg) 150 - { 151 - return readl(port->membase + reg); 152 - } 153 - 154 - static u32 esp32_uart_tx_fifo_cnt(struct uart_port *port) 155 - { 156 - u32 status = esp32_uart_read(port, UART_STATUS_REG); 157 - 158 - return (status & port_variant(port)->txfifo_cnt_mask) >> UART_TXFIFO_CNT_SHIFT; 159 - } 160 - 161 - static u32 esp32_uart_rx_fifo_cnt(struct uart_port *port) 162 - { 163 - u32 status = esp32_uart_read(port, UART_STATUS_REG); 164 - 165 - return (status & port_variant(port)->rxfifo_cnt_mask) >> UART_RXFIFO_CNT_SHIFT; 166 - } 167 - 168 - /* return TIOCSER_TEMT when transmitter is not busy */ 169 - static unsigned int esp32_uart_tx_empty(struct uart_port *port) 170 - { 171 - return esp32_uart_tx_fifo_cnt(port) ? 0 : TIOCSER_TEMT; 172 - } 173 - 174 - static void esp32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 175 - { 176 - u32 conf0 = esp32_uart_read(port, UART_CONF0_REG); 177 - 178 - conf0 &= ~(UART_LOOPBACK | 179 - UART_SW_RTS | UART_RTS_INV | 180 - UART_SW_DTR | UART_DTR_INV); 181 - 182 - if (mctrl & TIOCM_RTS) 183 - conf0 |= UART_SW_RTS; 184 - if (mctrl & TIOCM_DTR) 185 - conf0 |= UART_SW_DTR; 186 - if (mctrl & TIOCM_LOOP) 187 - conf0 |= UART_LOOPBACK; 188 - 189 - esp32_uart_write(port, UART_CONF0_REG, conf0); 190 - } 191 - 192 - static unsigned int esp32_uart_get_mctrl(struct uart_port *port) 193 - { 194 - u32 status = esp32_uart_read(port, UART_STATUS_REG); 195 - unsigned int ret = TIOCM_CAR; 196 - 197 - if (status & UART_DSRN) 198 - ret |= TIOCM_DSR; 199 - if (status & UART_CTSN) 200 - ret |= TIOCM_CTS; 201 - 202 - return ret; 203 - } 204 - 205 - static void esp32_uart_stop_tx(struct uart_port *port) 206 - { 207 - u32 int_ena; 208 - 209 - int_ena = esp32_uart_read(port, UART_INT_ENA_REG); 210 - int_ena &= ~UART_TXFIFO_EMPTY_INT; 211 - esp32_uart_write(port, UART_INT_ENA_REG, int_ena); 212 - } 213 - 214 - static void esp32_uart_rxint(struct uart_port *port) 215 - { 216 - struct tty_port *tty_port = &port->state->port; 217 - u32 rx_fifo_cnt = esp32_uart_rx_fifo_cnt(port); 218 - unsigned long flags; 219 - u32 i; 220 - 221 - if (!rx_fifo_cnt) 222 - return; 223 - 224 - spin_lock_irqsave(&port->lock, flags); 225 - 226 - for (i = 0; i < rx_fifo_cnt; ++i) { 227 - u32 rx = esp32_uart_read(port, UART_FIFO_REG); 228 - 229 - if (!rx && 230 - (esp32_uart_read(port, UART_INT_ST_REG) & UART_BRK_DET_INT)) { 231 - esp32_uart_write(port, UART_INT_CLR_REG, UART_BRK_DET_INT); 232 - ++port->icount.brk; 233 - uart_handle_break(port); 234 - } else { 235 - if (uart_handle_sysrq_char(port, (unsigned char)rx)) 236 - continue; 237 - tty_insert_flip_char(tty_port, rx, TTY_NORMAL); 238 - ++port->icount.rx; 239 - } 240 - } 241 - spin_unlock_irqrestore(&port->lock, flags); 242 - 243 - tty_flip_buffer_push(tty_port); 244 - } 245 - 246 - static void esp32_uart_put_char(struct uart_port *port, u8 c) 247 - { 248 - esp32_uart_write(port, UART_FIFO_REG, c); 249 - } 250 - 251 - static void esp32_uart_put_char_sync(struct uart_port *port, u8 c) 252 - { 253 - unsigned long timeout = jiffies + HZ; 254 - 255 - while (esp32_uart_tx_fifo_cnt(port) >= ESP32_UART_TX_FIFO_SIZE) { 256 - if (time_after(jiffies, timeout)) { 257 - dev_warn(port->dev, "timeout waiting for TX FIFO\n"); 258 - return; 259 - } 260 - cpu_relax(); 261 - } 262 - esp32_uart_put_char(port, c); 263 - } 264 - 265 - static void esp32_uart_transmit_buffer(struct uart_port *port) 266 - { 267 - u32 tx_fifo_used = esp32_uart_tx_fifo_cnt(port); 268 - unsigned int pending; 269 - u8 ch; 270 - 271 - if (tx_fifo_used >= ESP32_UART_TX_FIFO_SIZE) 272 - return; 273 - 274 - pending = uart_port_tx_limited(port, ch, 275 - ESP32_UART_TX_FIFO_SIZE - tx_fifo_used, 276 - true, esp32_uart_put_char(port, ch), 277 - ({})); 278 - if (pending) { 279 - u32 int_ena; 280 - 281 - int_ena = esp32_uart_read(port, UART_INT_ENA_REG); 282 - int_ena |= UART_TXFIFO_EMPTY_INT; 283 - esp32_uart_write(port, UART_INT_ENA_REG, int_ena); 284 - } 285 - } 286 - 287 - static void esp32_uart_txint(struct uart_port *port) 288 - { 289 - esp32_uart_transmit_buffer(port); 290 - } 291 - 292 - static irqreturn_t esp32_uart_int(int irq, void *dev_id) 293 - { 294 - struct uart_port *port = dev_id; 295 - u32 status; 296 - 297 - status = esp32_uart_read(port, UART_INT_ST_REG); 298 - 299 - if (status & (UART_RXFIFO_FULL_INT | UART_BRK_DET_INT)) 300 - esp32_uart_rxint(port); 301 - if (status & UART_TXFIFO_EMPTY_INT) 302 - esp32_uart_txint(port); 303 - 304 - esp32_uart_write(port, UART_INT_CLR_REG, status); 305 - 306 - return IRQ_RETVAL(status); 307 - } 308 - 309 - static void esp32_uart_start_tx(struct uart_port *port) 310 - { 311 - esp32_uart_transmit_buffer(port); 312 - } 313 - 314 - static void esp32_uart_stop_rx(struct uart_port *port) 315 - { 316 - u32 int_ena; 317 - 318 - int_ena = esp32_uart_read(port, UART_INT_ENA_REG); 319 - int_ena &= ~UART_RXFIFO_FULL_INT; 320 - esp32_uart_write(port, UART_INT_ENA_REG, int_ena); 321 - } 322 - 323 - static int esp32_uart_startup(struct uart_port *port) 324 - { 325 - int ret = 0; 326 - unsigned long flags; 327 - struct esp32_port *sport = container_of(port, struct esp32_port, port); 328 - 329 - ret = clk_prepare_enable(sport->clk); 330 - if (ret) 331 - return ret; 332 - 333 - ret = request_irq(port->irq, esp32_uart_int, 0, DRIVER_NAME, port); 334 - if (ret) { 335 - clk_disable_unprepare(sport->clk); 336 - return ret; 337 - } 338 - 339 - spin_lock_irqsave(&port->lock, flags); 340 - if (port_variant(port)->has_clkconf) 341 - esp32_uart_write(port, ESP32S3_UART_CLK_CONF_REG, 342 - ESP32S3_UART_CLK_CONF_DEFAULT); 343 - esp32_uart_write(port, UART_CONF1_REG, 344 - (1 << UART_RXFIFO_FULL_THRHD_SHIFT) | 345 - (1 << port_variant(port)->txfifo_empty_thrhd_shift)); 346 - esp32_uart_write(port, UART_INT_CLR_REG, UART_RXFIFO_FULL_INT | UART_BRK_DET_INT); 347 - esp32_uart_write(port, UART_INT_ENA_REG, UART_RXFIFO_FULL_INT | UART_BRK_DET_INT); 348 - spin_unlock_irqrestore(&port->lock, flags); 349 - 350 - return ret; 351 - } 352 - 353 - static void esp32_uart_shutdown(struct uart_port *port) 354 - { 355 - struct esp32_port *sport = container_of(port, struct esp32_port, port); 356 - 357 - esp32_uart_write(port, UART_INT_ENA_REG, 0); 358 - free_irq(port->irq, port); 359 - clk_disable_unprepare(sport->clk); 360 - } 361 - 362 - static bool esp32_uart_set_baud(struct uart_port *port, u32 baud) 363 - { 364 - u32 sclk = port->uartclk; 365 - u32 div = sclk / baud; 366 - 367 - if (port_variant(port)->has_clkconf) { 368 - u32 sclk_div = div / port_variant(port)->clkdiv_mask; 369 - 370 - if (div > port_variant(port)->clkdiv_mask) { 371 - sclk /= (sclk_div + 1); 372 - div = sclk / baud; 373 - } 374 - esp32_uart_write(port, ESP32S3_UART_CLK_CONF_REG, 375 - FIELD_PREP(ESP32S3_UART_SCLK_DIV_NUM, sclk_div) | 376 - ESP32S3_UART_CLK_CONF_DEFAULT); 377 - } 378 - 379 - if (div <= port_variant(port)->clkdiv_mask) { 380 - u32 frag = (sclk * 16) / baud - div * 16; 381 - 382 - esp32_uart_write(port, UART_CLKDIV_REG, 383 - div | FIELD_PREP(UART_CLKDIV_FRAG, frag)); 384 - return true; 385 - } 386 - 387 - return false; 388 - } 389 - 390 - static void esp32_uart_set_termios(struct uart_port *port, 391 - struct ktermios *termios, 392 - const struct ktermios *old) 393 - { 394 - unsigned long flags; 395 - u32 conf0, conf1; 396 - u32 baud; 397 - const u32 rx_flow_en = port_variant(port)->rx_flow_en; 398 - u32 max_div = port_variant(port)->clkdiv_mask; 399 - 400 - termios->c_cflag &= ~CMSPAR; 401 - 402 - if (port_variant(port)->has_clkconf) 403 - max_div *= FIELD_MAX(ESP32S3_UART_SCLK_DIV_NUM); 404 - 405 - baud = uart_get_baud_rate(port, termios, old, 406 - port->uartclk / max_div, 407 - port->uartclk / 16); 408 - 409 - spin_lock_irqsave(&port->lock, flags); 410 - 411 - conf0 = esp32_uart_read(port, UART_CONF0_REG); 412 - conf0 &= ~(UART_PARITY_EN | UART_PARITY | UART_BIT_NUM | UART_STOP_BIT_NUM); 413 - 414 - conf1 = esp32_uart_read(port, UART_CONF1_REG); 415 - conf1 &= ~rx_flow_en; 416 - 417 - if (termios->c_cflag & PARENB) { 418 - conf0 |= UART_PARITY_EN; 419 - if (termios->c_cflag & PARODD) 420 - conf0 |= UART_PARITY; 421 - } 422 - 423 - switch (termios->c_cflag & CSIZE) { 424 - case CS5: 425 - conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_5); 426 - break; 427 - case CS6: 428 - conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_6); 429 - break; 430 - case CS7: 431 - conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_7); 432 - break; 433 - case CS8: 434 - conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_8); 435 - break; 436 - } 437 - 438 - if (termios->c_cflag & CSTOPB) 439 - conf0 |= FIELD_PREP(UART_STOP_BIT_NUM, UART_STOP_BIT_NUM_2); 440 - else 441 - conf0 |= FIELD_PREP(UART_STOP_BIT_NUM, UART_STOP_BIT_NUM_1); 442 - 443 - if (termios->c_cflag & CRTSCTS) 444 - conf1 |= rx_flow_en; 445 - 446 - esp32_uart_write(port, UART_CONF0_REG, conf0); 447 - esp32_uart_write(port, UART_CONF1_REG, conf1); 448 - 449 - if (baud) { 450 - esp32_uart_set_baud(port, baud); 451 - uart_update_timeout(port, termios->c_cflag, baud); 452 - } else { 453 - if (esp32_uart_set_baud(port, 115200)) { 454 - baud = 115200; 455 - tty_termios_encode_baud_rate(termios, baud, baud); 456 - uart_update_timeout(port, termios->c_cflag, baud); 457 - } else { 458 - dev_warn(port->dev, 459 - "unable to set speed to %d baud or the default 115200\n", 460 - baud); 461 - } 462 - } 463 - spin_unlock_irqrestore(&port->lock, flags); 464 - } 465 - 466 - static const char *esp32_uart_type(struct uart_port *port) 467 - { 468 - return port_variant(port)->type; 469 - } 470 - 471 - /* configure/auto-configure the port */ 472 - static void esp32_uart_config_port(struct uart_port *port, int flags) 473 - { 474 - if (flags & UART_CONFIG_TYPE) 475 - port->type = PORT_GENERIC; 476 - } 477 - 478 - #ifdef CONFIG_CONSOLE_POLL 479 - static int esp32_uart_poll_init(struct uart_port *port) 480 - { 481 - struct esp32_port *sport = container_of(port, struct esp32_port, port); 482 - 483 - return clk_prepare_enable(sport->clk); 484 - } 485 - 486 - static void esp32_uart_poll_put_char(struct uart_port *port, unsigned char c) 487 - { 488 - esp32_uart_put_char_sync(port, c); 489 - } 490 - 491 - static int esp32_uart_poll_get_char(struct uart_port *port) 492 - { 493 - if (esp32_uart_rx_fifo_cnt(port)) 494 - return esp32_uart_read(port, UART_FIFO_REG); 495 - else 496 - return NO_POLL_CHAR; 497 - 498 - } 499 - #endif 500 - 501 - static const struct uart_ops esp32_uart_pops = { 502 - .tx_empty = esp32_uart_tx_empty, 503 - .set_mctrl = esp32_uart_set_mctrl, 504 - .get_mctrl = esp32_uart_get_mctrl, 505 - .stop_tx = esp32_uart_stop_tx, 506 - .start_tx = esp32_uart_start_tx, 507 - .stop_rx = esp32_uart_stop_rx, 508 - .startup = esp32_uart_startup, 509 - .shutdown = esp32_uart_shutdown, 510 - .set_termios = esp32_uart_set_termios, 511 - .type = esp32_uart_type, 512 - .config_port = esp32_uart_config_port, 513 - #ifdef CONFIG_CONSOLE_POLL 514 - .poll_init = esp32_uart_poll_init, 515 - .poll_put_char = esp32_uart_poll_put_char, 516 - .poll_get_char = esp32_uart_poll_get_char, 517 - #endif 518 - }; 519 - 520 - static void esp32_uart_console_putchar(struct uart_port *port, u8 c) 521 - { 522 - esp32_uart_put_char_sync(port, c); 523 - } 524 - 525 - static void esp32_uart_string_write(struct uart_port *port, const char *s, 526 - unsigned int count) 527 - { 528 - uart_console_write(port, s, count, esp32_uart_console_putchar); 529 - } 530 - 531 - static void 532 - esp32_uart_console_write(struct console *co, const char *s, unsigned int count) 533 - { 534 - struct esp32_port *sport = esp32_uart_ports[co->index]; 535 - struct uart_port *port = &sport->port; 536 - unsigned long flags; 537 - bool locked = true; 538 - 539 - if (port->sysrq) 540 - locked = false; 541 - else if (oops_in_progress) 542 - locked = spin_trylock_irqsave(&port->lock, flags); 543 - else 544 - spin_lock_irqsave(&port->lock, flags); 545 - 546 - esp32_uart_string_write(port, s, count); 547 - 548 - if (locked) 549 - spin_unlock_irqrestore(&port->lock, flags); 550 - } 551 - 552 - static int __init esp32_uart_console_setup(struct console *co, char *options) 553 - { 554 - struct esp32_port *sport; 555 - int baud = 115200; 556 - int bits = 8; 557 - int parity = 'n'; 558 - int flow = 'n'; 559 - int ret; 560 - 561 - /* 562 - * check whether an invalid uart number has been specified, and 563 - * if so, search for the first available port that does have 564 - * console support. 565 - */ 566 - if (co->index == -1 || co->index >= ARRAY_SIZE(esp32_uart_ports)) 567 - co->index = 0; 568 - 569 - sport = esp32_uart_ports[co->index]; 570 - if (!sport) 571 - return -ENODEV; 572 - 573 - ret = clk_prepare_enable(sport->clk); 574 - if (ret) 575 - return ret; 576 - 577 - if (options) 578 - uart_parse_options(options, &baud, &parity, &bits, &flow); 579 - 580 - return uart_set_options(&sport->port, co, baud, parity, bits, flow); 581 - } 582 - 583 - static int esp32_uart_console_exit(struct console *co) 584 - { 585 - struct esp32_port *sport = esp32_uart_ports[co->index]; 586 - 587 - clk_disable_unprepare(sport->clk); 588 - return 0; 589 - } 590 - 591 - static struct uart_driver esp32_uart_reg; 592 - static struct console esp32_uart_console = { 593 - .name = DEV_NAME, 594 - .write = esp32_uart_console_write, 595 - .device = uart_console_device, 596 - .setup = esp32_uart_console_setup, 597 - .exit = esp32_uart_console_exit, 598 - .flags = CON_PRINTBUFFER, 599 - .index = -1, 600 - .data = &esp32_uart_reg, 601 - }; 602 - 603 - static void esp32_uart_earlycon_putchar(struct uart_port *port, u8 c) 604 - { 605 - esp32_uart_put_char_sync(port, c); 606 - } 607 - 608 - static void esp32_uart_earlycon_write(struct console *con, const char *s, 609 - unsigned int n) 610 - { 611 - struct earlycon_device *dev = con->data; 612 - 613 - uart_console_write(&dev->port, s, n, esp32_uart_earlycon_putchar); 614 - } 615 - 616 - #ifdef CONFIG_CONSOLE_POLL 617 - static int esp32_uart_earlycon_read(struct console *con, char *s, unsigned int n) 618 - { 619 - struct earlycon_device *dev = con->data; 620 - unsigned int num_read = 0; 621 - 622 - while (num_read < n) { 623 - int c = esp32_uart_poll_get_char(&dev->port); 624 - 625 - if (c == NO_POLL_CHAR) 626 - break; 627 - s[num_read++] = c; 628 - } 629 - return num_read; 630 - } 631 - #endif 632 - 633 - static int __init esp32xx_uart_early_console_setup(struct earlycon_device *device, 634 - const char *options) 635 - { 636 - if (!device->port.membase) 637 - return -ENODEV; 638 - 639 - device->con->write = esp32_uart_earlycon_write; 640 - #ifdef CONFIG_CONSOLE_POLL 641 - device->con->read = esp32_uart_earlycon_read; 642 - #endif 643 - if (device->port.uartclk != BASE_BAUD * 16) 644 - esp32_uart_set_baud(&device->port, device->baud); 645 - 646 - return 0; 647 - } 648 - 649 - static int __init esp32_uart_early_console_setup(struct earlycon_device *device, 650 - const char *options) 651 - { 652 - device->port.private_data = (void *)&esp32_variant; 653 - 654 - return esp32xx_uart_early_console_setup(device, options); 655 - } 656 - 657 - OF_EARLYCON_DECLARE(esp32uart, "esp,esp32-uart", 658 - esp32_uart_early_console_setup); 659 - 660 - static int __init esp32s3_uart_early_console_setup(struct earlycon_device *device, 661 - const char *options) 662 - { 663 - device->port.private_data = (void *)&esp32s3_variant; 664 - 665 - return esp32xx_uart_early_console_setup(device, options); 666 - } 667 - 668 - OF_EARLYCON_DECLARE(esp32s3uart, "esp,esp32s3-uart", 669 - esp32s3_uart_early_console_setup); 670 - 671 - static struct uart_driver esp32_uart_reg = { 672 - .owner = THIS_MODULE, 673 - .driver_name = DRIVER_NAME, 674 - .dev_name = DEV_NAME, 675 - .nr = ARRAY_SIZE(esp32_uart_ports), 676 - .cons = &esp32_uart_console, 677 - }; 678 - 679 - static int esp32_uart_probe(struct platform_device *pdev) 680 - { 681 - struct device_node *np = pdev->dev.of_node; 682 - struct uart_port *port; 683 - struct esp32_port *sport; 684 - struct resource *res; 685 - int ret; 686 - 687 - sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 688 - if (!sport) 689 - return -ENOMEM; 690 - 691 - port = &sport->port; 692 - 693 - ret = of_alias_get_id(np, "serial"); 694 - if (ret < 0) { 695 - dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 696 - return ret; 697 - } 698 - if (ret >= UART_NR) { 699 - dev_err(&pdev->dev, "driver limited to %d serial ports\n", UART_NR); 700 - return -ENOMEM; 701 - } 702 - 703 - port->line = ret; 704 - 705 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 706 - if (!res) 707 - return -ENODEV; 708 - 709 - port->mapbase = res->start; 710 - port->membase = devm_ioremap_resource(&pdev->dev, res); 711 - if (IS_ERR(port->membase)) 712 - return PTR_ERR(port->membase); 713 - 714 - sport->clk = devm_clk_get(&pdev->dev, NULL); 715 - if (IS_ERR(sport->clk)) 716 - return PTR_ERR(sport->clk); 717 - 718 - port->uartclk = clk_get_rate(sport->clk); 719 - port->dev = &pdev->dev; 720 - port->type = PORT_GENERIC; 721 - port->iotype = UPIO_MEM; 722 - port->irq = platform_get_irq(pdev, 0); 723 - port->ops = &esp32_uart_pops; 724 - port->flags = UPF_BOOT_AUTOCONF; 725 - port->has_sysrq = 1; 726 - port->fifosize = ESP32_UART_TX_FIFO_SIZE; 727 - port->private_data = (void *)device_get_match_data(&pdev->dev); 728 - 729 - esp32_uart_ports[port->line] = sport; 730 - 731 - platform_set_drvdata(pdev, port); 732 - 733 - return uart_add_one_port(&esp32_uart_reg, port); 734 - } 735 - 736 - static void esp32_uart_remove(struct platform_device *pdev) 737 - { 738 - struct uart_port *port = platform_get_drvdata(pdev); 739 - 740 - uart_remove_one_port(&esp32_uart_reg, port); 741 - } 742 - 743 - 744 - static struct platform_driver esp32_uart_driver = { 745 - .probe = esp32_uart_probe, 746 - .remove = esp32_uart_remove, 747 - .driver = { 748 - .name = DRIVER_NAME, 749 - .of_match_table = esp32_uart_dt_ids, 750 - }, 751 - }; 752 - 753 - static int __init esp32_uart_init(void) 754 - { 755 - int ret; 756 - 757 - ret = uart_register_driver(&esp32_uart_reg); 758 - if (ret) 759 - return ret; 760 - 761 - ret = platform_driver_register(&esp32_uart_driver); 762 - if (ret) 763 - uart_unregister_driver(&esp32_uart_reg); 764 - 765 - return ret; 766 - } 767 - 768 - static void __exit esp32_uart_exit(void) 769 - { 770 - platform_driver_unregister(&esp32_uart_driver); 771 - uart_unregister_driver(&esp32_uart_reg); 772 - } 773 - 774 - module_init(esp32_uart_init); 775 - module_exit(esp32_uart_exit); 776 - 777 - MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>"); 778 - MODULE_DESCRIPTION("Espressif ESP32 UART support"); 779 - MODULE_LICENSE("GPL");

+4 -3

drivers/tty/serial/imx.c

··· 1442 1442 1443 1443 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 1444 1444 1445 - /* set UCR1 */ 1445 + /* set UCR1 except TXDMAEN which would be enabled in imx_uart_dma_tx */ 1446 1446 ucr1 = imx_uart_readl(sport, UCR1); 1447 - ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 1447 + ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 1448 1448 imx_uart_writel(sport, ucr1, UCR1); 1449 1449 1450 1450 sport->dma_is_enabled = 1; ··· 1567 1567 imx_uart_enable_ms(&sport->port); 1568 1568 1569 1569 if (dma_is_inited) { 1570 - imx_uart_enable_dma(sport); 1570 + /* Note: enable dma request after transfer start! */ 1571 1571 imx_uart_start_rx_dma(sport); 1572 + imx_uart_enable_dma(sport); 1572 1573 } else { 1573 1574 ucr1 = imx_uart_readl(sport, UCR1); 1574 1575 ucr1 |= UCR1_RRDYEN;

+2 -2

drivers/tty/serial/ip22zilog.c

··· 1015 1015 1016 1016 static struct uart_driver ip22zilog_reg = { 1017 1017 .owner = THIS_MODULE, 1018 - .driver_name = "serial", 1018 + .driver_name = "serial_ip22zilog", 1019 1019 .dev_name = "ttyS", 1020 1020 .major = TTY_MAJOR, 1021 1021 .minor = 64, ··· 1025 1025 #endif 1026 1026 }; 1027 1027 1028 - static void __init ip22zilog_prepare(struct uart_ip22zilog_port *up) 1028 + static void ip22zilog_prepare(struct uart_ip22zilog_port *up) 1029 1029 { 1030 1030 unsigned char sysrq_on = IS_ENABLED(CONFIG_SERIAL_IP22_ZILOG_CONSOLE); 1031 1031 int brg;

+2 -1

drivers/tty/serial/mxs-auart.c

··· 1318 1318 s = auart_port[co->index]; 1319 1319 port = &s->port; 1320 1320 1321 - clk_enable(s->clk); 1321 + if (clk_enable(s->clk)) 1322 + return; 1322 1323 1323 1324 /* First save the CR then disable the interrupts */ 1324 1325 old_ctrl2 = mxs_read(s, REG_CTRL2);

+16 -5

drivers/tty/serial/qcom_geni_serial.c

··· 146 146 int wakeup_irq; 147 147 bool rx_tx_swap; 148 148 bool cts_rts_swap; 149 + bool manual_flow; 149 150 150 151 struct qcom_geni_private_data private_data; 151 152 const struct qcom_geni_device_data *dev_data; ··· 251 250 if (mctrl & TIOCM_LOOP) 252 251 port->loopback = RX_TX_CTS_RTS_SORTED; 253 252 254 - if (!(mctrl & TIOCM_RTS) && !uport->suspended) 253 + if (port->manual_flow && !(mctrl & TIOCM_RTS) && !uport->suspended) 255 254 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; 256 255 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); 257 256 } ··· 1282 1281 return -EINVAL; 1283 1282 } 1284 1283 1285 - dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n, clk_idx = %u\n", 1284 + dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u, clk_idx = %u\n", 1286 1285 baud * sampling_rate, clk_rate, clk_div, clk_idx); 1287 1286 1288 1287 uport->uartclk = clk_rate; ··· 1402 1401 else 1403 1402 stop_bit_len = TX_STOP_BIT_LEN_1; 1404 1403 1405 - /* flow control, clear the CTS_MASK bit if using flow control. */ 1406 - if (termios->c_cflag & CRTSCTS) 1404 + /* Configure flow control based on CRTSCTS flag. 1405 + * When CRTSCTS is set, use HW/auto flow control mode, where HW 1406 + * controls the RTS/CTS pin based FIFO state. 1407 + * When CRTSCTS is clear, the CTS pin value is ignored for TX 1408 + * path and RTS pin can be set/cleared using registers, for RX 1409 + * path. 1410 + */ 1411 + 1412 + if (termios->c_cflag & CRTSCTS) { 1407 1413 tx_trans_cfg &= ~UART_CTS_MASK; 1408 - else 1414 + port->manual_flow = false; 1415 + } else { 1409 1416 tx_trans_cfg |= UART_CTS_MASK; 1417 + port->manual_flow = true; 1418 + } 1410 1419 1411 1420 if (baud) { 1412 1421 uart_update_timeout(uport, termios->c_cflag, baud);

+13

drivers/tty/serial/rsci.c

··· 695 695 .params = &rsci_rzg3e_port_params, 696 696 }; 697 697 698 + struct sci_of_data of_rsci_rzg3l_data = { 699 + .type = RSCI_PORT_SCIF32_SINGLE_TCLK, 700 + .ops = &rsci_port_ops, 701 + .uart_ops = &rsci_uart_ops, 702 + .params = &rsci_rzg3e_port_params, 703 + }; 704 + 698 705 struct sci_of_data of_rsci_rzt2h_data = { 699 706 .type = RSCI_PORT_SCIF16, 700 707 .ops = &rsci_port_ops, ··· 710 703 }; 711 704 712 705 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 706 + static int __init rsci_rzg3l_early_console_setup(struct earlycon_device *device, 707 + const char *opt) 708 + { 709 + return scix_early_console_setup(device, &of_rsci_rzg3l_data); 710 + } 713 711 714 712 static int __init rsci_rzg3e_early_console_setup(struct earlycon_device *device, 715 713 const char *opt) ··· 728 716 return scix_early_console_setup(device, &of_rsci_rzt2h_data); 729 717 } 730 718 719 + OF_EARLYCON_DECLARE(rsci, "renesas,r9a08g046-rsci", rsci_rzg3l_early_console_setup); 731 720 OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rsci", rsci_rzg3e_early_console_setup); 732 721 OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_rzt2h_early_console_setup); 733 722

+1

drivers/tty/serial/rsci.h

··· 6 6 #include "sh-sci-common.h" 7 7 8 8 extern struct sci_of_data of_rsci_rzg3e_data; 9 + extern struct sci_of_data of_rsci_rzg3l_data; 9 10 extern struct sci_of_data of_rsci_rzt2h_data; 10 11 11 12 #endif /* __RSCI_H__ */

+2 -8

drivers/tty/serial/samsung_tty.c

··· 1562 1562 ulcon |= S3C2410_LCON_PNONE; 1563 1563 } 1564 1564 1565 - uart_port_lock_irqsave(port, &flags); 1566 - 1567 1565 dev_dbg(port->dev, 1568 1566 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n", 1569 1567 ulcon, quot, udivslot); 1568 + 1569 + uart_port_lock_irqsave(port, &flags); 1570 1570 1571 1571 wr_regl(port, S3C2410_ULCON, ulcon); 1572 1572 wr_regl(port, S3C2410_UBRDIV, quot); ··· 1586 1586 1587 1587 if (ourport->info->has_divslot) 1588 1588 wr_regl(port, S3C2443_DIVSLOT, udivslot); 1589 - 1590 - dev_dbg(port->dev, 1591 - "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n", 1592 - rd_regl(port, S3C2410_ULCON), 1593 - rd_regl(port, S3C2410_UCON), 1594 - rd_regl(port, S3C2410_UFCON)); 1595 1589 1596 1590 /* 1597 1591 * Update the per-port timeout.

+1

drivers/tty/serial/sh-sci-common.h

··· 9 9 enum SCI_PORT_TYPE { 10 10 RSCI_PORT_SCIF16 = BIT(7) | 0, 11 11 RSCI_PORT_SCIF32 = BIT(7) | 1, 12 + RSCI_PORT_SCIF32_SINGLE_TCLK = BIT(7) | 2, 12 13 }; 13 14 14 15 enum SCI_CLKS {

+11 -3

drivers/tty/serial/sh-sci.c

··· 1184 1184 1185 1185 static bool sci_is_rsci_type(u8 type) 1186 1186 { 1187 - return (type == RSCI_PORT_SCIF16 || type == RSCI_PORT_SCIF32); 1187 + return (type == RSCI_PORT_SCIF16 || type == RSCI_PORT_SCIF32 || 1188 + type == RSCI_PORT_SCIF32_SINGLE_TCLK); 1188 1189 } 1189 1190 1190 1191 static int sci_handle_fifo_overrun(struct uart_port *port) ··· 3182 3181 3183 3182 if (sci_port->type == PORT_HSCIF) { 3184 3183 clk_names[SCI_SCK] = "hsck"; 3185 - } else if (sci_port->type == RSCI_PORT_SCIF16) { 3184 + } else if (sci_port->type == RSCI_PORT_SCIF16 || 3185 + sci_port->type == RSCI_PORT_SCIF32_SINGLE_TCLK) { 3186 3186 clk_names[SCI_FCK] = "operation"; 3187 3187 clk_names[SCI_BRG_INT] = "bus"; 3188 3188 } else if (sci_port->type == RSCI_PORT_SCIF32) { ··· 3198 3196 if (IS_ERR(clk)) 3199 3197 return PTR_ERR(clk); 3200 3198 3201 - if (!clk && sci_port->type == RSCI_PORT_SCIF16 && 3199 + if (!clk && (sci_port->type == RSCI_PORT_SCIF16 || 3200 + sci_port->type == RSCI_PORT_SCIF32_SINGLE_TCLK) && 3202 3201 (i == SCI_FCK || i == SCI_BRG_INT)) 3203 3202 return dev_err_probe(dev, -ENODEV, "failed to get %s\n", name); 3204 3203 ··· 3333 3330 break; 3334 3331 case PORT_SCIFA: 3335 3332 case RSCI_PORT_SCIF32: 3333 + case RSCI_PORT_SCIF32_SINGLE_TCLK: 3336 3334 sci_port->rx_trigger = 32; 3337 3335 break; 3338 3336 case PORT_SCIF: ··· 3667 3663 .data = &of_sci_scif_rzv2h, 3668 3664 }, 3669 3665 #ifdef CONFIG_SERIAL_RSCI 3666 + { 3667 + .compatible = "renesas,r9a08g046-rsci", 3668 + .data = &of_rsci_rzg3l_data, 3669 + }, 3670 3670 { 3671 3671 .compatible = "renesas,r9a09g047-rsci", 3672 3672 .data = &of_rsci_rzg3e_data,

-1

drivers/tty/serial/xilinx_uartps.c

··· 22 22 #include <linux/of.h> 23 23 #include <linux/module.h> 24 24 #include <linux/pm_runtime.h> 25 - #include <linux/gpio.h> 26 25 #include <linux/gpio/consumer.h> 27 26 #include <linux/delay.h> 28 27 #include <linux/reset.h>

+1 -1

drivers/tty/serial/zs.c

··· 1252 1252 1253 1253 static struct uart_driver zs_reg = { 1254 1254 .owner = THIS_MODULE, 1255 - .driver_name = "serial", 1255 + .driver_name = "serial_zs", 1256 1256 .dev_name = "ttyS", 1257 1257 .major = TTY_MAJOR, 1258 1258 .minor = 64,

+11 -4

drivers/tty/tty_buffer.c

··· 59 59 } 60 60 EXPORT_SYMBOL_GPL(tty_buffer_lock_exclusive); 61 61 62 + static bool tty_buffer_queue_work(struct tty_bufhead *buf) 63 + { 64 + struct workqueue_struct *flip_wq = READ_ONCE(buf->flip_wq); 65 + 66 + return queue_work(flip_wq ?: system_dfl_wq, &buf->work); 67 + } 68 + 62 69 /** 63 70 * tty_buffer_unlock_exclusive - release exclusive access 64 71 * @port: tty port owning the flip buffer ··· 83 76 mutex_unlock(&buf->lock); 84 77 85 78 if (restart) 86 - queue_work(system_dfl_wq, &buf->work); 79 + tty_buffer_queue_work(buf); 87 80 } 88 81 EXPORT_SYMBOL_GPL(tty_buffer_unlock_exclusive); 89 82 ··· 537 530 struct tty_bufhead *buf = &port->buf; 538 531 539 532 tty_flip_buffer_commit(buf->tail); 540 - queue_work(system_dfl_wq, &buf->work); 533 + tty_buffer_queue_work(buf); 541 534 } 542 535 EXPORT_SYMBOL(tty_flip_buffer_push); 543 536 ··· 567 560 tty_flip_buffer_commit(buf->tail); 568 561 spin_unlock_irqrestore(&port->lock, flags); 569 562 570 - queue_work(system_dfl_wq, &buf->work); 563 + tty_buffer_queue_work(buf); 571 564 572 565 return size; 573 566 } ··· 620 613 621 614 bool tty_buffer_restart_work(struct tty_port *port) 622 615 { 623 - return queue_work(system_dfl_wq, &port->buf.work); 616 + return tty_buffer_queue_work(&port->buf); 624 617 } 625 618 626 619 bool tty_buffer_cancel_work(struct tty_port *port)

+24 -1

drivers/tty/tty_io.c

··· 3443 3443 if (error < 0) 3444 3444 goto err; 3445 3445 3446 + /* 3447 + * Drivers that do not define driver_name are potentially in-memory devices 3448 + * like vty, which generally do not require special workqueue settings. 3449 + */ 3450 + if (!(driver->flags & TTY_DRIVER_NO_WORKQUEUE) && driver->driver_name) { 3451 + driver->flip_wq = alloc_workqueue("%s-%s", WQ_UNBOUND | WQ_SYSFS, 3452 + 0, driver->name, driver->driver_name); 3453 + if (!driver->flip_wq) { 3454 + error = -ENOMEM; 3455 + goto err_unreg_char; 3456 + } 3457 + for (i = 0; i < driver->num; i++) { 3458 + if (driver->ports[i]) 3459 + tty_port_link_driver_wq(driver->ports[i], driver); 3460 + } 3461 + } 3462 + 3446 3463 if (driver->flags & TTY_DRIVER_DYNAMIC_ALLOC) { 3447 3464 error = tty_cdev_add(driver, dev, 0, driver->num); 3448 3465 if (error) 3449 - goto err_unreg_char; 3466 + goto err_destroy_wq; 3450 3467 } 3451 3468 3452 3469 scoped_guard(mutex, &tty_mutex) ··· 3489 3472 scoped_guard(mutex, &tty_mutex) 3490 3473 list_del(&driver->tty_drivers); 3491 3474 3475 + err_destroy_wq: 3476 + if (driver->flip_wq) 3477 + destroy_workqueue(driver->flip_wq); 3478 + 3492 3479 err_unreg_char: 3493 3480 unregister_chrdev_region(dev, driver->num); 3494 3481 err: ··· 3512 3491 driver->num); 3513 3492 scoped_guard(mutex, &tty_mutex) 3514 3493 list_del(&driver->tty_drivers); 3494 + if (driver->flip_wq) 3495 + destroy_workqueue(driver->flip_wq); 3515 3496 } 3516 3497 EXPORT_SYMBOL(tty_unregister_driver); 3517 3498

+8 -8

drivers/tty/tty_ldisc.c

··· 44 44 45 45 static DEFINE_RAW_SPINLOCK(tty_ldiscs_lock); 46 46 /* Line disc dispatch table */ 47 - static struct tty_ldisc_ops *tty_ldiscs[NR_LDISCS]; 47 + static const struct tty_ldisc_ops *tty_ldiscs[NR_LDISCS]; 48 48 49 49 /** 50 50 * tty_register_ldisc - install a line discipline ··· 55 55 * 56 56 * Locking: takes %tty_ldiscs_lock to guard against ldisc races 57 57 */ 58 - int tty_register_ldisc(struct tty_ldisc_ops *new_ldisc) 58 + int tty_register_ldisc(const struct tty_ldisc_ops *new_ldisc) 59 59 { 60 60 unsigned long flags; 61 61 ··· 80 80 * Locking: takes %tty_ldiscs_lock to guard against ldisc races 81 81 */ 82 82 83 - void tty_unregister_ldisc(struct tty_ldisc_ops *ldisc) 83 + void tty_unregister_ldisc(const struct tty_ldisc_ops *ldisc) 84 84 { 85 85 unsigned long flags; 86 86 ··· 90 90 } 91 91 EXPORT_SYMBOL(tty_unregister_ldisc); 92 92 93 - static struct tty_ldisc_ops *get_ldops(int disc) 93 + static const struct tty_ldisc_ops *get_ldops(int disc) 94 94 { 95 95 unsigned long flags; 96 - struct tty_ldisc_ops *ldops, *ret; 96 + const struct tty_ldisc_ops *ldops, *ret; 97 97 98 98 raw_spin_lock_irqsave(&tty_ldiscs_lock, flags); 99 99 ret = ERR_PTR(-EINVAL); ··· 107 107 return ret; 108 108 } 109 109 110 - static void put_ldops(struct tty_ldisc_ops *ldops) 110 + static void put_ldops(const struct tty_ldisc_ops *ldops) 111 111 { 112 112 unsigned long flags; 113 113 ··· 139 139 static struct tty_ldisc *tty_ldisc_get(struct tty_struct *tty, int disc) 140 140 { 141 141 struct tty_ldisc *ld; 142 - struct tty_ldisc_ops *ldops; 142 + const struct tty_ldisc_ops *ldops; 143 143 144 144 if (disc < N_TTY || disc >= NR_LDISCS) 145 145 return ERR_PTR(-EINVAL); ··· 202 202 static int tty_ldiscs_seq_show(struct seq_file *m, void *v) 203 203 { 204 204 int i = *(loff_t *)v; 205 - struct tty_ldisc_ops *ldops; 205 + const struct tty_ldisc_ops *ldops; 206 206 207 207 ldops = get_ldops(i); 208 208 if (IS_ERR(ldops))

+22

drivers/tty/tty_port.c

··· 100 100 EXPORT_SYMBOL(tty_port_init); 101 101 102 102 /** 103 + * tty_port_link_wq - link tty_port and flip workqueue 104 + * @port: tty_port of the device 105 + * @flip_wq: workqueue to queue flip buffer work on 106 + * 107 + * Whenever %TTY_DRIVER_NO_WORKQUEUE is used, every tty_port can be linked to 108 + * a workqueue manually by this function. 109 + * tty_port will use system_dfl_wq when buf.flip_wq is NULL. 110 + * 111 + * Note that tty_port API will NOT destroy the workqueue. 112 + */ 113 + void tty_port_link_wq(struct tty_port *port, struct workqueue_struct *flip_wq) 114 + { 115 + port->buf.flip_wq = flip_wq; 116 + } 117 + EXPORT_SYMBOL_GPL(tty_port_link_wq); 118 + 119 + /** 103 120 * tty_port_link_device - link tty and tty_port 104 121 * @port: tty_port of the device 105 122 * @driver: tty_driver for this device ··· 174 157 const struct attribute_group **attr_grp) 175 158 { 176 159 tty_port_link_device(port, driver, index); 160 + tty_port_link_driver_wq(port, driver); 177 161 return tty_register_device_attr(driver, index, device, drvdata, 178 162 attr_grp); 179 163 } ··· 201 183 struct device *dev; 202 184 203 185 tty_port_link_device(port, driver, index); 186 + tty_port_link_driver_wq(port, driver); 204 187 205 188 dev = serdev_tty_port_register(port, host, parent, driver, index); 206 189 if (PTR_ERR(dev) != -ENODEV) { ··· 229 210 { 230 211 int ret; 231 212 213 + WRITE_ONCE(port->buf.flip_wq, NULL); 232 214 ret = serdev_tty_port_unregister(port); 233 215 if (ret == 0) 234 216 return; ··· 277 257 { 278 258 tty_buffer_cancel_work(port); 279 259 tty_buffer_free_all(port); 260 + WRITE_ONCE(port->buf.flip_wq, NULL); 280 261 } 281 262 EXPORT_SYMBOL(tty_port_destroy); 282 263 ··· 724 703 struct tty_struct *tty) 725 704 { 726 705 tty->port = port; 706 + tty_port_link_driver_wq(port, driver); 727 707 return tty_standard_install(driver, tty); 728 708 } 729 709 EXPORT_SYMBOL_GPL(tty_port_install);

+74 -6

drivers/tty/vt/keyboard.c

··· 74 74 k_self, k_fn, k_spec, k_pad,\ 75 75 k_dead, k_cons, k_cur, k_shift,\ 76 76 k_meta, k_ascii, k_lock, k_lowercase,\ 77 - k_slock, k_dead2, k_brl, k_ignore 77 + k_slock, k_dead2, k_brl, k_csi 78 78 79 79 typedef void (k_handler_fn)(struct vc_data *vc, unsigned char value, 80 80 char up_flag); ··· 127 127 [ KT_SLOCK ] = NR_LOCK - 1, 128 128 [ KT_DEAD2 ] = 255, 129 129 [ KT_BRL ] = NR_BRL - 1, 130 + [ KT_CSI ] = 99, 130 131 }; 131 132 132 133 static const int NR_TYPES = ARRAY_SIZE(max_vals); ··· 645 644 /* 646 645 * Special key handlers 647 646 */ 648 - static void k_ignore(struct vc_data *vc, unsigned char value, char up_flag) 649 - { 650 - } 651 - 652 647 static void k_spec(struct vc_data *vc, unsigned char value, char up_flag) 653 648 { 654 649 if (up_flag) ··· 762 765 pr_err("k_fn called with value=%d\n", value); 763 766 } 764 767 768 + /* 769 + * Compute xterm-style modifier parameter for CSI sequences. 770 + * Returns 1 + (shift ? 1 : 0) + (alt ? 2 : 0) + (ctrl ? 4 : 0) 771 + */ 772 + static int csi_modifier_param(void) 773 + { 774 + int mod = 1; 775 + 776 + if (shift_state & (BIT(KG_SHIFT) | BIT(KG_SHIFTL) | BIT(KG_SHIFTR))) 777 + mod += 1; 778 + if (shift_state & (BIT(KG_ALT) | BIT(KG_ALTGR))) 779 + mod += 2; 780 + if (shift_state & (BIT(KG_CTRL) | BIT(KG_CTRLL) | BIT(KG_CTRLR))) 781 + mod += 4; 782 + return mod; 783 + } 784 + 765 785 static void k_cur(struct vc_data *vc, unsigned char value, char up_flag) 766 786 { 767 787 static const char cur_chars[] = "BDCA"; 788 + int mod; 768 789 769 790 if (up_flag) 770 791 return; 771 792 772 - applkey(vc, cur_chars[value], vc_kbd_mode(kbd, VC_CKMODE)); 793 + mod = csi_modifier_param(); 794 + if (mod > 1) { 795 + char buf[] = { 0x1b, '[', '1', ';', '0' + mod, cur_chars[value], 0x00 }; 796 + 797 + puts_queue(vc, buf); 798 + } else { 799 + applkey(vc, cur_chars[value], vc_kbd_mode(kbd, VC_CKMODE)); 800 + } 773 801 } 774 802 775 803 static void k_pad(struct vc_data *vc, unsigned char value, char up_flag) ··· 1024 1002 } 1025 1003 pressed &= ~BIT(value - 1); 1026 1004 } 1005 + } 1006 + 1007 + /* 1008 + * Handle KT_CSI keysym type: generate CSI tilde sequences with modifier 1009 + * support. The value encodes the CSI parameter number, producing sequences 1010 + * like ESC [ <value> ~ or ESC [ <value> ; <mod> ~ when modifiers are held. 1011 + */ 1012 + static void k_csi(struct vc_data *vc, unsigned char value, char up_flag) 1013 + { 1014 + char buf[10]; 1015 + int i = 0; 1016 + int mod; 1017 + 1018 + if (up_flag) 1019 + return; 1020 + 1021 + mod = csi_modifier_param(); 1022 + 1023 + buf[i++] = 0x1b; 1024 + buf[i++] = '['; 1025 + if (value >= 10) 1026 + buf[i++] = '0' + value / 10; 1027 + buf[i++] = '0' + value % 10; 1028 + if (mod > 1) { 1029 + buf[i++] = ';'; 1030 + buf[i++] = '0' + mod; 1031 + } 1032 + buf[i++] = '~'; 1033 + buf[i] = 0x00; 1034 + 1035 + puts_queue(vc, buf); 1027 1036 } 1028 1037 1029 1038 #if IS_ENABLED(CONFIG_INPUT_LEDS) && IS_ENABLED(CONFIG_LEDS_TRIGGERS) ··· 1497 1444 param.shift = shift_final = (shift_state | kbd->slockstate) ^ kbd->lockstate; 1498 1445 param.ledstate = kbd->ledflagstate; 1499 1446 key_map = key_maps[shift_final]; 1447 + 1448 + /* 1449 + * Fall back to the plain map if modifiers are active, the modifier- 1450 + * specific map is missing or has no entry, and the plain map has a 1451 + * modifier-aware key type (KT_CUR or KT_CSI). These handlers encode 1452 + * the modifier state into the emitted escape sequence. 1453 + */ 1454 + if (shift_final && keycode < NR_KEYS && 1455 + (!key_map || key_map[keycode] == K_HOLE) && key_maps[0]) { 1456 + unsigned short plain = key_maps[0][keycode]; 1457 + unsigned char type = KTYP(plain); 1458 + 1459 + if (type >= 0xf0 && (type - 0xf0 == KT_CUR || type - 0xf0 == KT_CSI)) 1460 + key_map = key_maps[0]; 1461 + } 1500 1462 1501 1463 rc = atomic_notifier_call_chain(&keyboard_notifier_list, 1502 1464 KBD_KEYCODE, &param);

+45 -3

drivers/tty/vt/vt.c

··· 1680 1680 1681 1681 /* 1682 1682 * ITU T.416 Higher colour modes. They break the usual properties of SGR codes 1683 - * and thus need to be detected and ignored by hand. That standard also 1684 - * wants : rather than ; as separators but sequences containing : are currently 1685 - * completely ignored by the parser. 1683 + * and thus need to be detected and ignored by hand. 1686 1684 * 1687 1685 * Subcommands 3 (CMY) and 4 (CMYK) are so insane there's no point in 1688 1686 * supporting them. ··· 1737 1739 CSI_m_BG_COLOR_END = 47, 1738 1740 CSI_m_BG_COLOR = 48, 1739 1741 CSI_m_DEFAULT_BG_COLOR = 49, 1742 + CSI_m_UNDERLINE_COLOR = 58, 1740 1743 CSI_m_BRIGHT_FG_COLOR_BEG = 90, 1741 1744 CSI_m_BRIGHT_FG_COLOR_END = 97, 1742 1745 CSI_m_BRIGHT_FG_COLOR_OFF = CSI_m_BRIGHT_FG_COLOR_BEG - CSI_m_FG_COLOR_BEG, ··· 2217 2218 * @ESesc: ESC parsed 2218 2219 * @ESsquare: CSI parsed -- modifiers/parameters/ctrl chars expected 2219 2220 * @ESgetpars: CSI parsed -- parameters/ctrl chars expected 2221 + * @ESgetsubpars: CSI m parsed -- subparameters expected 2220 2222 * @ESfunckey: CSI [ parsed 2221 2223 * @EShash: ESC # parsed 2222 2224 * @ESsetG0: ESC ( parsed ··· 2238 2238 ESesc, 2239 2239 ESsquare, 2240 2240 ESgetpars, 2241 + ESgetsubpars, 2241 2242 ESfunckey, 2242 2243 EShash, 2243 2244 ESsetG0, ··· 2760 2759 fallthrough; 2761 2760 case ESgetpars: /* ESC [ aka CSI, parameters expected */ 2762 2761 switch (c) { 2762 + case ':': /* ITU-T T.416 color subparameters */ 2763 + if (vc->vc_par[vc->vc_npar] == CSI_m_FG_COLOR || 2764 + vc->vc_par[vc->vc_npar] == CSI_m_BG_COLOR || 2765 + vc->vc_par[vc->vc_npar] == CSI_m_UNDERLINE_COLOR) 2766 + vc->vc_state = ESgetsubpars; 2767 + else 2768 + break; 2769 + fallthrough; 2770 + case ';': 2771 + if (vc->vc_npar < NPAR - 1) { 2772 + vc->vc_npar++; 2773 + return; 2774 + } 2775 + break; 2776 + case '0' ... '9': 2777 + vc->vc_par[vc->vc_npar] *= 10; 2778 + vc->vc_par[vc->vc_npar] += c - '0'; 2779 + return; 2780 + } 2781 + if (c >= ASCII_CSI_IGNORE_FIRST && c <= ASCII_CSI_IGNORE_LAST) { 2782 + vc->vc_state = EScsiignore; 2783 + return; 2784 + } 2785 + 2786 + /* parameters done, handle the control char @c */ 2787 + 2788 + vc->vc_state = ESnormal; 2789 + 2790 + switch (vc->vc_priv) { 2791 + case EPdec: 2792 + csi_DEC(tty, vc, c); 2793 + return; 2794 + case EPecma: 2795 + csi_ECMA(tty, vc, c); 2796 + return; 2797 + default: 2798 + return; 2799 + } 2800 + case ESgetsubpars: /* ESC [ 38/48/58, subparameters expected */ 2801 + switch (c) { 2802 + case ':': 2763 2803 case ';': 2764 2804 if (vc->vc_npar < NPAR - 1) { 2765 2805 vc->vc_npar++;

+5 -4

include/linux/serdev.h

··· 37 37 * @nr: Device number on serdev bus. 38 38 * @ctrl: serdev controller managing this device. 39 39 * @ops: Device operations. 40 - * @write_comp Completion used by serdev_device_write() internally 41 - * @write_lock Lock to serialize access when writing data 40 + * @write_comp: Completion used by serdev_device_write() internally 41 + * @write_lock: Lock to serialize access when writing data 42 42 */ 43 43 struct serdev_device { 44 44 struct device dev; ··· 57 57 * structure. 58 58 * @probe: binds this driver to a serdev device. 59 59 * @remove: unbinds this driver from the serdev device. 60 + * @shutdown: shut down this serdev device. 60 61 */ 61 62 struct serdev_device_driver { 62 63 struct device_driver driver; ··· 121 120 122 121 /** 123 122 * serdev_device_put() - decrement serdev device refcount 124 - * @serdev serdev device. 123 + * @serdev: serdev device. 125 124 */ 126 125 static inline void serdev_device_put(struct serdev_device *serdev) 127 126 { ··· 149 148 150 149 /** 151 150 * serdev_controller_put() - decrement controller refcount 152 - * @ctrl serdev controller. 151 + * @ctrl: serdev controller. 153 152 */ 154 153 static inline void serdev_controller_put(struct serdev_controller *ctrl) 155 154 {

+1

include/linux/tty_buffer.h

··· 34 34 35 35 struct tty_bufhead { 36 36 struct tty_buffer *head; /* Queue head */ 37 + struct workqueue_struct *flip_wq; 37 38 struct work_struct work; 38 39 struct mutex lock; 39 40 atomic_t priority;

+7

include/linux/tty_driver.h

··· 69 69 * Do not create numbered ``/dev`` nodes. For example, create 70 70 * ``/dev/ttyprintk`` and not ``/dev/ttyprintk0``. Applicable only when a 71 71 * driver for a single tty device is being allocated. 72 + * 73 + * @TTY_DRIVER_NO_WORKQUEUE: 74 + * Do not create workqueue when tty_register_driver(). Whenever set, flip 75 + * buffer workqueue can be set by tty_port_link_wq() for every port. 72 76 */ 73 77 enum tty_driver_flag { 74 78 TTY_DRIVER_INSTALLED = BIT(0), ··· 83 79 TTY_DRIVER_HARDWARE_BREAK = BIT(5), 84 80 TTY_DRIVER_DYNAMIC_ALLOC = BIT(6), 85 81 TTY_DRIVER_UNNUMBERED_NODE = BIT(7), 82 + TTY_DRIVER_NO_WORKQUEUE = BIT(8), 86 83 }; 87 84 88 85 enum tty_driver_type { ··· 511 506 * @flags: tty driver flags (%TTY_DRIVER_) 512 507 * @proc_entry: proc fs entry, used internally 513 508 * @other: driver of the linked tty; only used for the PTY driver 509 + * @flip_wq: workqueue to queue flip buffer work on 514 510 * @ttys: array of active &struct tty_struct, set by tty_standard_install() 515 511 * @ports: array of &struct tty_port; can be set during initialization by 516 512 * tty_port_link_device() and similar ··· 545 539 unsigned long flags; 546 540 struct proc_dir_entry *proc_entry; 547 541 struct tty_driver *other; 542 + struct workqueue_struct *flip_wq; 548 543 549 544 /* 550 545 * Pointer to the tty data structures

+3 -3

include/linux/tty_ldisc.h

··· 266 266 }; 267 267 268 268 struct tty_ldisc { 269 - struct tty_ldisc_ops *ops; 269 + const struct tty_ldisc_ops *ops; 270 270 struct tty_struct *tty; 271 271 }; 272 272 ··· 281 281 282 282 void tty_ldisc_flush(struct tty_struct *tty); 283 283 284 - int tty_register_ldisc(struct tty_ldisc_ops *new_ldisc); 285 - void tty_unregister_ldisc(struct tty_ldisc_ops *ldisc); 284 + int tty_register_ldisc(const struct tty_ldisc_ops *new_ldisc); 285 + void tty_unregister_ldisc(const struct tty_ldisc_ops *ldisc); 286 286 int tty_set_ldisc(struct tty_struct *tty, int disc); 287 287 288 288 #endif /* _LINUX_TTY_LDISC_H */

+13

include/linux/tty_port.h

··· 138 138 kernel */ 139 139 140 140 void tty_port_init(struct tty_port *port); 141 + void tty_port_link_wq(struct tty_port *port, struct workqueue_struct *flip_wq); 141 142 void tty_port_link_device(struct tty_port *port, struct tty_driver *driver, 142 143 unsigned index); 143 144 struct device *tty_port_register_device(struct tty_port *port, ··· 164 163 if (port && kref_get_unless_zero(&port->kref)) 165 164 return port; 166 165 return NULL; 166 + } 167 + 168 + /* 169 + * Never overwrite the workqueue set by tty_port_link_wq(). 170 + * No effect when %TTY_DRIVER_NO_WORKQUEUE is set, as driver->flip_wq is 171 + * %NULL. 172 + */ 173 + static inline void tty_port_link_driver_wq(struct tty_port *port, 174 + struct tty_driver *driver) 175 + { 176 + if (!port->buf.flip_wq) 177 + tty_port_link_wq(port, driver->flip_wq); 167 178 } 168 179 169 180 /* If the cts flow control is enabled, return true. */

+29

include/uapi/linux/keyboard.h

··· 41 41 #define KT_SLOCK 12 42 42 #define KT_DEAD2 13 43 43 #define KT_BRL 14 44 + #define KT_CSI 15 /* CSI sequences with modifier support */ 44 45 45 46 #define K(t,v) (((t)<<8)|(v)) 46 47 #define KTYP(x) ((x) >> 8) ··· 461 460 #define K_BRL_DOT10 K(KT_BRL, 10) 462 461 463 462 #define NR_BRL 11 463 + 464 + /* KT_CSI keys: value is the CSI parameter number for ESC [ <value> ~ */ 465 + #define K_CSI_HOME K(KT_CSI, 1) /* ESC [ 1 ~ */ 466 + #define K_CSI_INSERT K(KT_CSI, 2) /* ESC [ 2 ~ */ 467 + #define K_CSI_DELETE K(KT_CSI, 3) /* ESC [ 3 ~ */ 468 + #define K_CSI_END K(KT_CSI, 4) /* ESC [ 4 ~ */ 469 + #define K_CSI_PGUP K(KT_CSI, 5) /* ESC [ 5 ~ */ 470 + #define K_CSI_PGDN K(KT_CSI, 6) /* ESC [ 6 ~ */ 471 + #define K_CSI_F1 K(KT_CSI, 11) /* ESC [ 11 ~ */ 472 + #define K_CSI_F2 K(KT_CSI, 12) /* ESC [ 12 ~ */ 473 + #define K_CSI_F3 K(KT_CSI, 13) /* ESC [ 13 ~ */ 474 + #define K_CSI_F4 K(KT_CSI, 14) /* ESC [ 14 ~ */ 475 + #define K_CSI_F5 K(KT_CSI, 15) /* ESC [ 15 ~ */ 476 + #define K_CSI_F6 K(KT_CSI, 17) /* ESC [ 17 ~ */ 477 + #define K_CSI_F7 K(KT_CSI, 18) /* ESC [ 18 ~ */ 478 + #define K_CSI_F8 K(KT_CSI, 19) /* ESC [ 19 ~ */ 479 + #define K_CSI_F9 K(KT_CSI, 20) /* ESC [ 20 ~ */ 480 + #define K_CSI_F10 K(KT_CSI, 21) /* ESC [ 21 ~ */ 481 + #define K_CSI_F11 K(KT_CSI, 23) /* ESC [ 23 ~ */ 482 + #define K_CSI_F12 K(KT_CSI, 24) /* ESC [ 24 ~ */ 483 + #define K_CSI_F13 K(KT_CSI, 25) /* ESC [ 25 ~ */ 484 + #define K_CSI_F14 K(KT_CSI, 26) /* ESC [ 26 ~ */ 485 + #define K_CSI_F15 K(KT_CSI, 28) /* ESC [ 28 ~ */ 486 + #define K_CSI_F16 K(KT_CSI, 29) /* ESC [ 29 ~ */ 487 + #define K_CSI_F17 K(KT_CSI, 31) /* ESC [ 31 ~ */ 488 + #define K_CSI_F18 K(KT_CSI, 32) /* ESC [ 32 ~ */ 489 + #define K_CSI_F19 K(KT_CSI, 33) /* ESC [ 33 ~ */ 490 + #define K_CSI_F20 K(KT_CSI, 34) /* ESC [ 34 ~ */ 464 491 465 492 #define MAX_DIACR 256 466 493 #endif /* _UAPI__LINUX_KEYBOARD_H */

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