tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

clk: qcom: gcc-sm7150: constify clk_init_data structures

The clk_init_data structures are never modified, make them const.

No functional changes.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20240505201038.276047-3-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Danila Tikhonov and committed by
Bjorn Andersson 734b6e7a 97cf9296

+196 -196
+196 -196
drivers/clk/qcom/gcc-sm7150.c
··· 44 44 .clkr = { 45 45 .enable_reg = 0x52000, 46 46 .enable_mask = BIT(0), 47 - .hw.init = &(struct clk_init_data){ 47 + .hw.init = &(const struct clk_init_data) { 48 48 .name = "gpll0", 49 - .parent_data = &(const struct clk_parent_data){ 49 + .parent_data = &(const struct clk_parent_data) { 50 50 .index = DT_BI_TCXO, 51 51 }, 52 52 .num_parents = 1, ··· 70 70 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 71 71 .width = 4, 72 72 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 73 - .clkr.hw.init = &(struct clk_init_data){ 73 + .clkr.hw.init = &(const struct clk_init_data) { 74 74 .name = "gpll0_out_even", 75 - .parent_hws = (const struct clk_hw*[]){ 75 + .parent_hws = (const struct clk_hw*[]) { 76 76 &gpll0.clkr.hw, 77 77 }, 78 78 .num_parents = 1, ··· 83 83 static struct clk_fixed_factor gcc_pll0_main_div_cdiv = { 84 84 .mult = 1, 85 85 .div = 2, 86 - .hw.init = &(struct clk_init_data){ 86 + .hw.init = &(const struct clk_init_data) { 87 87 .name = "gcc_pll0_main_div_cdiv", 88 - .parent_hws = (const struct clk_hw*[]){ 88 + .parent_hws = (const struct clk_hw*[]) { 89 89 &gpll0.clkr.hw, 90 90 }, 91 91 .num_parents = 1, ··· 99 99 .clkr = { 100 100 .enable_reg = 0x52000, 101 101 .enable_mask = BIT(6), 102 - .hw.init = &(struct clk_init_data){ 102 + .hw.init = &(const struct clk_init_data) { 103 103 .name = "gpll6", 104 - .parent_data = &(const struct clk_parent_data){ 104 + .parent_data = &(const struct clk_parent_data) { 105 105 .index = DT_BI_TCXO, 106 106 }, 107 107 .num_parents = 1, ··· 116 116 .clkr = { 117 117 .enable_reg = 0x52000, 118 118 .enable_mask = BIT(7), 119 - .hw.init = &(struct clk_init_data){ 119 + .hw.init = &(const struct clk_init_data) { 120 120 .name = "gpll7", 121 - .parent_data = &(const struct clk_parent_data){ 121 + .parent_data = &(const struct clk_parent_data) { 122 122 .index = DT_BI_TCXO, 123 123 }, 124 124 .num_parents = 1, ··· 252 252 .hid_width = 5, 253 253 .parent_map = gcc_parent_map_0, 254 254 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 255 - .clkr.hw.init = &(struct clk_init_data){ 255 + .clkr.hw.init = &(const struct clk_init_data) { 256 256 .name = "gcc_cpuss_ahb_clk_src", 257 257 .parent_data = gcc_parent_data_0_ao, 258 258 .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao), ··· 272 272 .hid_width = 5, 273 273 .parent_map = gcc_parent_map_2, 274 274 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, 275 - .clkr.hw.init = &(struct clk_init_data){ 275 + .clkr.hw.init = &(const struct clk_init_data) { 276 276 .name = "gcc_cpuss_rbcpr_clk_src", 277 277 .parent_data = gcc_parent_data_2_ao, 278 278 .num_parents = ARRAY_SIZE(gcc_parent_data_2_ao), ··· 295 295 .hid_width = 5, 296 296 .parent_map = gcc_parent_map_1, 297 297 .freq_tbl = ftbl_gcc_gp1_clk_src, 298 - .clkr.hw.init = &(struct clk_init_data){ 298 + .clkr.hw.init = &(const struct clk_init_data) { 299 299 .name = "gcc_gp1_clk_src", 300 300 .parent_data = gcc_parent_data_1, 301 301 .num_parents = ARRAY_SIZE(gcc_parent_data_1), ··· 309 309 .hid_width = 5, 310 310 .parent_map = gcc_parent_map_1, 311 311 .freq_tbl = ftbl_gcc_gp1_clk_src, 312 - .clkr.hw.init = &(struct clk_init_data){ 312 + .clkr.hw.init = &(const struct clk_init_data) { 313 313 .name = "gcc_gp2_clk_src", 314 314 .parent_data = gcc_parent_data_1, 315 315 .num_parents = ARRAY_SIZE(gcc_parent_data_1), ··· 323 323 .hid_width = 5, 324 324 .parent_map = gcc_parent_map_1, 325 325 .freq_tbl = ftbl_gcc_gp1_clk_src, 326 - .clkr.hw.init = &(struct clk_init_data){ 326 + .clkr.hw.init = &(const struct clk_init_data) { 327 327 .name = "gcc_gp3_clk_src", 328 328 .parent_data = gcc_parent_data_1, 329 329 .num_parents = ARRAY_SIZE(gcc_parent_data_1), ··· 343 343 .hid_width = 5, 344 344 .parent_map = gcc_parent_map_3, 345 345 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 346 - .clkr.hw.init = &(struct clk_init_data){ 346 + .clkr.hw.init = &(const struct clk_init_data) { 347 347 .name = "gcc_pcie_0_aux_clk_src", 348 348 .parent_data = gcc_parent_data_3, 349 349 .num_parents = ARRAY_SIZE(gcc_parent_data_3), ··· 363 363 .hid_width = 5, 364 364 .parent_map = gcc_parent_map_0, 365 365 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, 366 - .clkr.hw.init = &(struct clk_init_data){ 366 + .clkr.hw.init = &(const struct clk_init_data) { 367 367 .name = "gcc_pcie_phy_refgen_clk_src", 368 368 .parent_data = gcc_parent_data_0, 369 369 .num_parents = ARRAY_SIZE(gcc_parent_data_0), ··· 383 383 .hid_width = 5, 384 384 .parent_map = gcc_parent_map_0, 385 385 .freq_tbl = ftbl_gcc_pdm2_clk_src, 386 - .clkr.hw.init = &(struct clk_init_data){ 386 + .clkr.hw.init = &(const struct clk_init_data) { 387 387 .name = "gcc_pdm2_clk_src", 388 388 .parent_data = gcc_parent_data_0, 389 389 .num_parents = ARRAY_SIZE(gcc_parent_data_0), ··· 687 687 .hid_width = 5, 688 688 .parent_map = gcc_parent_map_5, 689 689 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 690 - .clkr.hw.init = &(struct clk_init_data){ 690 + .clkr.hw.init = &(const struct clk_init_data) { 691 691 .name = "gcc_sdcc1_apps_clk_src", 692 692 .parent_data = gcc_parent_data_5, 693 693 .num_parents = ARRAY_SIZE(gcc_parent_data_5), ··· 709 709 .hid_width = 5, 710 710 .parent_map = gcc_parent_map_0, 711 711 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 712 - .clkr.hw.init = &(struct clk_init_data){ 712 + .clkr.hw.init = &(const struct clk_init_data) { 713 713 .name = "gcc_sdcc1_ice_core_clk_src", 714 714 .parent_data = gcc_parent_data_0, 715 715 .num_parents = ARRAY_SIZE(gcc_parent_data_0), ··· 734 734 .hid_width = 5, 735 735 .parent_map = gcc_parent_map_6, 736 736 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 737 - .clkr.hw.init = &(struct clk_init_data){ 737 + .clkr.hw.init = &(const struct clk_init_data) { 738 738 .name = "gcc_sdcc2_apps_clk_src", 739 739 .parent_data = gcc_parent_data_6, 740 740 .num_parents = ARRAY_SIZE(gcc_parent_data_6), ··· 760 760 .hid_width = 5, 761 761 .parent_map = gcc_parent_map_0, 762 762 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 763 - .clkr.hw.init = &(struct clk_init_data){ 763 + .clkr.hw.init = &(const struct clk_init_data) { 764 764 .name = "gcc_sdcc4_apps_clk_src", 765 765 .parent_data = gcc_parent_data_0, 766 766 .num_parents = ARRAY_SIZE(gcc_parent_data_0), ··· 779 779 .hid_width = 5, 780 780 .parent_map = gcc_parent_map_7, 781 781 .freq_tbl = ftbl_gcc_tsif_ref_clk_src, 782 - .clkr.hw.init = &(struct clk_init_data){ 782 + .clkr.hw.init = &(const struct clk_init_data) { 783 783 .name = "gcc_tsif_ref_clk_src", 784 784 .parent_data = gcc_parent_data_7, 785 785 .num_parents = ARRAY_SIZE(gcc_parent_data_7), ··· 802 802 .hid_width = 5, 803 803 .parent_map = gcc_parent_map_0, 804 804 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 805 - .clkr.hw.init = &(struct clk_init_data){ 805 + .clkr.hw.init = &(const struct clk_init_data) { 806 806 .name = "gcc_ufs_phy_axi_clk_src", 807 807 .parent_data = gcc_parent_data_0, 808 808 .num_parents = ARRAY_SIZE(gcc_parent_data_0), ··· 824 824 .hid_width = 5, 825 825 .parent_map = gcc_parent_map_0, 826 826 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 827 - .clkr.hw.init = &(struct clk_init_data){ 827 + .clkr.hw.init = &(const struct clk_init_data) { 828 828 .name = "gcc_ufs_phy_ice_core_clk_src", 829 829 .parent_data = gcc_parent_data_0, 830 830 .num_parents = ARRAY_SIZE(gcc_parent_data_0), ··· 838 838 .hid_width = 5, 839 839 .parent_map = gcc_parent_map_4, 840 840 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 841 - .clkr.hw.init = &(struct clk_init_data){ 841 + .clkr.hw.init = &(const struct clk_init_data) { 842 842 .name = "gcc_ufs_phy_phy_aux_clk_src", 843 843 .parent_data = gcc_parent_data_4, 844 844 .num_parents = ARRAY_SIZE(gcc_parent_data_4), ··· 859 859 .hid_width = 5, 860 860 .parent_map = gcc_parent_map_0, 861 861 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 862 - .clkr.hw.init = &(struct clk_init_data){ 862 + .clkr.hw.init = &(const struct clk_init_data) { 863 863 .name = "gcc_ufs_phy_unipro_core_clk_src", 864 864 .parent_data = gcc_parent_data_0, 865 865 .num_parents = ARRAY_SIZE(gcc_parent_data_0), ··· 881 881 .hid_width = 5, 882 882 .parent_map = gcc_parent_map_0, 883 883 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 884 - .clkr.hw.init = &(struct clk_init_data){ 884 + .clkr.hw.init = &(const struct clk_init_data) { 885 885 .name = "gcc_usb30_prim_master_clk_src", 886 886 .parent_data = gcc_parent_data_0, 887 887 .num_parents = ARRAY_SIZE(gcc_parent_data_0), ··· 903 903 .hid_width = 5, 904 904 .parent_map = gcc_parent_map_0, 905 905 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 906 - .clkr.hw.init = &(struct clk_init_data){ 906 + .clkr.hw.init = &(const struct clk_init_data) { 907 907 .name = "gcc_usb30_prim_mock_utmi_clk_src", 908 908 .parent_data = gcc_parent_data_0, 909 909 .num_parents = ARRAY_SIZE(gcc_parent_data_0), ··· 922 922 .hid_width = 5, 923 923 .parent_map = gcc_parent_map_3, 924 924 .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, 925 - .clkr.hw.init = &(struct clk_init_data){ 925 + .clkr.hw.init = &(const struct clk_init_data) { 926 926 .name = "gcc_usb3_prim_phy_aux_clk_src", 927 927 .parent_data = gcc_parent_data_3, 928 928 .num_parents = ARRAY_SIZE(gcc_parent_data_3), ··· 936 936 .hid_width = 5, 937 937 .parent_map = gcc_parent_map_2, 938 938 .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, 939 - .clkr.hw.init = &(struct clk_init_data){ 939 + .clkr.hw.init = &(const struct clk_init_data) { 940 940 .name = "gcc_vs_ctrl_clk_src", 941 941 .parent_data = gcc_parent_data_2, 942 942 .num_parents = ARRAY_SIZE(gcc_parent_data_2), ··· 957 957 .hid_width = 5, 958 958 .parent_map = gcc_parent_map_8, 959 959 .freq_tbl = ftbl_gcc_vsensor_clk_src, 960 - .clkr.hw.init = &(struct clk_init_data){ 960 + .clkr.hw.init = &(const struct clk_init_data) { 961 961 .name = "gcc_vsensor_clk_src", 962 962 .parent_data = gcc_parent_data_8, 963 963 .num_parents = ARRAY_SIZE(gcc_parent_data_8), ··· 971 971 .clkr = { 972 972 .enable_reg = 0x2800c, 973 973 .enable_mask = BIT(0), 974 - .hw.init = &(struct clk_init_data){ 974 + .hw.init = &(const struct clk_init_data) { 975 975 .name = "gcc_aggre_noc_pcie_tbu_clk", 976 976 .ops = &clk_branch2_ops, 977 977 }, ··· 986 986 .clkr = { 987 987 .enable_reg = 0x82024, 988 988 .enable_mask = BIT(0), 989 - .hw.init = &(struct clk_init_data){ 989 + .hw.init = &(const struct clk_init_data) { 990 990 .name = "gcc_aggre_ufs_phy_axi_clk", 991 - .parent_hws = (const struct clk_hw*[]){ 991 + .parent_hws = (const struct clk_hw*[]) { 992 992 &gcc_ufs_phy_axi_clk_src.clkr.hw, 993 993 }, 994 994 .num_parents = 1, ··· 1006 1006 .clkr = { 1007 1007 .enable_reg = 0x82024, 1008 1008 .enable_mask = BIT(1), 1009 - .hw.init = &(struct clk_init_data){ 1009 + .hw.init = &(const struct clk_init_data) { 1010 1010 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", 1011 - .parent_hws = (const struct clk_hw*[]){ 1011 + .parent_hws = (const struct clk_hw*[]) { 1012 1012 &gcc_aggre_ufs_phy_axi_clk.clkr.hw, 1013 1013 }, 1014 1014 .num_parents = 1, ··· 1024 1024 .clkr = { 1025 1025 .enable_reg = 0x8201c, 1026 1026 .enable_mask = BIT(0), 1027 - .hw.init = &(struct clk_init_data){ 1027 + .hw.init = &(const struct clk_init_data) { 1028 1028 .name = "gcc_aggre_usb3_prim_axi_clk", 1029 - .parent_hws = (const struct clk_hw*[]){ 1029 + .parent_hws = (const struct clk_hw*[]) { 1030 1030 &gcc_usb30_prim_master_clk_src.clkr.hw, 1031 1031 }, 1032 1032 .num_parents = 1, ··· 1042 1042 .clkr = { 1043 1043 .enable_reg = 0x7a050, 1044 1044 .enable_mask = BIT(0), 1045 - .hw.init = &(struct clk_init_data){ 1045 + .hw.init = &(const struct clk_init_data) { 1046 1046 .name = "gcc_apc_vs_clk", 1047 - .parent_hws = (const struct clk_hw*[]){ 1047 + .parent_hws = (const struct clk_hw*[]) { 1048 1048 &gcc_vsensor_clk_src.clkr.hw, 1049 1049 }, 1050 1050 .num_parents = 1, ··· 1062 1062 .clkr = { 1063 1063 .enable_reg = 0x52004, 1064 1064 .enable_mask = BIT(10), 1065 - .hw.init = &(struct clk_init_data){ 1065 + .hw.init = &(const struct clk_init_data) { 1066 1066 .name = "gcc_boot_rom_ahb_clk", 1067 1067 .ops = &clk_branch2_ops, 1068 1068 }, ··· 1075 1075 .clkr = { 1076 1076 .enable_reg = 0xb020, 1077 1077 .enable_mask = BIT(0), 1078 - .hw.init = &(struct clk_init_data){ 1078 + .hw.init = &(const struct clk_init_data) { 1079 1079 .name = "gcc_camera_hf_axi_clk", 1080 1080 .ops = &clk_branch2_ops, 1081 1081 }, ··· 1088 1088 .clkr = { 1089 1089 .enable_reg = 0xb06c, 1090 1090 .enable_mask = BIT(0), 1091 - .hw.init = &(struct clk_init_data){ 1091 + .hw.init = &(const struct clk_init_data) { 1092 1092 .name = "gcc_camera_sf_axi_clk", 1093 1093 .ops = &clk_branch2_ops, 1094 1094 }, ··· 1103 1103 .clkr = { 1104 1104 .enable_reg = 0x52004, 1105 1105 .enable_mask = BIT(3), 1106 - .hw.init = &(struct clk_init_data){ 1106 + .hw.init = &(const struct clk_init_data) { 1107 1107 .name = "gcc_ce1_ahb_clk", 1108 1108 .ops = &clk_branch2_ops, 1109 1109 }, ··· 1116 1116 .clkr = { 1117 1117 .enable_reg = 0x52004, 1118 1118 .enable_mask = BIT(4), 1119 - .hw.init = &(struct clk_init_data){ 1119 + .hw.init = &(const struct clk_init_data) { 1120 1120 .name = "gcc_ce1_axi_clk", 1121 1121 .ops = &clk_branch2_ops, 1122 1122 }, ··· 1129 1129 .clkr = { 1130 1130 .enable_reg = 0x52004, 1131 1131 .enable_mask = BIT(5), 1132 - .hw.init = &(struct clk_init_data){ 1132 + .hw.init = &(const struct clk_init_data) { 1133 1133 .name = "gcc_ce1_clk", 1134 1134 .ops = &clk_branch2_ops, 1135 1135 }, ··· 1142 1142 .clkr = { 1143 1143 .enable_reg = 0x502c, 1144 1144 .enable_mask = BIT(0), 1145 - .hw.init = &(struct clk_init_data){ 1145 + .hw.init = &(const struct clk_init_data) { 1146 1146 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1147 - .parent_hws = (const struct clk_hw*[]){ 1147 + .parent_hws = (const struct clk_hw*[]) { 1148 1148 &gcc_usb30_prim_master_clk_src.clkr.hw, 1149 1149 }, 1150 1150 .num_parents = 1, ··· 1160 1160 .clkr = { 1161 1161 .enable_reg = 0x52004, 1162 1162 .enable_mask = BIT(21), 1163 - .hw.init = &(struct clk_init_data){ 1163 + .hw.init = &(const struct clk_init_data) { 1164 1164 .name = "gcc_cpuss_ahb_clk", 1165 - .parent_hws = (const struct clk_hw*[]){ 1165 + .parent_hws = (const struct clk_hw*[]) { 1166 1166 &gcc_cpuss_ahb_clk_src.clkr.hw, 1167 1167 }, 1168 1168 .num_parents = 1, ··· 1178 1178 .clkr = { 1179 1179 .enable_reg = 0x48008, 1180 1180 .enable_mask = BIT(0), 1181 - .hw.init = &(struct clk_init_data){ 1181 + .hw.init = &(const struct clk_init_data) { 1182 1182 .name = "gcc_cpuss_rbcpr_clk", 1183 - .parent_hws = (const struct clk_hw*[]){ 1183 + .parent_hws = (const struct clk_hw*[]) { 1184 1184 &gcc_cpuss_rbcpr_clk_src.clkr.hw, 1185 1185 }, 1186 1186 .num_parents = 1, ··· 1196 1196 .clkr = { 1197 1197 .enable_reg = 0x4452c, 1198 1198 .enable_mask = BIT(0), 1199 - .hw.init = &(struct clk_init_data){ 1199 + .hw.init = &(const struct clk_init_data) { 1200 1200 .name = "gcc_ddrss_gpu_axi_clk", 1201 1201 .ops = &clk_branch2_ops, 1202 1202 }, ··· 1209 1209 .clkr = { 1210 1210 .enable_reg = 0x52004, 1211 1211 .enable_mask = BIT(18), 1212 - .hw.init = &(struct clk_init_data){ 1212 + .hw.init = &(const struct clk_init_data) { 1213 1213 .name = "gcc_disp_gpll0_clk_src", 1214 - .parent_hws = (const struct clk_hw*[]){ 1214 + .parent_hws = (const struct clk_hw*[]) { 1215 1215 &gpll0.clkr.hw, 1216 1216 }, 1217 1217 .num_parents = 1, ··· 1225 1225 .clkr = { 1226 1226 .enable_reg = 0x52004, 1227 1227 .enable_mask = BIT(19), 1228 - .hw.init = &(struct clk_init_data){ 1228 + .hw.init = &(const struct clk_init_data) { 1229 1229 .name = "gcc_disp_gpll0_div_clk_src", 1230 - .parent_hws = (const struct clk_hw*[]){ 1230 + .parent_hws = (const struct clk_hw*[]) { 1231 1231 &gcc_pll0_main_div_cdiv.hw, 1232 1232 }, 1233 1233 .num_parents = 1, ··· 1242 1242 .clkr = { 1243 1243 .enable_reg = 0xb024, 1244 1244 .enable_mask = BIT(0), 1245 - .hw.init = &(struct clk_init_data){ 1245 + .hw.init = &(const struct clk_init_data) { 1246 1246 .name = "gcc_disp_hf_axi_clk", 1247 1247 .ops = &clk_branch2_ops, 1248 1248 }, ··· 1255 1255 .clkr = { 1256 1256 .enable_reg = 0xb070, 1257 1257 .enable_mask = BIT(0), 1258 - .hw.init = &(struct clk_init_data){ 1258 + .hw.init = &(const struct clk_init_data) { 1259 1259 .name = "gcc_disp_sf_axi_clk", 1260 1260 .ops = &clk_branch2_ops, 1261 1261 }, ··· 1269 1269 .clkr = { 1270 1270 .enable_reg = 0x64000, 1271 1271 .enable_mask = BIT(0), 1272 - .hw.init = &(struct clk_init_data){ 1272 + .hw.init = &(const struct clk_init_data) { 1273 1273 .name = "gcc_gp1_clk", 1274 - .parent_hws = (const struct clk_hw*[]){ 1274 + .parent_hws = (const struct clk_hw*[]) { 1275 1275 &gcc_gp1_clk_src.clkr.hw, 1276 1276 }, 1277 1277 .num_parents = 1, ··· 1287 1287 .clkr = { 1288 1288 .enable_reg = 0x65000, 1289 1289 .enable_mask = BIT(0), 1290 - .hw.init = &(struct clk_init_data){ 1290 + .hw.init = &(const struct clk_init_data) { 1291 1291 .name = "gcc_gp2_clk", 1292 - .parent_hws = (const struct clk_hw*[]){ 1292 + .parent_hws = (const struct clk_hw*[]) { 1293 1293 &gcc_gp2_clk_src.clkr.hw, 1294 1294 }, 1295 1295 .num_parents = 1, ··· 1305 1305 .clkr = { 1306 1306 .enable_reg = 0x66000, 1307 1307 .enable_mask = BIT(0), 1308 - .hw.init = &(struct clk_init_data){ 1308 + .hw.init = &(const struct clk_init_data) { 1309 1309 .name = "gcc_gp3_clk", 1310 - .parent_hws = (const struct clk_hw*[]){ 1310 + .parent_hws = (const struct clk_hw*[]) { 1311 1311 &gcc_gp3_clk_src.clkr.hw, 1312 1312 }, 1313 1313 .num_parents = 1, ··· 1322 1322 .clkr = { 1323 1323 .enable_reg = 0x52004, 1324 1324 .enable_mask = BIT(15), 1325 - .hw.init = &(struct clk_init_data){ 1325 + .hw.init = &(const struct clk_init_data) { 1326 1326 .name = "gcc_gpu_gpll0_clk_src", 1327 - .parent_hws = (const struct clk_hw*[]){ 1327 + .parent_hws = (const struct clk_hw*[]) { 1328 1328 &gpll0.clkr.hw, 1329 1329 }, 1330 1330 .num_parents = 1, ··· 1338 1338 .clkr = { 1339 1339 .enable_reg = 0x52004, 1340 1340 .enable_mask = BIT(16), 1341 - .hw.init = &(struct clk_init_data){ 1341 + .hw.init = &(const struct clk_init_data) { 1342 1342 .name = "gcc_gpu_gpll0_div_clk_src", 1343 - .parent_hws = (const struct clk_hw*[]){ 1343 + .parent_hws = (const struct clk_hw*[]) { 1344 1344 &gcc_pll0_main_div_cdiv.hw, 1345 1345 }, 1346 1346 .num_parents = 1, ··· 1355 1355 .clkr = { 1356 1356 .enable_reg = 0x7100c, 1357 1357 .enable_mask = BIT(0), 1358 - .hw.init = &(struct clk_init_data){ 1358 + .hw.init = &(const struct clk_init_data) { 1359 1359 .name = "gcc_gpu_memnoc_gfx_clk", 1360 1360 .ops = &clk_branch2_ops, 1361 1361 }, ··· 1368 1368 .clkr = { 1369 1369 .enable_reg = 0x71018, 1370 1370 .enable_mask = BIT(0), 1371 - .hw.init = &(struct clk_init_data){ 1371 + .hw.init = &(const struct clk_init_data) { 1372 1372 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1373 1373 .ops = &clk_branch2_ops, 1374 1374 }, ··· 1381 1381 .clkr = { 1382 1382 .enable_reg = 0x7a04c, 1383 1383 .enable_mask = BIT(0), 1384 - .hw.init = &(struct clk_init_data){ 1384 + .hw.init = &(const struct clk_init_data) { 1385 1385 .name = "gcc_gpu_vs_clk", 1386 - .parent_hws = (const struct clk_hw*[]){ 1386 + .parent_hws = (const struct clk_hw*[]) { 1387 1387 &gcc_vsensor_clk_src.clkr.hw, 1388 1388 }, 1389 1389 .num_parents = 1, ··· 1399 1399 .clkr = { 1400 1400 .enable_reg = 0x4d008, 1401 1401 .enable_mask = BIT(0), 1402 - .hw.init = &(struct clk_init_data){ 1402 + .hw.init = &(const struct clk_init_data) { 1403 1403 .name = "gcc_npu_axi_clk", 1404 1404 .ops = &clk_branch2_ops, 1405 1405 }, ··· 1414 1414 .clkr = { 1415 1415 .enable_reg = 0x4d004, 1416 1416 .enable_mask = BIT(0), 1417 - .hw.init = &(struct clk_init_data){ 1417 + .hw.init = &(const struct clk_init_data) { 1418 1418 .name = "gcc_npu_cfg_ahb_clk", 1419 1419 .flags = CLK_IS_CRITICAL, 1420 1420 .ops = &clk_branch2_ops, ··· 1427 1427 .clkr = { 1428 1428 .enable_reg = 0x52004, 1429 1429 .enable_mask = BIT(25), 1430 - .hw.init = &(struct clk_init_data){ 1430 + .hw.init = &(const struct clk_init_data) { 1431 1431 .name = "gcc_npu_gpll0_clk_src", 1432 - .parent_hws = (const struct clk_hw*[]){ 1432 + .parent_hws = (const struct clk_hw*[]) { 1433 1433 &gpll0.clkr.hw, 1434 1434 }, 1435 1435 .num_parents = 1, ··· 1443 1443 .clkr = { 1444 1444 .enable_reg = 0x52004, 1445 1445 .enable_mask = BIT(26), 1446 - .hw.init = &(struct clk_init_data){ 1446 + .hw.init = &(const struct clk_init_data) { 1447 1447 .name = "gcc_npu_gpll0_div_clk_src", 1448 - .parent_hws = (const struct clk_hw*[]){ 1448 + .parent_hws = (const struct clk_hw*[]) { 1449 1449 &gcc_pll0_main_div_cdiv.hw, 1450 1450 }, 1451 1451 .num_parents = 1, ··· 1461 1461 .clkr = { 1462 1462 .enable_reg = 0x5200c, 1463 1463 .enable_mask = BIT(3), 1464 - .hw.init = &(struct clk_init_data){ 1464 + .hw.init = &(const struct clk_init_data) { 1465 1465 .name = "gcc_pcie_0_aux_clk", 1466 - .parent_hws = (const struct clk_hw*[]){ 1466 + .parent_hws = (const struct clk_hw*[]) { 1467 1467 &gcc_pcie_0_aux_clk_src.clkr.hw, 1468 1468 }, 1469 1469 .num_parents = 1, ··· 1481 1481 .clkr = { 1482 1482 .enable_reg = 0x5200c, 1483 1483 .enable_mask = BIT(2), 1484 - .hw.init = &(struct clk_init_data){ 1484 + .hw.init = &(const struct clk_init_data) { 1485 1485 .name = "gcc_pcie_0_cfg_ahb_clk", 1486 1486 .ops = &clk_branch2_ops, 1487 1487 }, ··· 1494 1494 .clkr = { 1495 1495 .enable_reg = 0x8c008, 1496 1496 .enable_mask = BIT(0), 1497 - .hw.init = &(struct clk_init_data){ 1497 + .hw.init = &(const struct clk_init_data) { 1498 1498 .name = "gcc_pcie_0_clkref_clk", 1499 1499 .ops = &clk_branch2_ops, 1500 1500 }, ··· 1507 1507 .clkr = { 1508 1508 .enable_reg = 0x5200c, 1509 1509 .enable_mask = BIT(1), 1510 - .hw.init = &(struct clk_init_data){ 1510 + .hw.init = &(const struct clk_init_data) { 1511 1511 .name = "gcc_pcie_0_mstr_axi_clk", 1512 1512 .ops = &clk_branch2_ops, 1513 1513 }, ··· 1520 1520 .clkr = { 1521 1521 .enable_reg = 0x5200c, 1522 1522 .enable_mask = BIT(4), 1523 - .hw.init = &(struct clk_init_data){ 1523 + .hw.init = &(const struct clk_init_data) { 1524 1524 .name = "gcc_pcie_0_pipe_clk", 1525 1525 .ops = &clk_branch2_ops, 1526 1526 }, ··· 1535 1535 .clkr = { 1536 1536 .enable_reg = 0x5200c, 1537 1537 .enable_mask = BIT(0), 1538 - .hw.init = &(struct clk_init_data){ 1538 + .hw.init = &(const struct clk_init_data) { 1539 1539 .name = "gcc_pcie_0_slv_axi_clk", 1540 1540 .ops = &clk_branch2_ops, 1541 1541 }, ··· 1548 1548 .clkr = { 1549 1549 .enable_reg = 0x5200c, 1550 1550 .enable_mask = BIT(5), 1551 - .hw.init = &(struct clk_init_data){ 1551 + .hw.init = &(const struct clk_init_data) { 1552 1552 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1553 1553 .ops = &clk_branch2_ops, 1554 1554 }, ··· 1561 1561 .clkr = { 1562 1562 .enable_reg = 0x6f004, 1563 1563 .enable_mask = BIT(0), 1564 - .hw.init = &(struct clk_init_data){ 1564 + .hw.init = &(const struct clk_init_data) { 1565 1565 .name = "gcc_pcie_phy_aux_clk", 1566 - .parent_hws = (const struct clk_hw*[]){ 1566 + .parent_hws = (const struct clk_hw*[]) { 1567 1567 &gcc_pcie_0_aux_clk_src.clkr.hw, 1568 1568 }, 1569 1569 .num_parents = 1, ··· 1579 1579 .clkr = { 1580 1580 .enable_reg = 0x6f02c, 1581 1581 .enable_mask = BIT(0), 1582 - .hw.init = &(struct clk_init_data){ 1582 + .hw.init = &(const struct clk_init_data) { 1583 1583 .name = "gcc_pcie_phy_refgen_clk", 1584 - .parent_hws = (const struct clk_hw*[]){ 1584 + .parent_hws = (const struct clk_hw*[]) { 1585 1585 &gcc_pcie_phy_refgen_clk_src.clkr.hw, 1586 1586 }, 1587 1587 .num_parents = 1, ··· 1597 1597 .clkr = { 1598 1598 .enable_reg = 0x3300c, 1599 1599 .enable_mask = BIT(0), 1600 - .hw.init = &(struct clk_init_data){ 1600 + .hw.init = &(const struct clk_init_data) { 1601 1601 .name = "gcc_pdm2_clk", 1602 - .parent_hws = (const struct clk_hw*[]){ 1602 + .parent_hws = (const struct clk_hw*[]) { 1603 1603 &gcc_pdm2_clk_src.clkr.hw, 1604 1604 }, 1605 1605 .num_parents = 1, ··· 1617 1617 .clkr = { 1618 1618 .enable_reg = 0x33004, 1619 1619 .enable_mask = BIT(0), 1620 - .hw.init = &(struct clk_init_data){ 1620 + .hw.init = &(const struct clk_init_data) { 1621 1621 .name = "gcc_pdm_ahb_clk", 1622 1622 .ops = &clk_branch2_ops, 1623 1623 }, ··· 1630 1630 .clkr = { 1631 1631 .enable_reg = 0x33008, 1632 1632 .enable_mask = BIT(0), 1633 - .hw.init = &(struct clk_init_data){ 1633 + .hw.init = &(const struct clk_init_data) { 1634 1634 .name = "gcc_pdm_xo4_clk", 1635 1635 .ops = &clk_branch2_ops, 1636 1636 }, ··· 1645 1645 .clkr = { 1646 1646 .enable_reg = 0x52004, 1647 1647 .enable_mask = BIT(13), 1648 - .hw.init = &(struct clk_init_data){ 1648 + .hw.init = &(const struct clk_init_data) { 1649 1649 .name = "gcc_prng_ahb_clk", 1650 1650 .ops = &clk_branch2_ops, 1651 1651 }, ··· 1658 1658 .clkr = { 1659 1659 .enable_reg = 0x5200c, 1660 1660 .enable_mask = BIT(9), 1661 - .hw.init = &(struct clk_init_data){ 1661 + .hw.init = &(const struct clk_init_data) { 1662 1662 .name = "gcc_qupv3_wrap0_core_2x_clk", 1663 1663 .ops = &clk_branch2_ops, 1664 1664 }, ··· 1671 1671 .clkr = { 1672 1672 .enable_reg = 0x5200c, 1673 1673 .enable_mask = BIT(8), 1674 - .hw.init = &(struct clk_init_data){ 1674 + .hw.init = &(const struct clk_init_data) { 1675 1675 .name = "gcc_qupv3_wrap0_core_clk", 1676 1676 .ops = &clk_branch2_ops, 1677 1677 }, ··· 1684 1684 .clkr = { 1685 1685 .enable_reg = 0x5200c, 1686 1686 .enable_mask = BIT(10), 1687 - .hw.init = &(struct clk_init_data){ 1687 + .hw.init = &(const struct clk_init_data) { 1688 1688 .name = "gcc_qupv3_wrap0_s0_clk", 1689 - .parent_hws = (const struct clk_hw*[]){ 1689 + .parent_hws = (const struct clk_hw*[]) { 1690 1690 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 1691 1691 }, 1692 1692 .num_parents = 1, ··· 1702 1702 .clkr = { 1703 1703 .enable_reg = 0x5200c, 1704 1704 .enable_mask = BIT(11), 1705 - .hw.init = &(struct clk_init_data){ 1705 + .hw.init = &(const struct clk_init_data) { 1706 1706 .name = "gcc_qupv3_wrap0_s1_clk", 1707 - .parent_hws = (const struct clk_hw*[]){ 1707 + .parent_hws = (const struct clk_hw*[]) { 1708 1708 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 1709 1709 }, 1710 1710 .num_parents = 1, ··· 1720 1720 .clkr = { 1721 1721 .enable_reg = 0x5200c, 1722 1722 .enable_mask = BIT(12), 1723 - .hw.init = &(struct clk_init_data){ 1723 + .hw.init = &(const struct clk_init_data) { 1724 1724 .name = "gcc_qupv3_wrap0_s2_clk", 1725 - .parent_hws = (const struct clk_hw*[]){ 1725 + .parent_hws = (const struct clk_hw*[]) { 1726 1726 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 1727 1727 }, 1728 1728 .num_parents = 1, ··· 1738 1738 .clkr = { 1739 1739 .enable_reg = 0x5200c, 1740 1740 .enable_mask = BIT(13), 1741 - .hw.init = &(struct clk_init_data){ 1741 + .hw.init = &(const struct clk_init_data) { 1742 1742 .name = "gcc_qupv3_wrap0_s3_clk", 1743 - .parent_hws = (const struct clk_hw*[]){ 1743 + .parent_hws = (const struct clk_hw*[]) { 1744 1744 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 1745 1745 }, 1746 1746 .num_parents = 1, ··· 1756 1756 .clkr = { 1757 1757 .enable_reg = 0x5200c, 1758 1758 .enable_mask = BIT(14), 1759 - .hw.init = &(struct clk_init_data){ 1759 + .hw.init = &(const struct clk_init_data) { 1760 1760 .name = "gcc_qupv3_wrap0_s4_clk", 1761 - .parent_hws = (const struct clk_hw*[]){ 1761 + .parent_hws = (const struct clk_hw*[]) { 1762 1762 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 1763 1763 }, 1764 1764 .num_parents = 1, ··· 1774 1774 .clkr = { 1775 1775 .enable_reg = 0x5200c, 1776 1776 .enable_mask = BIT(15), 1777 - .hw.init = &(struct clk_init_data){ 1777 + .hw.init = &(const struct clk_init_data) { 1778 1778 .name = "gcc_qupv3_wrap0_s5_clk", 1779 - .parent_hws = (const struct clk_hw*[]){ 1779 + .parent_hws = (const struct clk_hw*[]) { 1780 1780 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 1781 1781 }, 1782 1782 .num_parents = 1, ··· 1792 1792 .clkr = { 1793 1793 .enable_reg = 0x5200c, 1794 1794 .enable_mask = BIT(16), 1795 - .hw.init = &(struct clk_init_data){ 1795 + .hw.init = &(const struct clk_init_data) { 1796 1796 .name = "gcc_qupv3_wrap0_s6_clk", 1797 - .parent_hws = (const struct clk_hw*[]){ 1797 + .parent_hws = (const struct clk_hw*[]) { 1798 1798 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 1799 1799 }, 1800 1800 .num_parents = 1, ··· 1810 1810 .clkr = { 1811 1811 .enable_reg = 0x5200c, 1812 1812 .enable_mask = BIT(17), 1813 - .hw.init = &(struct clk_init_data){ 1813 + .hw.init = &(const struct clk_init_data) { 1814 1814 .name = "gcc_qupv3_wrap0_s7_clk", 1815 - .parent_hws = (const struct clk_hw*[]){ 1815 + .parent_hws = (const struct clk_hw*[]) { 1816 1816 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 1817 1817 }, 1818 1818 .num_parents = 1, ··· 1828 1828 .clkr = { 1829 1829 .enable_reg = 0x5200c, 1830 1830 .enable_mask = BIT(18), 1831 - .hw.init = &(struct clk_init_data){ 1831 + .hw.init = &(const struct clk_init_data) { 1832 1832 .name = "gcc_qupv3_wrap1_core_2x_clk", 1833 1833 .ops = &clk_branch2_ops, 1834 1834 }, ··· 1841 1841 .clkr = { 1842 1842 .enable_reg = 0x5200c, 1843 1843 .enable_mask = BIT(19), 1844 - .hw.init = &(struct clk_init_data){ 1844 + .hw.init = &(const struct clk_init_data) { 1845 1845 .name = "gcc_qupv3_wrap1_core_clk", 1846 1846 .ops = &clk_branch2_ops, 1847 1847 }, ··· 1854 1854 .clkr = { 1855 1855 .enable_reg = 0x5200c, 1856 1856 .enable_mask = BIT(22), 1857 - .hw.init = &(struct clk_init_data){ 1857 + .hw.init = &(const struct clk_init_data) { 1858 1858 .name = "gcc_qupv3_wrap1_s0_clk", 1859 - .parent_hws = (const struct clk_hw*[]){ 1859 + .parent_hws = (const struct clk_hw*[]) { 1860 1860 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 1861 1861 }, 1862 1862 .num_parents = 1, ··· 1872 1872 .clkr = { 1873 1873 .enable_reg = 0x5200c, 1874 1874 .enable_mask = BIT(23), 1875 - .hw.init = &(struct clk_init_data){ 1875 + .hw.init = &(const struct clk_init_data) { 1876 1876 .name = "gcc_qupv3_wrap1_s1_clk", 1877 - .parent_hws = (const struct clk_hw*[]){ 1877 + .parent_hws = (const struct clk_hw*[]) { 1878 1878 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 1879 1879 }, 1880 1880 .num_parents = 1, ··· 1890 1890 .clkr = { 1891 1891 .enable_reg = 0x5200c, 1892 1892 .enable_mask = BIT(24), 1893 - .hw.init = &(struct clk_init_data){ 1893 + .hw.init = &(const struct clk_init_data) { 1894 1894 .name = "gcc_qupv3_wrap1_s2_clk", 1895 - .parent_hws = (const struct clk_hw*[]){ 1895 + .parent_hws = (const struct clk_hw*[]) { 1896 1896 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 1897 1897 }, 1898 1898 .num_parents = 1, ··· 1908 1908 .clkr = { 1909 1909 .enable_reg = 0x5200c, 1910 1910 .enable_mask = BIT(25), 1911 - .hw.init = &(struct clk_init_data){ 1911 + .hw.init = &(const struct clk_init_data) { 1912 1912 .name = "gcc_qupv3_wrap1_s3_clk", 1913 - .parent_hws = (const struct clk_hw*[]){ 1913 + .parent_hws = (const struct clk_hw*[]) { 1914 1914 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 1915 1915 }, 1916 1916 .num_parents = 1, ··· 1926 1926 .clkr = { 1927 1927 .enable_reg = 0x5200c, 1928 1928 .enable_mask = BIT(26), 1929 - .hw.init = &(struct clk_init_data){ 1929 + .hw.init = &(const struct clk_init_data) { 1930 1930 .name = "gcc_qupv3_wrap1_s4_clk", 1931 - .parent_hws = (const struct clk_hw*[]){ 1931 + .parent_hws = (const struct clk_hw*[]) { 1932 1932 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 1933 1933 }, 1934 1934 .num_parents = 1, ··· 1944 1944 .clkr = { 1945 1945 .enable_reg = 0x5200c, 1946 1946 .enable_mask = BIT(27), 1947 - .hw.init = &(struct clk_init_data){ 1947 + .hw.init = &(const struct clk_init_data) { 1948 1948 .name = "gcc_qupv3_wrap1_s5_clk", 1949 - .parent_hws = (const struct clk_hw*[]){ 1949 + .parent_hws = (const struct clk_hw*[]) { 1950 1950 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 1951 1951 }, 1952 1952 .num_parents = 1, ··· 1962 1962 .clkr = { 1963 1963 .enable_reg = 0x5200c, 1964 1964 .enable_mask = BIT(28), 1965 - .hw.init = &(struct clk_init_data){ 1965 + .hw.init = &(const struct clk_init_data) { 1966 1966 .name = "gcc_qupv3_wrap1_s6_clk", 1967 - .parent_hws = (const struct clk_hw*[]){ 1967 + .parent_hws = (const struct clk_hw*[]) { 1968 1968 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 1969 1969 }, 1970 1970 .num_parents = 1, ··· 1980 1980 .clkr = { 1981 1981 .enable_reg = 0x5200c, 1982 1982 .enable_mask = BIT(29), 1983 - .hw.init = &(struct clk_init_data){ 1983 + .hw.init = &(const struct clk_init_data) { 1984 1984 .name = "gcc_qupv3_wrap1_s7_clk", 1985 - .parent_hws = (const struct clk_hw*[]){ 1985 + .parent_hws = (const struct clk_hw*[]) { 1986 1986 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 1987 1987 }, 1988 1988 .num_parents = 1, ··· 1998 1998 .clkr = { 1999 1999 .enable_reg = 0x5200c, 2000 2000 .enable_mask = BIT(6), 2001 - .hw.init = &(struct clk_init_data){ 2001 + .hw.init = &(const struct clk_init_data) { 2002 2002 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2003 2003 .ops = &clk_branch2_ops, 2004 2004 }, ··· 2013 2013 .clkr = { 2014 2014 .enable_reg = 0x5200c, 2015 2015 .enable_mask = BIT(7), 2016 - .hw.init = &(struct clk_init_data){ 2016 + .hw.init = &(const struct clk_init_data) { 2017 2017 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2018 2018 .ops = &clk_branch2_ops, 2019 2019 }, ··· 2026 2026 .clkr = { 2027 2027 .enable_reg = 0x5200c, 2028 2028 .enable_mask = BIT(20), 2029 - .hw.init = &(struct clk_init_data){ 2029 + .hw.init = &(const struct clk_init_data) { 2030 2030 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2031 2031 .ops = &clk_branch2_ops, 2032 2032 }, ··· 2041 2041 .clkr = { 2042 2042 .enable_reg = 0x5200c, 2043 2043 .enable_mask = BIT(21), 2044 - .hw.init = &(struct clk_init_data){ 2044 + .hw.init = &(const struct clk_init_data) { 2045 2045 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2046 2046 .ops = &clk_branch2_ops, 2047 2047 }, ··· 2054 2054 .clkr = { 2055 2055 .enable_reg = 0x12008, 2056 2056 .enable_mask = BIT(0), 2057 - .hw.init = &(struct clk_init_data){ 2057 + .hw.init = &(const struct clk_init_data) { 2058 2058 .name = "gcc_sdcc1_ahb_clk", 2059 2059 .ops = &clk_branch2_ops, 2060 2060 }, ··· 2067 2067 .clkr = { 2068 2068 .enable_reg = 0x1200c, 2069 2069 .enable_mask = BIT(0), 2070 - .hw.init = &(struct clk_init_data){ 2070 + .hw.init = &(const struct clk_init_data) { 2071 2071 .name = "gcc_sdcc1_apps_clk", 2072 - .parent_hws = (const struct clk_hw*[]){ 2072 + .parent_hws = (const struct clk_hw*[]) { 2073 2073 &gcc_sdcc1_apps_clk_src.clkr.hw, 2074 2074 }, 2075 2075 .num_parents = 1, ··· 2085 2085 .clkr = { 2086 2086 .enable_reg = 0x12040, 2087 2087 .enable_mask = BIT(0), 2088 - .hw.init = &(struct clk_init_data){ 2088 + .hw.init = &(const struct clk_init_data) { 2089 2089 .name = "gcc_sdcc1_ice_core_clk", 2090 - .parent_hws = (const struct clk_hw*[]){ 2090 + .parent_hws = (const struct clk_hw*[]) { 2091 2091 &gcc_sdcc1_ice_core_clk_src.clkr.hw, 2092 2092 }, 2093 2093 .num_parents = 1, ··· 2103 2103 .clkr = { 2104 2104 .enable_reg = 0x14008, 2105 2105 .enable_mask = BIT(0), 2106 - .hw.init = &(struct clk_init_data){ 2106 + .hw.init = &(const struct clk_init_data) { 2107 2107 .name = "gcc_sdcc2_ahb_clk", 2108 2108 .ops = &clk_branch2_ops, 2109 2109 }, ··· 2116 2116 .clkr = { 2117 2117 .enable_reg = 0x14004, 2118 2118 .enable_mask = BIT(0), 2119 - .hw.init = &(struct clk_init_data){ 2119 + .hw.init = &(const struct clk_init_data) { 2120 2120 .name = "gcc_sdcc2_apps_clk", 2121 - .parent_hws = (const struct clk_hw*[]){ 2121 + .parent_hws = (const struct clk_hw*[]) { 2122 2122 &gcc_sdcc2_apps_clk_src.clkr.hw, 2123 2123 }, 2124 2124 .num_parents = 1, ··· 2134 2134 .clkr = { 2135 2135 .enable_reg = 0x16008, 2136 2136 .enable_mask = BIT(0), 2137 - .hw.init = &(struct clk_init_data){ 2137 + .hw.init = &(const struct clk_init_data) { 2138 2138 .name = "gcc_sdcc4_ahb_clk", 2139 2139 .ops = &clk_branch2_ops, 2140 2140 }, ··· 2147 2147 .clkr = { 2148 2148 .enable_reg = 0x16004, 2149 2149 .enable_mask = BIT(0), 2150 - .hw.init = &(struct clk_init_data){ 2150 + .hw.init = &(const struct clk_init_data) { 2151 2151 .name = "gcc_sdcc4_apps_clk", 2152 - .parent_hws = (const struct clk_hw*[]){ 2152 + .parent_hws = (const struct clk_hw*[]) { 2153 2153 &gcc_sdcc4_apps_clk_src.clkr.hw, 2154 2154 }, 2155 2155 .num_parents = 1, ··· 2165 2165 .clkr = { 2166 2166 .enable_reg = 0x52004, 2167 2167 .enable_mask = BIT(0), 2168 - .hw.init = &(struct clk_init_data){ 2168 + .hw.init = &(const struct clk_init_data) { 2169 2169 .name = "gcc_sys_noc_cpuss_ahb_clk", 2170 - .parent_hws = (const struct clk_hw*[]){ 2170 + .parent_hws = (const struct clk_hw*[]) { 2171 2171 &gcc_cpuss_ahb_clk_src.clkr.hw, 2172 2172 }, 2173 2173 .num_parents = 1, ··· 2183 2183 .clkr = { 2184 2184 .enable_reg = 0x36004, 2185 2185 .enable_mask = BIT(0), 2186 - .hw.init = &(struct clk_init_data){ 2186 + .hw.init = &(const struct clk_init_data) { 2187 2187 .name = "gcc_tsif_ahb_clk", 2188 2188 .ops = &clk_branch2_ops, 2189 2189 }, ··· 2196 2196 .clkr = { 2197 2197 .enable_reg = 0x3600c, 2198 2198 .enable_mask = BIT(0), 2199 - .hw.init = &(struct clk_init_data){ 2199 + .hw.init = &(const struct clk_init_data) { 2200 2200 .name = "gcc_tsif_inactivity_timers_clk", 2201 2201 .ops = &clk_branch2_ops, 2202 2202 }, ··· 2209 2209 .clkr = { 2210 2210 .enable_reg = 0x36008, 2211 2211 .enable_mask = BIT(0), 2212 - .hw.init = &(struct clk_init_data){ 2212 + .hw.init = &(const struct clk_init_data) { 2213 2213 .name = "gcc_tsif_ref_clk", 2214 - .parent_hws = (const struct clk_hw*[]){ 2214 + .parent_hws = (const struct clk_hw*[]) { 2215 2215 &gcc_tsif_ref_clk_src.clkr.hw, 2216 2216 }, 2217 2217 .num_parents = 1, ··· 2227 2227 .clkr = { 2228 2228 .enable_reg = 0x8c000, 2229 2229 .enable_mask = BIT(0), 2230 - .hw.init = &(struct clk_init_data){ 2230 + .hw.init = &(const struct clk_init_data) { 2231 2231 .name = "gcc_ufs_mem_clkref_clk", 2232 2232 .ops = &clk_branch2_ops, 2233 2233 }, ··· 2242 2242 .clkr = { 2243 2243 .enable_reg = 0x77014, 2244 2244 .enable_mask = BIT(0), 2245 - .hw.init = &(struct clk_init_data){ 2245 + .hw.init = &(const struct clk_init_data) { 2246 2246 .name = "gcc_ufs_phy_ahb_clk", 2247 2247 .ops = &clk_branch2_ops, 2248 2248 }, ··· 2257 2257 .clkr = { 2258 2258 .enable_reg = 0x77038, 2259 2259 .enable_mask = BIT(0), 2260 - .hw.init = &(struct clk_init_data){ 2260 + .hw.init = &(const struct clk_init_data) { 2261 2261 .name = "gcc_ufs_phy_axi_clk", 2262 - .parent_hws = (const struct clk_hw*[]){ 2262 + .parent_hws = (const struct clk_hw*[]) { 2263 2263 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2264 2264 }, 2265 2265 .num_parents = 1, ··· 2277 2277 .clkr = { 2278 2278 .enable_reg = 0x77038, 2279 2279 .enable_mask = BIT(1), 2280 - .hw.init = &(struct clk_init_data){ 2280 + .hw.init = &(const struct clk_init_data) { 2281 2281 .name = "gcc_ufs_phy_axi_hw_ctl_clk", 2282 - .parent_hws = (const struct clk_hw*[]){ 2282 + .parent_hws = (const struct clk_hw*[]) { 2283 2283 &gcc_ufs_phy_axi_clk.clkr.hw, 2284 2284 }, 2285 2285 .num_parents = 1, ··· 2297 2297 .clkr = { 2298 2298 .enable_reg = 0x77090, 2299 2299 .enable_mask = BIT(0), 2300 - .hw.init = &(struct clk_init_data){ 2300 + .hw.init = &(const struct clk_init_data) { 2301 2301 .name = "gcc_ufs_phy_ice_core_clk", 2302 - .parent_hws = (const struct clk_hw*[]){ 2302 + .parent_hws = (const struct clk_hw*[]) { 2303 2303 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2304 2304 }, 2305 2305 .num_parents = 1, ··· 2317 2317 .clkr = { 2318 2318 .enable_reg = 0x77090, 2319 2319 .enable_mask = BIT(1), 2320 - .hw.init = &(struct clk_init_data){ 2320 + .hw.init = &(const struct clk_init_data) { 2321 2321 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", 2322 - .parent_hws = (const struct clk_hw*[]){ 2322 + .parent_hws = (const struct clk_hw*[]) { 2323 2323 &gcc_ufs_phy_ice_core_clk.clkr.hw, 2324 2324 }, 2325 2325 .num_parents = 1, ··· 2337 2337 .clkr = { 2338 2338 .enable_reg = 0x77094, 2339 2339 .enable_mask = BIT(0), 2340 - .hw.init = &(struct clk_init_data){ 2340 + .hw.init = &(const struct clk_init_data) { 2341 2341 .name = "gcc_ufs_phy_phy_aux_clk", 2342 - .parent_hws = (const struct clk_hw*[]){ 2342 + .parent_hws = (const struct clk_hw*[]) { 2343 2343 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2344 2344 }, 2345 2345 .num_parents = 1, ··· 2357 2357 .clkr = { 2358 2358 .enable_reg = 0x77094, 2359 2359 .enable_mask = BIT(1), 2360 - .hw.init = &(struct clk_init_data){ 2360 + .hw.init = &(const struct clk_init_data) { 2361 2361 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", 2362 - .parent_hws = (const struct clk_hw*[]){ 2362 + .parent_hws = (const struct clk_hw*[]) { 2363 2363 &gcc_ufs_phy_phy_aux_clk.clkr.hw, 2364 2364 }, 2365 2365 .num_parents = 1, ··· 2375 2375 .clkr = { 2376 2376 .enable_reg = 0x7701c, 2377 2377 .enable_mask = BIT(0), 2378 - .hw.init = &(struct clk_init_data){ 2378 + .hw.init = &(const struct clk_init_data) { 2379 2379 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2380 2380 .ops = &clk_branch2_ops, 2381 2381 }, ··· 2388 2388 .clkr = { 2389 2389 .enable_reg = 0x77018, 2390 2390 .enable_mask = BIT(0), 2391 - .hw.init = &(struct clk_init_data){ 2391 + .hw.init = &(const struct clk_init_data) { 2392 2392 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2393 2393 .ops = &clk_branch2_ops, 2394 2394 }, ··· 2403 2403 .clkr = { 2404 2404 .enable_reg = 0x7708c, 2405 2405 .enable_mask = BIT(0), 2406 - .hw.init = &(struct clk_init_data){ 2406 + .hw.init = &(const struct clk_init_data) { 2407 2407 .name = "gcc_ufs_phy_unipro_core_clk", 2408 - .parent_hws = (const struct clk_hw*[]){ 2408 + .parent_hws = (const struct clk_hw*[]) { 2409 2409 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2410 2410 }, 2411 2411 .num_parents = 1, ··· 2423 2423 .clkr = { 2424 2424 .enable_reg = 0x7708c, 2425 2425 .enable_mask = BIT(1), 2426 - .hw.init = &(struct clk_init_data){ 2426 + .hw.init = &(const struct clk_init_data) { 2427 2427 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", 2428 - .parent_hws = (const struct clk_hw*[]){ 2428 + .parent_hws = (const struct clk_hw*[]) { 2429 2429 &gcc_ufs_phy_unipro_core_clk.clkr.hw, 2430 2430 }, 2431 2431 .num_parents = 1, ··· 2441 2441 .clkr = { 2442 2442 .enable_reg = 0xf010, 2443 2443 .enable_mask = BIT(0), 2444 - .hw.init = &(struct clk_init_data){ 2444 + .hw.init = &(const struct clk_init_data) { 2445 2445 .name = "gcc_usb30_prim_master_clk", 2446 - .parent_hws = (const struct clk_hw*[]){ 2446 + .parent_hws = (const struct clk_hw*[]) { 2447 2447 &gcc_usb30_prim_master_clk_src.clkr.hw, 2448 2448 }, 2449 2449 .num_parents = 1, ··· 2459 2459 .clkr = { 2460 2460 .enable_reg = 0xf018, 2461 2461 .enable_mask = BIT(0), 2462 - .hw.init = &(struct clk_init_data){ 2462 + .hw.init = &(const struct clk_init_data) { 2463 2463 .name = "gcc_usb30_prim_mock_utmi_clk", 2464 - .parent_hws = (const struct clk_hw*[]){ 2464 + .parent_hws = (const struct clk_hw*[]) { 2465 2465 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 2466 2466 }, 2467 2467 .num_parents = 1, ··· 2477 2477 .clkr = { 2478 2478 .enable_reg = 0xf014, 2479 2479 .enable_mask = BIT(0), 2480 - .hw.init = &(struct clk_init_data){ 2480 + .hw.init = &(const struct clk_init_data) { 2481 2481 .name = "gcc_usb30_prim_sleep_clk", 2482 2482 .ops = &clk_branch2_ops, 2483 2483 }, ··· 2490 2490 .clkr = { 2491 2491 .enable_reg = 0x8c010, 2492 2492 .enable_mask = BIT(0), 2493 - .hw.init = &(struct clk_init_data){ 2493 + .hw.init = &(const struct clk_init_data) { 2494 2494 .name = "gcc_usb3_prim_clkref_clk", 2495 2495 .ops = &clk_branch2_ops, 2496 2496 }, ··· 2503 2503 .clkr = { 2504 2504 .enable_reg = 0xf050, 2505 2505 .enable_mask = BIT(0), 2506 - .hw.init = &(struct clk_init_data){ 2506 + .hw.init = &(const struct clk_init_data) { 2507 2507 .name = "gcc_usb3_prim_phy_aux_clk", 2508 - .parent_hws = (const struct clk_hw*[]){ 2508 + .parent_hws = (const struct clk_hw*[]) { 2509 2509 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2510 2510 }, 2511 2511 .num_parents = 1, ··· 2521 2521 .clkr = { 2522 2522 .enable_reg = 0xf054, 2523 2523 .enable_mask = BIT(0), 2524 - .hw.init = &(struct clk_init_data){ 2524 + .hw.init = &(const struct clk_init_data) { 2525 2525 .name = "gcc_usb3_prim_phy_com_aux_clk", 2526 - .parent_hws = (const struct clk_hw*[]){ 2526 + .parent_hws = (const struct clk_hw*[]) { 2527 2527 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2528 2528 }, 2529 2529 .num_parents = 1, ··· 2538 2538 .clkr = { 2539 2539 .enable_reg = 0xf058, 2540 2540 .enable_mask = BIT(0), 2541 - .hw.init = &(struct clk_init_data){ 2541 + .hw.init = &(const struct clk_init_data) { 2542 2542 .name = "gcc_usb3_prim_phy_pipe_clk", 2543 2543 .ops = &clk_branch2_ops, 2544 2544 }, ··· 2553 2553 .clkr = { 2554 2554 .enable_reg = 0x6a004, 2555 2555 .enable_mask = BIT(0), 2556 - .hw.init = &(struct clk_init_data){ 2556 + .hw.init = &(const struct clk_init_data) { 2557 2557 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2558 2558 .ops = &clk_branch2_ops, 2559 2559 }, ··· 2566 2566 .clkr = { 2567 2567 .enable_reg = 0x7a00c, 2568 2568 .enable_mask = BIT(0), 2569 - .hw.init = &(struct clk_init_data){ 2569 + .hw.init = &(const struct clk_init_data) { 2570 2570 .name = "gcc_vdda_vs_clk", 2571 - .parent_hws = (const struct clk_hw*[]){ 2571 + .parent_hws = (const struct clk_hw*[]) { 2572 2572 &gcc_vsensor_clk_src.clkr.hw, 2573 2573 }, 2574 2574 .num_parents = 1, ··· 2584 2584 .clkr = { 2585 2585 .enable_reg = 0x7a004, 2586 2586 .enable_mask = BIT(0), 2587 - .hw.init = &(struct clk_init_data){ 2587 + .hw.init = &(const struct clk_init_data) { 2588 2588 .name = "gcc_vddcx_vs_clk", 2589 - .parent_hws = (const struct clk_hw*[]){ 2589 + .parent_hws = (const struct clk_hw*[]) { 2590 2590 &gcc_vsensor_clk_src.clkr.hw, 2591 2591 }, 2592 2592 .num_parents = 1, ··· 2602 2602 .clkr = { 2603 2603 .enable_reg = 0x7a008, 2604 2604 .enable_mask = BIT(0), 2605 - .hw.init = &(struct clk_init_data){ 2605 + .hw.init = &(const struct clk_init_data) { 2606 2606 .name = "gcc_vddmx_vs_clk", 2607 - .parent_hws = (const struct clk_hw*[]){ 2607 + .parent_hws = (const struct clk_hw*[]) { 2608 2608 &gcc_vsensor_clk_src.clkr.hw, 2609 2609 }, 2610 2610 .num_parents = 1, ··· 2621 2621 .clkr = { 2622 2622 .enable_reg = 0xb01c, 2623 2623 .enable_mask = BIT(0), 2624 - .hw.init = &(struct clk_init_data){ 2624 + .hw.init = &(const struct clk_init_data) { 2625 2625 .name = "gcc_video_axi_clk", 2626 2626 .ops = &clk_branch2_ops, 2627 2627 }, ··· 2636 2636 .clkr = { 2637 2637 .enable_reg = 0x7a014, 2638 2638 .enable_mask = BIT(0), 2639 - .hw.init = &(struct clk_init_data){ 2639 + .hw.init = &(const struct clk_init_data) { 2640 2640 .name = "gcc_vs_ctrl_ahb_clk", 2641 2641 .ops = &clk_branch2_ops, 2642 2642 }, ··· 2649 2649 .clkr = { 2650 2650 .enable_reg = 0x7a010, 2651 2651 .enable_mask = BIT(0), 2652 - .hw.init = &(struct clk_init_data){ 2652 + .hw.init = &(const struct clk_init_data) { 2653 2653 .name = "gcc_vs_ctrl_clk", 2654 - .parent_hws = (const struct clk_hw*[]){ 2654 + .parent_hws = (const struct clk_hw*[]) { 2655 2655 &gcc_vs_ctrl_clk_src.clkr.hw, 2656 2656 }, 2657 2657 .num_parents = 1,