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Merge tag 'cxl-fixes-6.9-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl

Pull cxl fix from Dave Jiang:
"Add missing RCH support for endpoint access_coordinate calculation.

A late bug was reported by Robert Richter that the Restricted CXL Host
(RCH) support was missing in the CXL endpoint access_coordinate
calculation.

The missing support causes the topology iterator to stumble over a
NULL pointer and triggers a kernel OOPS on a platform with CXL 1.1
support.

The fix bypasses RCH topology as the access_coordinate calculation is
not necessary since RCH does not support hotplug and the memory region
exported should be covered by the HMAT table already.

A unit test is also added to cxl_test to check against future
regressions on the topology iterator"

* tag 'cxl-fixes-6.9-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl:
cxl: Fix cxl_endpoint_get_perf_coordinate() support for RCH

+21 -1
+14 -1
drivers/cxl/core/port.c
··· 2184 2184 int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, 2185 2185 struct access_coordinate *coord) 2186 2186 { 2187 + struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev); 2187 2188 struct access_coordinate c[] = { 2188 2189 { 2189 2190 .read_bandwidth = UINT_MAX, ··· 2198 2197 struct cxl_port *iter = port; 2199 2198 struct cxl_dport *dport; 2200 2199 struct pci_dev *pdev; 2200 + struct device *dev; 2201 2201 unsigned int bw; 2202 2202 bool is_cxl_root; 2203 2203 2204 2204 if (!is_cxl_endpoint(port)) 2205 2205 return -EINVAL; 2206 + 2207 + /* 2208 + * Skip calculation for RCD. Expectation is HMAT already covers RCD case 2209 + * since RCH does not support hotplug. 2210 + */ 2211 + if (cxlmd->cxlds->rcd) 2212 + return 0; 2206 2213 2207 2214 /* 2208 2215 * Exit the loop when the parent port of the current iter port is cxl ··· 2241 2232 return -EINVAL; 2242 2233 cxl_coordinates_combine(c, c, dport->coord); 2243 2234 2235 + dev = port->uport_dev->parent; 2236 + if (!dev_is_pci(dev)) 2237 + return -ENODEV; 2238 + 2244 2239 /* Get the calculated PCI paths bandwidth */ 2245 - pdev = to_pci_dev(port->uport_dev->parent); 2240 + pdev = to_pci_dev(dev); 2246 2241 bw = pcie_bandwidth_available(pdev, NULL, NULL, NULL); 2247 2242 if (bw == 0) 2248 2243 return -ENXIO;
+7
tools/testing/cxl/test/cxl.c
··· 1001 1001 struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev); 1002 1002 struct cxl_dev_state *cxlds = cxlmd->cxlds; 1003 1003 struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); 1004 + struct access_coordinate ep_c[ACCESS_COORDINATE_MAX]; 1004 1005 struct range pmem_range = { 1005 1006 .start = cxlds->pmem_res.start, 1006 1007 .end = cxlds->pmem_res.end, ··· 1021 1020 dpa_perf_setup(port, &pmem_range, &mds->pmem_perf); 1022 1021 1023 1022 cxl_memdev_update_perf(cxlmd); 1023 + 1024 + /* 1025 + * This function is here to only test the topology iterator. It serves 1026 + * no other purpose. 1027 + */ 1028 + cxl_endpoint_get_perf_coordinates(port, ep_c); 1024 1029 } 1025 1030 1026 1031 static struct cxl_mock_ops cxl_mock_ops = {