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dt-bindings: display: mediatek: split: add compatible for MT8195

Add compatible string and GCE property for MT8195 SPLIT, of
which is operated by MDP3.

Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

authored by

Moudy Ho and committed by
AngeloGioacchino Del Regno
739058a9 fe49f432

+27
+27
Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
··· 23 23 oneOf: 24 24 - enum: 25 25 - mediatek,mt8173-disp-split 26 + - mediatek,mt8195-mdp3-split 26 27 - items: 27 28 - const: mediatek,mt6795-disp-split 28 29 - const: mediatek,mt8173-disp-split ··· 39 38 the power controller specified by phandle. See 40 39 Documentation/devicetree/bindings/power/power-domain.yaml for details. 41 40 41 + mediatek,gce-client-reg: 42 + description: 43 + The register of display function block to be set by gce. There are 4 arguments, 44 + such as gce node, subsys id, offset and register size. The subsys id that is 45 + mapping to the register of display function blocks is defined in the gce header 46 + include/dt-bindings/gce/<chip>-gce.h of each chips. 47 + $ref: /schemas/types.yaml#/definitions/phandle-array 48 + items: 49 + items: 50 + - description: phandle of GCE 51 + - description: GCE subsys id 52 + - description: register offset 53 + - description: register size 54 + maxItems: 1 55 + 42 56 clocks: 43 57 items: 44 58 - description: SPLIT Clock ··· 63 47 - reg 64 48 - power-domains 65 49 - clocks 50 + 51 + allOf: 52 + - if: 53 + properties: 54 + compatible: 55 + contains: 56 + const: mediatek,mt8195-mdp3-split 57 + 58 + then: 59 + required: 60 + - mediatek,gce-client-reg 66 61 67 62 additionalProperties: false 68 63