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Merge branch 'net-pse-pd-tps23881-reset-gpio-support'

Kyle Swenson says:

====================
net: pse-pd: tps23881: Reset GPIO support

On some boards, the TPS2388x's reset line (active low) is pulled low to
keep the chip in reset until the SoC pulls the device out of reset.
This series updates the device-tree binding for the tps23881 and then
adds support for the reset gpio handling in the tps23881 driver.

v1: https://lore.kernel.org/20240819190151.93253-1-kyle.swenson@est.tech
====================

Link: https://patch.msgid.link/20240822220100.3030184-1-kyle.swenson@est.tech
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski 73b22ba0 d2ab3bb8

+24
+3
Documentation/devicetree/bindings/net/pse-pd/ti,tps23881.yaml
··· 23 23 '#pse-cells': 24 24 const: 1 25 25 26 + reset-gpios: 27 + maxItems: 1 28 + 26 29 channels: 27 30 description: each set of 8 ports can be assigned to one physical 28 31 channels or two for PoE4. This parameter describes the configuration
+21
drivers/net/pse-pd/tps23881.c
··· 8 8 #include <linux/bitfield.h> 9 9 #include <linux/delay.h> 10 10 #include <linux/firmware.h> 11 + #include <linux/gpio/consumer.h> 11 12 #include <linux/i2c.h> 12 13 #include <linux/module.h> 13 14 #include <linux/of.h> ··· 738 737 { 739 738 struct device *dev = &client->dev; 740 739 struct tps23881_priv *priv; 740 + struct gpio_desc *reset; 741 741 int ret; 742 742 u8 val; 743 743 ··· 750 748 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 751 749 if (!priv) 752 750 return -ENOMEM; 751 + 752 + reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 753 + if (IS_ERR(reset)) 754 + return dev_err_probe(&client->dev, PTR_ERR(reset), "Failed to get reset GPIO\n"); 755 + 756 + if (reset) { 757 + /* TPS23880 datasheet (Rev G) indicates minimum reset pulse is 5us */ 758 + usleep_range(5, 10); 759 + gpiod_set_value_cansleep(reset, 0); /* De-assert reset */ 760 + 761 + /* TPS23880 datasheet indicates the minimum time after power on reset 762 + * should be 20ms, but the document describing how to load SRAM ("How 763 + * to Load TPS2388x SRAM and Parity Code over I2C" (Rev E)) 764 + * indicates we should delay that programming by at least 50ms. So 765 + * we'll wait the entire 50ms here to ensure we're safe to go to the 766 + * SRAM loading proceedure. 767 + */ 768 + msleep(50); 769 + } 753 770 754 771 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_DEVID); 755 772 if (ret < 0)