Merge branch 'pci/resource' · tjh.dev/kernel@73b4779

+1

drivers/pci/Makefile

··· 39 39 obj-$(CONFIG_PCI_DYNAMIC_OF_NODES) += of_property.o 40 40 obj-$(CONFIG_PCI_NPEM) += npem.o 41 41 obj-$(CONFIG_PCIE_TPH) += tph.o 42 + obj-$(CONFIG_CARDBUS) += setup-cardbus.o 42 43 43 44 # Endpoint library must be initialized before its users 44 45 obj-$(CONFIG_PCI_ENDPOINT) += endpoint/

+1 -1

drivers/pci/pci-sysfs.c

··· 181 181 struct resource zerores = {}; 182 182 183 183 /* For backwards compatibility */ 184 - if (i >= PCI_BRIDGE_RESOURCES && i <= PCI_BRIDGE_RESOURCE_END && 184 + if (pci_resource_is_bridge_win(i) && 185 185 res->flags & (IORESOURCE_UNSET | IORESOURCE_DISABLED)) 186 186 res = &zerores; 187 187

+3 -11

drivers/pci/pci.c

··· 99 99 int pci_domains_supported = 1; 100 100 #endif 101 101 102 - #define DEFAULT_CARDBUS_IO_SIZE (256) 103 - #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) 104 - /* pci=cbmemsize=nnM,cbiosize=nn can override this */ 105 - unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; 106 - unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; 107 - 108 102 #define DEFAULT_HOTPLUG_IO_SIZE (256) 109 103 #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024) 110 104 #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024) ··· 6633 6639 if (k) 6634 6640 *k++ = 0; 6635 6641 if (*str && (str = pcibios_setup(str)) && *str) { 6636 - if (!strcmp(str, "nomsi")) { 6642 + if (!pci_setup_cardbus(str)) { 6643 + /* Function handled the parameters */ 6644 + } else if (!strcmp(str, "nomsi")) { 6637 6645 pci_no_msi(); 6638 6646 } else if (!strncmp(str, "noats", 5)) { 6639 6647 pr_info("PCIe: ATS is disabled\n"); ··· 6654 6658 pcie_ari_disabled = true; 6655 6659 } else if (!strncmp(str, "notph", 5)) { 6656 6660 pci_no_tph(); 6657 - } else if (!strncmp(str, "cbiosize=", 9)) { 6658 - pci_cardbus_io_size = memparse(str + 9, &str); 6659 - } else if (!strncmp(str, "cbmemsize=", 10)) { 6660 - pci_cardbus_mem_size = memparse(str + 10, &str); 6661 6661 } else if (!strncmp(str, "resource_alignment=", 19)) { 6662 6662 resource_alignment_param = str + 19; 6663 6663 } else if (!strncmp(str, "ecrc=", 5)) {

+45 -4

drivers/pci/pci.h

··· 245 245 void pci_pm_power_up_and_verify_state(struct pci_dev *pci_dev); 246 246 void pci_pm_init(struct pci_dev *dev); 247 247 void pci_ea_init(struct pci_dev *dev); 248 + bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub); 248 249 void pci_msi_init(struct pci_dev *dev); 249 250 void pci_msix_init(struct pci_dev *dev); 250 251 bool pci_bridge_d3_possible(struct pci_dev *dev); ··· 380 379 extern unsigned long pci_hotplug_mmio_size; 381 380 extern unsigned long pci_hotplug_mmio_pref_size; 382 381 extern unsigned long pci_hotplug_bus_size; 383 - extern unsigned long pci_cardbus_io_size; 384 - extern unsigned long pci_cardbus_mem_size; 382 + 383 + static inline bool pci_is_cardbus_bridge(struct pci_dev *dev) 384 + { 385 + return dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 386 + } 387 + #ifdef CONFIG_CARDBUS 388 + unsigned long pci_cardbus_resource_alignment(struct resource *res); 389 + int pci_bus_size_cardbus_bridge(struct pci_bus *bus, 390 + struct list_head *realloc_head); 391 + int pci_cardbus_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 392 + u32 buses, int max, 393 + unsigned int available_buses, int pass); 394 + int pci_setup_cardbus(char *str); 395 + 396 + #else 397 + static inline unsigned long pci_cardbus_resource_alignment(struct resource *res) 398 + { 399 + return 0; 400 + } 401 + static inline int pci_bus_size_cardbus_bridge(struct pci_bus *bus, 402 + struct list_head *realloc_head) 403 + { 404 + return -EOPNOTSUPP; 405 + } 406 + static inline int pci_cardbus_scan_bridge_extend(struct pci_bus *bus, 407 + struct pci_dev *dev, 408 + u32 buses, int max, 409 + unsigned int available_buses, 410 + int pass) 411 + { 412 + return max; 413 + } 414 + static inline int pci_setup_cardbus(char *str) { return -ENOENT; } 415 + #endif /* CONFIG_CARDBUS */ 385 416 386 417 /** 387 418 * pci_match_one_device - Tell if a PCI device structure has a matching ··· 476 443 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 477 444 struct resource *res, unsigned int reg, u32 *sizes); 478 445 void pci_configure_ari(struct pci_dev *dev); 446 + 447 + int pci_dev_res_add_to_list(struct list_head *head, struct pci_dev *dev, 448 + struct resource *res, resource_size_t add_size, 449 + resource_size_t min_align); 479 450 void __pci_bus_size_bridges(struct pci_bus *bus, 480 451 struct list_head *realloc_head); 481 452 void __pci_bus_assign_resources(const struct pci_bus *bus, ··· 492 455 493 456 const char *pci_resource_name(struct pci_dev *dev, unsigned int i); 494 457 bool pci_resource_is_optional(const struct pci_dev *dev, int resno); 458 + static inline bool pci_resource_is_bridge_win(int resno) 459 + { 460 + return resno >= PCI_BRIDGE_RESOURCES && 461 + resno <= PCI_BRIDGE_RESOURCE_END; 462 + } 495 463 496 464 /** 497 465 * pci_resource_num - Reverse lookup resource number from device resources ··· 520 478 return resno; 521 479 } 522 480 481 + void pbus_validate_busn(struct pci_bus *bus); 523 482 struct resource *pbus_select_window(struct pci_bus *bus, 524 483 const struct resource *res); 525 484 void pci_reassigndev_resource_alignment(struct pci_dev *dev); ··· 969 926 static inline void pci_suspend_ptm(struct pci_dev *dev) { } 970 927 static inline void pci_resume_ptm(struct pci_dev *dev) { } 971 928 #endif 972 - 973 - unsigned long pci_cardbus_resource_alignment(struct resource *); 974 929 975 930 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 976 931 struct resource *res)

+50 -84

drivers/pci/probe.c

··· 14 14 #include <linux/platform_device.h> 15 15 #include <linux/pci_hotplug.h> 16 16 #include <linux/slab.h> 17 + #include <linux/sprintf.h> 17 18 #include <linux/module.h> 18 19 #include <linux/cpumask.h> 19 20 #include <linux/aer.h> ··· 24 23 #include <linux/pm_runtime.h> 25 24 #include <linux/bitfield.h> 26 25 #include "pci.h" 27 - 28 - #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 29 - #define CARDBUS_RESERVE_BUSNR 3 30 26 31 27 static struct resource busn_resource = { 32 28 .name = "PCI busn", ··· 285 287 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) 286 288 && sz64 > 0x100000000ULL) { 287 289 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; 288 - res->start = 0; 289 - res->end = 0; 290 + resource_set_range(res, 0, 0); 290 291 pci_err(dev, "%s: can't handle BAR larger than 4GB (size %#010llx)\n", 291 292 res_name, (unsigned long long)sz64); 292 293 goto out; ··· 294 297 if ((sizeof(pci_bus_addr_t) < 8) && l) { 295 298 /* Above 32-bit boundary; try to reallocate */ 296 299 res->flags |= IORESOURCE_UNSET; 297 - res->start = 0; 298 - res->end = sz64 - 1; 300 + resource_set_range(res, 0, sz64); 299 301 pci_info(dev, "%s: can't handle BAR above 4GB (bus address %#010llx)\n", 300 302 res_name, (unsigned long long)l64); 301 303 goto out; ··· 521 525 522 526 pci_read_config_dword(bridge, PCI_PRIMARY_BUS, &buses); 523 527 res.flags = IORESOURCE_BUS; 524 - res.start = (buses >> 8) & 0xff; 525 - res.end = (buses >> 16) & 0xff; 528 + res.start = FIELD_GET(PCI_SECONDARY_BUS_MASK, buses); 529 + res.end = FIELD_GET(PCI_SUBORDINATE_BUS_MASK, buses); 526 530 pci_info(bridge, "PCI bridge to %pR%s\n", &res, 527 531 bridge->transparent ? " (subtractive decode)" : ""); 528 532 ··· 1309 1313 1310 1314 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 1311 1315 unsigned int available_buses); 1316 + 1317 + void pbus_validate_busn(struct pci_bus *bus) 1318 + { 1319 + struct pci_bus *upstream = bus->parent; 1320 + struct pci_dev *bridge = bus->self; 1321 + 1322 + /* Check that all devices are accessible */ 1323 + while (upstream->parent) { 1324 + if ((bus->busn_res.end > upstream->busn_res.end) || 1325 + (bus->number > upstream->busn_res.end) || 1326 + (bus->number < upstream->number) || 1327 + (bus->busn_res.end < upstream->number)) { 1328 + pci_info(bridge, "devices behind bridge are unusable because %pR cannot be assigned for them\n", 1329 + &bus->busn_res); 1330 + break; 1331 + } 1332 + upstream = upstream->parent; 1333 + } 1334 + } 1335 + 1312 1336 /** 1313 1337 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus 1314 1338 * numbers from EA capability. ··· 1340 1324 * and subordinate bus numbers, return true with the bus numbers in @sec 1341 1325 * and @sub. Otherwise return false. 1342 1326 */ 1343 - static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) 1327 + bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) 1344 1328 { 1345 1329 int ea, offset; 1346 1330 u32 dw; ··· 1394 1378 int pass) 1395 1379 { 1396 1380 struct pci_bus *child; 1397 - int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 1398 - u32 buses, i, j = 0; 1381 + u32 buses; 1399 1382 u16 bctl; 1400 1383 u8 primary, secondary, subordinate; 1401 1384 int broken = 0; ··· 1409 1394 pm_runtime_get_sync(&dev->dev); 1410 1395 1411 1396 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 1412 - primary = buses & 0xFF; 1413 - secondary = (buses >> 8) & 0xFF; 1414 - subordinate = (buses >> 16) & 0xFF; 1397 + primary = FIELD_GET(PCI_PRIMARY_BUS_MASK, buses); 1398 + secondary = FIELD_GET(PCI_SECONDARY_BUS_MASK, buses); 1399 + subordinate = FIELD_GET(PCI_SUBORDINATE_BUS_MASK, buses); 1415 1400 1416 1401 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 1417 1402 secondary, subordinate, pass); ··· 1438 1423 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 1439 1424 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 1440 1425 1441 - if ((secondary || subordinate) && !pcibios_assign_all_busses() && 1442 - !is_cardbus && !broken) { 1426 + if (pci_is_cardbus_bridge(dev)) { 1427 + max = pci_cardbus_scan_bridge_extend(bus, dev, buses, max, 1428 + available_buses, 1429 + pass); 1430 + goto out; 1431 + } 1432 + 1433 + if ((secondary || subordinate) && 1434 + !pcibios_assign_all_busses() && !broken) { 1443 1435 unsigned int cmax, buses; 1444 1436 1445 1437 /* ··· 1488 1466 * do in the second pass. 1489 1467 */ 1490 1468 if (!pass) { 1491 - if (pcibios_assign_all_busses() || broken || is_cardbus) 1469 + if (pcibios_assign_all_busses() || broken) 1492 1470 1493 1471 /* 1494 1472 * Temporarily disable forwarding of the ··· 1499 1477 * ranges. 1500 1478 */ 1501 1479 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 1502 - buses & ~0xffffff); 1480 + buses & PCI_SEC_LATENCY_TIMER_MASK); 1503 1481 goto out; 1504 1482 } 1505 1483 ··· 1530 1508 if (available_buses) 1531 1509 available_buses--; 1532 1510 1533 - buses = (buses & 0xff000000) 1534 - | ((unsigned int)(child->primary) << 0) 1535 - | ((unsigned int)(child->busn_res.start) << 8) 1536 - | ((unsigned int)(child->busn_res.end) << 16); 1537 - 1538 - /* 1539 - * yenta.c forces a secondary latency timer of 176. 1540 - * Copy that behaviour here. 1541 - */ 1542 - if (is_cardbus) { 1543 - buses &= ~0xff000000; 1544 - buses |= CARDBUS_LATENCY_TIMER << 24; 1545 - } 1511 + buses = (buses & PCI_SEC_LATENCY_TIMER_MASK) | 1512 + FIELD_PREP(PCI_PRIMARY_BUS_MASK, child->primary) | 1513 + FIELD_PREP(PCI_SECONDARY_BUS_MASK, child->busn_res.start) | 1514 + FIELD_PREP(PCI_SUBORDINATE_BUS_MASK, child->busn_res.end); 1546 1515 1547 1516 /* We need to blast all three values with a single write */ 1548 1517 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 1549 1518 1550 - if (!is_cardbus) { 1551 - child->bridge_ctl = bctl; 1552 - max = pci_scan_child_bus_extend(child, available_buses); 1553 - } else { 1554 - 1555 - /* 1556 - * For CardBus bridges, we leave 4 bus numbers as 1557 - * cards with a PCI-to-PCI bridge can be inserted 1558 - * later. 1559 - */ 1560 - for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { 1561 - struct pci_bus *parent = bus; 1562 - if (pci_find_bus(pci_domain_nr(bus), 1563 - max+i+1)) 1564 - break; 1565 - while (parent->parent) { 1566 - if ((!pcibios_assign_all_busses()) && 1567 - (parent->busn_res.end > max) && 1568 - (parent->busn_res.end <= max+i)) { 1569 - j = 1; 1570 - } 1571 - parent = parent->parent; 1572 - } 1573 - if (j) { 1574 - 1575 - /* 1576 - * Often, there are two CardBus 1577 - * bridges -- try to leave one 1578 - * valid bus number for each one. 1579 - */ 1580 - i /= 2; 1581 - break; 1582 - } 1583 - } 1584 - max += i; 1585 - } 1519 + child->bridge_ctl = bctl; 1520 + max = pci_scan_child_bus_extend(child, available_buses); 1586 1521 1587 1522 /* 1588 1523 * Set subordinate bus number to its real value. ··· 1551 1572 pci_bus_update_busn_res_end(child, max); 1552 1573 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 1553 1574 } 1575 + scnprintf(child->name, sizeof(child->name), "PCI Bus %04x:%02x", 1576 + pci_domain_nr(bus), child->number); 1554 1577 1555 - sprintf(child->name, 1556 - (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 1557 - pci_domain_nr(bus), child->number); 1558 - 1559 - /* Check that all devices are accessible */ 1560 - while (bus->parent) { 1561 - if ((child->busn_res.end > bus->busn_res.end) || 1562 - (child->number > bus->busn_res.end) || 1563 - (child->number < bus->number) || 1564 - (child->busn_res.end < bus->number)) { 1565 - dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", 1566 - &child->busn_res); 1567 - break; 1568 - } 1569 - bus = bus->parent; 1570 - } 1578 + pbus_validate_busn(child); 1571 1579 1572 1580 out: 1573 1581 /* Clear errors in the Secondary Status Register */

+228 -410

drivers/pci/setup-bus.c

··· 14 14 * tighter packing. Prefetchable range support. 15 15 */ 16 16 17 + #include <linux/align.h> 17 18 #include <linux/bitops.h> 18 19 #include <linux/bug.h> 19 20 #include <linux/init.h> 20 21 #include <linux/kernel.h> 22 + #include <linux/minmax.h> 21 23 #include <linux/module.h> 22 24 #include <linux/pci.h> 23 25 #include <linux/errno.h> ··· 49 47 unsigned long flags; 50 48 }; 51 49 52 - static void free_list(struct list_head *head) 50 + static void pci_dev_res_free_list(struct list_head *head) 53 51 { 54 52 struct pci_dev_resource *dev_res, *tmp; 55 53 ··· 60 58 } 61 59 62 60 /** 63 - * add_to_list() - Add a new resource tracker to the list 61 + * pci_dev_res_add_to_list() - Add a new resource tracker to the list 64 62 * @head: Head of the list 65 63 * @dev: Device to which the resource belongs 66 64 * @res: Resource to be tracked 67 65 * @add_size: Additional size to be optionally added to the resource 68 66 * @min_align: Minimum memory window alignment 69 67 */ 70 - static int add_to_list(struct list_head *head, struct pci_dev *dev, 71 - struct resource *res, resource_size_t add_size, 72 - resource_size_t min_align) 68 + int pci_dev_res_add_to_list(struct list_head *head, struct pci_dev *dev, 69 + struct resource *res, resource_size_t add_size, 70 + resource_size_t min_align) 73 71 { 74 72 struct pci_dev_resource *tmp; 75 73 ··· 90 88 return 0; 91 89 } 92 90 93 - static void remove_from_list(struct list_head *head, struct resource *res) 91 + static void pci_dev_res_remove_from_list(struct list_head *head, 92 + struct resource *res) 94 93 { 95 94 struct pci_dev_resource *dev_res, *tmp; 96 95 ··· 126 123 return dev_res ? dev_res->add_size : 0; 127 124 } 128 125 129 - static resource_size_t get_res_add_align(struct list_head *head, 130 - struct resource *res) 131 - { 132 - struct pci_dev_resource *dev_res; 133 - 134 - dev_res = res_to_dev_res(head, res); 135 - return dev_res ? dev_res->min_align : 0; 136 - } 137 - 138 - static void restore_dev_resource(struct pci_dev_resource *dev_res) 126 + static void pci_dev_res_restore(struct pci_dev_resource *dev_res) 139 127 { 140 128 struct resource *res = dev_res->res; 129 + struct pci_dev *dev = dev_res->dev; 130 + int idx = pci_resource_num(dev, res); 131 + const char *res_name = pci_resource_name(dev, idx); 141 132 142 - if (WARN_ON_ONCE(res->parent)) 133 + if (WARN_ON_ONCE(resource_assigned(res))) 143 134 return; 144 135 145 136 res->start = dev_res->start; 146 137 res->end = dev_res->end; 147 138 res->flags = dev_res->flags; 139 + 140 + pci_dbg(dev, "%s %pR: resource restored\n", res_name, res); 148 141 } 149 142 150 143 /* ··· 167 168 if ((r->flags & type_mask) != type) 168 169 continue; 169 170 170 - if (!r->parent) 171 + if (!resource_assigned(r)) 171 172 return r; 172 173 if (!r_assigned) 173 174 r_assigned = r; ··· 270 271 struct resource *pbus_select_window(struct pci_bus *bus, 271 272 const struct resource *res) 272 273 { 273 - if (res->parent) 274 + if (resource_assigned(res)) 274 275 return res->parent; 275 276 276 277 return pbus_select_window_for_type(bus, res->flags); ··· 301 302 if (!res->flags) 302 303 return false; 303 304 304 - if (idx >= PCI_BRIDGE_RESOURCES && idx <= PCI_BRIDGE_RESOURCE_END && 305 - res->flags & IORESOURCE_DISABLED) 305 + if (pci_resource_is_bridge_win(idx) && res->flags & IORESOURCE_DISABLED) 306 306 return false; 307 307 308 308 return true; ··· 309 311 310 312 static bool pdev_resource_should_fit(struct pci_dev *dev, struct resource *res) 311 313 { 312 - if (res->parent) 314 + if (resource_assigned(res)) 313 315 return false; 314 316 315 317 if (res->flags & IORESOURCE_PCI_FIXED) ··· 378 380 return true; 379 381 if (resno == PCI_ROM_RESOURCE && !(res->flags & IORESOURCE_ROM_ENABLE)) 380 382 return true; 383 + if (pci_resource_is_bridge_win(resno) && !resource_size(res)) 384 + return true; 381 385 382 386 return false; 383 387 } 384 388 385 - static inline void reset_resource(struct pci_dev *dev, struct resource *res) 389 + static void reset_resource(struct pci_dev *dev, struct resource *res) 386 390 { 387 391 int idx = pci_resource_num(dev, res); 392 + const char *res_name = pci_resource_name(dev, idx); 388 393 389 - if (idx >= PCI_BRIDGE_RESOURCES && idx <= PCI_BRIDGE_RESOURCE_END) { 394 + if (pci_resource_is_bridge_win(idx)) { 390 395 res->flags |= IORESOURCE_UNSET; 391 396 return; 392 397 } 398 + 399 + pci_dbg(dev, "%s %pR: resetting resource\n", res_name, res); 393 400 394 401 res->start = 0; 395 402 res->end = 0; ··· 416 413 struct list_head *head) 417 414 { 418 415 struct pci_dev_resource *add_res, *tmp; 419 - struct pci_dev_resource *dev_res; 420 416 struct pci_dev *dev; 421 417 struct resource *res; 422 418 const char *res_name; ··· 423 421 int idx; 424 422 425 423 list_for_each_entry_safe(add_res, tmp, realloc_head, list) { 426 - bool found_match = false; 427 - 428 424 res = add_res->res; 429 425 dev = add_res->dev; 430 426 idx = pci_resource_num(dev, res); ··· 431 431 * Skip resource that failed the earlier assignment and is 432 432 * not optional as it would just fail again. 433 433 */ 434 - if (!res->parent && resource_size(res) && 434 + if (!resource_assigned(res) && resource_size(res) && 435 435 !pci_resource_is_optional(dev, idx)) 436 436 goto out; 437 437 438 438 /* Skip this resource if not found in head list */ 439 - list_for_each_entry(dev_res, head, list) { 440 - if (dev_res->res == res) { 441 - found_match = true; 442 - break; 443 - } 444 - } 445 - if (!found_match) /* Just skip */ 439 + if (!res_to_dev_res(head, res)) 446 440 continue; 447 441 448 442 res_name = pci_resource_name(dev, idx); 449 443 add_size = add_res->add_size; 450 444 align = add_res->min_align; 451 - if (!res->parent) { 445 + if (!resource_assigned(res)) { 452 446 resource_set_range(res, align, 453 447 resource_size(res) + add_size); 454 448 if (pci_assign_resource(dev, idx)) { ··· 450 456 "%s %pR: ignoring failure in optional allocation\n", 451 457 res_name, res); 452 458 } 453 - } else if (add_size > 0) { 459 + } else if (add_size > 0 || !IS_ALIGNED(res->start, align)) { 454 460 res->flags |= add_res->flags & 455 461 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); 456 462 if (pci_reassign_resource(dev, idx, add_size, align)) ··· 499 505 500 506 if (pci_assign_resource(dev, idx)) { 501 507 if (fail_head) { 502 - add_to_list(fail_head, dev, res, 503 - 0 /* don't care */, 504 - 0 /* don't care */); 508 + pci_dev_res_add_to_list(fail_head, dev, res, 509 + 0 /* don't care */, 510 + 0 /* don't care */); 505 511 } 506 512 } 507 513 } ··· 598 604 LIST_HEAD(local_fail_head); 599 605 LIST_HEAD(dummy_head); 600 606 struct pci_dev_resource *save_res; 601 - struct pci_dev_resource *dev_res, *tmp_res, *dev_res2; 607 + struct pci_dev_resource *dev_res, *tmp_res, *dev_res2, *addsize_res; 602 608 struct resource *res; 603 609 struct pci_dev *dev; 604 610 unsigned long fail_type; 605 - resource_size_t add_align, align; 611 + resource_size_t align; 606 612 607 613 if (!realloc_head) 608 614 realloc_head = &dummy_head; ··· 613 619 614 620 /* Save original start, end, flags etc at first */ 615 621 list_for_each_entry(dev_res, head, list) { 616 - if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { 617 - free_list(&save_head); 622 + if (pci_dev_res_add_to_list(&save_head, dev_res->dev, 623 + dev_res->res, 0, 0)) { 624 + pci_dev_res_free_list(&save_head); 618 625 goto assign; 619 626 } 620 627 } ··· 624 629 list_for_each_entry_safe(dev_res, tmp_res, head, list) { 625 630 res = dev_res->res; 626 631 627 - res->end += get_res_add_size(realloc_head, res); 632 + addsize_res = res_to_dev_res(realloc_head, res); 633 + if (!addsize_res) 634 + continue; 628 635 636 + res->end += addsize_res->add_size; 629 637 /* 630 638 * There are two kinds of additional resources in the list: 631 639 * 1. bridge resource -- IORESOURCE_STARTALIGN ··· 638 640 if (!(res->flags & IORESOURCE_STARTALIGN)) 639 641 continue; 640 642 641 - add_align = get_res_add_align(realloc_head, res); 642 - 643 + if (addsize_res->min_align <= res->start) 644 + continue; 643 645 /* 644 646 * The "head" list is sorted by alignment so resources with 645 647 * bigger alignment will be assigned first. After we ··· 647 649 * need to reorder the list by alignment to make it 648 650 * consistent. 649 651 */ 650 - if (add_align > res->start) { 651 - resource_set_range(res, add_align, resource_size(res)); 652 + resource_set_range(res, addsize_res->min_align, 653 + resource_size(res)); 652 654 653 - list_for_each_entry(dev_res2, head, list) { 654 - align = pci_resource_alignment(dev_res2->dev, 655 - dev_res2->res); 656 - if (add_align > align) { 657 - list_move_tail(&dev_res->list, 658 - &dev_res2->list); 659 - break; 660 - } 655 + list_for_each_entry(dev_res2, head, list) { 656 + align = pci_resource_alignment(dev_res2->dev, 657 + dev_res2->res); 658 + if (addsize_res->min_align > align) { 659 + list_move_tail(&dev_res->list, &dev_res2->list); 660 + break; 661 661 } 662 662 } 663 663 ··· 668 672 if (list_empty(&local_fail_head)) { 669 673 /* Remove head list from realloc_head list */ 670 674 list_for_each_entry(dev_res, head, list) 671 - remove_from_list(realloc_head, dev_res->res); 672 - free_list(&save_head); 675 + pci_dev_res_remove_from_list(realloc_head, 676 + dev_res->res); 677 + pci_dev_res_free_list(&save_head); 673 678 goto out; 674 679 } 675 680 ··· 680 683 list_for_each_entry(save_res, &save_head, list) { 681 684 struct resource *res = save_res->res; 682 685 683 - if (res->parent) 686 + if (resource_assigned(res)) 684 687 continue; 685 688 686 - restore_dev_resource(save_res); 689 + pci_dev_res_restore(save_res); 687 690 } 688 - free_list(&local_fail_head); 689 - free_list(&save_head); 691 + pci_dev_res_free_list(&local_fail_head); 692 + pci_dev_res_free_list(&save_head); 690 693 goto out; 691 694 } 692 695 ··· 696 699 list_for_each_entry_safe(dev_res, tmp_res, head, list) { 697 700 res = dev_res->res; 698 701 699 - if (res->parent && !pci_need_to_release(fail_type, res)) { 702 + if (resource_assigned(res) && 703 + !pci_need_to_release(fail_type, res)) { 700 704 /* Remove it from realloc_head list */ 701 - remove_from_list(realloc_head, res); 702 - remove_from_list(&save_head, res); 705 + pci_dev_res_remove_from_list(realloc_head, res); 706 + pci_dev_res_remove_from_list(&save_head, res); 703 707 list_del(&dev_res->list); 704 708 kfree(dev_res); 705 709 } 706 710 } 707 711 708 - free_list(&local_fail_head); 712 + pci_dev_res_free_list(&local_fail_head); 709 713 /* Release assigned resource */ 710 714 list_for_each_entry(dev_res, head, list) { 711 715 res = dev_res->res; 712 716 dev = dev_res->dev; 713 717 714 718 pci_release_resource(dev, pci_resource_num(dev, res)); 715 - restore_dev_resource(dev_res); 719 + pci_dev_res_restore(dev_res); 716 720 } 717 721 /* Restore start/end/flags from saved list */ 718 722 list_for_each_entry(save_res, &save_head, list) 719 - restore_dev_resource(save_res); 720 - free_list(&save_head); 723 + pci_dev_res_restore(save_res); 724 + pci_dev_res_free_list(&save_head); 721 725 722 726 /* Satisfy the must-have resource requests */ 723 727 assign_requested_resources_sorted(head, NULL, false); ··· 733 735 res = dev_res->res; 734 736 dev = dev_res->dev; 735 737 736 - if (res->parent) 738 + if (resource_assigned(res)) 737 739 continue; 738 740 739 741 if (fail_head) { 740 - add_to_list(fail_head, dev, res, 741 - 0 /* don't care */, 742 - 0 /* don't care */); 742 + pci_dev_res_add_to_list(fail_head, dev, res, 743 + 0 /* don't care */, 744 + 0 /* don't care */); 743 745 } 744 746 745 747 reset_resource(dev, res); 746 748 } 747 749 748 - free_list(head); 750 + pci_dev_res_free_list(head); 749 751 } 750 752 751 753 static void pdev_assign_resources_sorted(struct pci_dev *dev, ··· 771 773 772 774 __assign_resources_sorted(&head, realloc_head, fail_head); 773 775 } 774 - 775 - void pci_setup_cardbus(struct pci_bus *bus) 776 - { 777 - struct pci_dev *bridge = bus->self; 778 - struct resource *res; 779 - struct pci_bus_region region; 780 - 781 - pci_info(bridge, "CardBus bridge to %pR\n", 782 - &bus->busn_res); 783 - 784 - res = bus->resource[0]; 785 - pcibios_resource_to_bus(bridge->bus, &region, res); 786 - if (res->parent && res->flags & IORESOURCE_IO) { 787 - /* 788 - * The IO resource is allocated a range twice as large as it 789 - * would normally need. This allows us to set both IO regs. 790 - */ 791 - pci_info(bridge, " bridge window %pR\n", res); 792 - pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, 793 - region.start); 794 - pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, 795 - region.end); 796 - } 797 - 798 - res = bus->resource[1]; 799 - pcibios_resource_to_bus(bridge->bus, &region, res); 800 - if (res->parent && res->flags & IORESOURCE_IO) { 801 - pci_info(bridge, " bridge window %pR\n", res); 802 - pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, 803 - region.start); 804 - pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, 805 - region.end); 806 - } 807 - 808 - res = bus->resource[2]; 809 - pcibios_resource_to_bus(bridge->bus, &region, res); 810 - if (res->parent && res->flags & IORESOURCE_MEM) { 811 - pci_info(bridge, " bridge window %pR\n", res); 812 - pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, 813 - region.start); 814 - pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, 815 - region.end); 816 - } 817 - 818 - res = bus->resource[3]; 819 - pcibios_resource_to_bus(bridge->bus, &region, res); 820 - if (res->parent && res->flags & IORESOURCE_MEM) { 821 - pci_info(bridge, " bridge window %pR\n", res); 822 - pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, 823 - region.start); 824 - pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, 825 - region.end); 826 - } 827 - } 828 - EXPORT_SYMBOL(pci_setup_cardbus); 829 776 830 777 /* 831 778 * Initialize bridges with base/limit values we have collected. PCI-to-PCI ··· 803 860 res = &bridge->resource[PCI_BRIDGE_IO_WINDOW]; 804 861 res_name = pci_resource_name(bridge, PCI_BRIDGE_IO_WINDOW); 805 862 pcibios_resource_to_bus(bridge->bus, &region, res); 806 - if (res->parent && res->flags & IORESOURCE_IO) { 863 + if (resource_assigned(res) && res->flags & IORESOURCE_IO) { 807 864 pci_read_config_word(bridge, PCI_IO_BASE, &l); 808 865 io_base_lo = (region.start >> 8) & io_mask; 809 866 io_limit_lo = (region.end >> 8) & io_mask; ··· 835 892 res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW]; 836 893 res_name = pci_resource_name(bridge, PCI_BRIDGE_MEM_WINDOW); 837 894 pcibios_resource_to_bus(bridge->bus, &region, res); 838 - if (res->parent && res->flags & IORESOURCE_MEM) { 895 + if (resource_assigned(res) && res->flags & IORESOURCE_MEM) { 839 896 l = (region.start >> 16) & 0xfff0; 840 897 l |= region.end & 0xfff00000; 841 898 pci_info(bridge, " %s %pR\n", res_name, res); ··· 864 921 res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 865 922 res_name = pci_resource_name(bridge, PCI_BRIDGE_PREF_MEM_WINDOW); 866 923 pcibios_resource_to_bus(bridge->bus, &region, res); 867 - if (res->parent && res->flags & IORESOURCE_PREFETCH) { 924 + if (resource_assigned(res) && res->flags & IORESOURCE_PREFETCH) { 868 925 l = (region.start >> 16) & 0xfff0; 869 926 l |= region.end & 0xfff00000; 870 927 if (res->flags & IORESOURCE_MEM_64) { ··· 935 992 { 936 993 int ret = -EINVAL; 937 994 938 - if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END) 995 + if (!pci_resource_is_bridge_win(i)) 939 996 return 0; 940 997 941 998 if (pci_claim_resource(bridge, i) == 0) ··· 1011 1068 1012 1069 static resource_size_t calculate_memsize(resource_size_t size, 1013 1070 resource_size_t min_size, 1014 - resource_size_t add_size, 1015 1071 resource_size_t children_add_size, 1016 - resource_size_t old_size, 1017 1072 resource_size_t align) 1018 1073 { 1019 - if (size < min_size) 1020 - size = min_size; 1021 - if (old_size == 1) 1022 - old_size = 0; 1023 - 1024 - size = max(size, add_size) + children_add_size; 1025 - return ALIGN(max(size, old_size), align); 1074 + size = max(size, min_size) + children_add_size; 1075 + return ALIGN(size, align); 1026 1076 } 1027 1077 1028 1078 resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus, ··· 1053 1117 * pbus_size_io() - Size the I/O window of a given bus 1054 1118 * 1055 1119 * @bus: The bus 1056 - * @min_size: The minimum I/O window that must be allocated 1057 - * @add_size: Additional optional I/O window 1120 + * @add_size: Additional I/O window 1058 1121 * @realloc_head: Track the additional I/O window on this list 1059 1122 * 1060 1123 * Sizing the I/O windows of the PCI-PCI bridge is trivial, since these ··· 1061 1126 * devices are limited to 256 bytes. We must be careful with the ISA 1062 1127 * aliasing though. 1063 1128 */ 1064 - static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, 1065 - resource_size_t add_size, 1129 + static void pbus_size_io(struct pci_bus *bus, resource_size_t add_size, 1066 1130 struct list_head *realloc_head) 1067 1131 { 1068 1132 struct pci_dev *dev; ··· 1074 1140 return; 1075 1141 1076 1142 /* If resource is already assigned, nothing more to do */ 1077 - if (b_res->parent) 1143 + if (resource_assigned(b_res)) 1078 1144 return; 1079 1145 1080 1146 min_align = window_alignment(bus, IORESOURCE_IO); ··· 1084 1150 pci_dev_for_each_resource(dev, r) { 1085 1151 unsigned long r_size; 1086 1152 1087 - if (r->parent || !(r->flags & IORESOURCE_IO)) 1153 + if (resource_assigned(r) || !(r->flags & IORESOURCE_IO)) 1088 1154 continue; 1089 1155 1090 1156 if (!pdev_resource_assignable(dev, r)) ··· 1106 1172 } 1107 1173 } 1108 1174 1109 - size0 = calculate_iosize(size, min_size, size1, 0, 0, 1175 + size0 = calculate_iosize(size, realloc_head ? 0 : add_size, size1, 0, 0, 1110 1176 resource_size(b_res), min_align); 1111 1177 1112 1178 if (size0) ··· 1114 1180 1115 1181 size1 = size0; 1116 1182 if (realloc_head && (add_size > 0 || children_add_size > 0)) { 1117 - size1 = calculate_iosize(size, min_size, size1, add_size, 1183 + size1 = calculate_iosize(size, 0, size1, add_size, 1118 1184 children_add_size, resource_size(b_res), 1119 1185 min_align); 1120 1186 } ··· 1131 1197 b_res->flags |= IORESOURCE_STARTALIGN; 1132 1198 if (bus->self && size1 > size0 && realloc_head) { 1133 1199 b_res->flags &= ~IORESOURCE_DISABLED; 1134 - add_to_list(realloc_head, bus->self, b_res, size1-size0, 1135 - min_align); 1200 + pci_dev_res_add_to_list(realloc_head, bus->self, b_res, 1201 + size1 - size0, min_align); 1136 1202 pci_info(bus->self, "bridge window %pR to %pR add_size %llx\n", 1137 1203 b_res, &bus->busn_res, 1138 1204 (unsigned long long) size1 - size0); ··· 1161 1227 return min_align; 1162 1228 } 1163 1229 1164 - /** 1165 - * pbus_upstream_space_available - Check no upstream resource limits allocation 1166 - * @bus: The bus 1167 - * @res: The resource to help select the correct bridge window 1168 - * @size: The size required from the bridge window 1169 - * @align: Required alignment for the resource 1170 - * 1171 - * Check that @size can fit inside the upstream bridge resources that are 1172 - * already assigned. Select the upstream bridge window based on the type of 1173 - * @res. 1174 - * 1175 - * Return: %true if enough space is available on all assigned upstream 1230 + /* 1231 + * Calculate bridge window head alignment that leaves no gaps in between 1176 1232 * resources. 1177 1233 */ 1178 - static bool pbus_upstream_space_available(struct pci_bus *bus, 1179 - struct resource *res, 1180 - resource_size_t size, 1181 - resource_size_t align) 1234 + static resource_size_t calculate_head_align(resource_size_t *aligns, 1235 + int max_order) 1182 1236 { 1183 - struct resource_constraint constraint = { 1184 - .max = RESOURCE_SIZE_MAX, 1185 - .align = align, 1186 - }; 1187 - struct pci_bus *downstream = bus; 1237 + resource_size_t head_align = 1; 1238 + resource_size_t remainder = 0; 1239 + int order; 1188 1240 1189 - while ((bus = bus->parent)) { 1190 - if (pci_is_root_bus(bus)) 1191 - break; 1241 + /* Take the largest alignment as the starting point. */ 1242 + head_align <<= max_order + __ffs(SZ_1M); 1192 1243 1193 - res = pbus_select_window(bus, res); 1194 - if (!res) 1195 - return false; 1196 - if (!res->parent) 1197 - continue; 1244 + for (order = max_order - 1; order >= 0; order--) { 1245 + resource_size_t align1 = 1; 1198 1246 1199 - if (resource_size(res) >= size) { 1200 - struct resource gap = {}; 1247 + align1 <<= order + __ffs(SZ_1M); 1201 1248 1202 - if (find_resource_space(res, &gap, size, &constraint) == 0) { 1203 - gap.flags = res->flags; 1204 - pci_dbg(bus->self, 1205 - "Assigned bridge window %pR to %pR free space at %pR\n", 1206 - res, &bus->busn_res, &gap); 1207 - return true; 1208 - } 1249 + /* 1250 + * Account smaller resources with alignment < max_order that 1251 + * could be used to fill head room if alignment less than 1252 + * max_order is used. 1253 + */ 1254 + remainder += aligns[order]; 1255 + 1256 + /* 1257 + * Test if head fill is enough to satisfy the alignment of 1258 + * the larger resources after reducing the alignment. 1259 + */ 1260 + while ((head_align > align1) && (remainder >= head_align / 2)) { 1261 + head_align /= 2; 1262 + remainder -= head_align; 1209 1263 } 1264 + } 1210 1265 1211 - if (bus->self) { 1212 - pci_info(bus->self, 1213 - "Assigned bridge window %pR to %pR cannot fit 0x%llx required for %s bridging to %pR\n", 1214 - res, &bus->busn_res, 1215 - (unsigned long long)size, 1216 - pci_name(downstream->self), 1217 - &downstream->busn_res); 1266 + return head_align; 1267 + } 1268 + 1269 + /* 1270 + * pbus_size_mem_optional - Account optional resources in bridge window 1271 + * 1272 + * Account an optional resource or the optional part of the resource in bridge 1273 + * window size. 1274 + * 1275 + * Return: %true if the resource is entirely optional. 1276 + */ 1277 + static bool pbus_size_mem_optional(struct pci_dev *dev, int resno, 1278 + resource_size_t align, 1279 + struct list_head *realloc_head, 1280 + resource_size_t *add_align, 1281 + resource_size_t *children_add_size) 1282 + { 1283 + struct resource *res = pci_resource_n(dev, resno); 1284 + bool optional = pci_resource_is_optional(dev, resno); 1285 + resource_size_t r_size = resource_size(res); 1286 + struct pci_dev_resource *dev_res; 1287 + 1288 + if (!realloc_head) 1289 + return false; 1290 + 1291 + if (!optional) { 1292 + /* 1293 + * Only bridges have optional sizes in realloc_head at this 1294 + * point. As res_to_dev_res() walks the entire realloc_head 1295 + * list, skip calling it when known unnecessary. 1296 + */ 1297 + if (!pci_resource_is_bridge_win(resno)) 1298 + return false; 1299 + 1300 + dev_res = res_to_dev_res(realloc_head, res); 1301 + if (dev_res) { 1302 + *children_add_size += dev_res->add_size; 1303 + *add_align = max(*add_align, dev_res->min_align); 1218 1304 } 1219 1305 1220 1306 return false; 1221 1307 } 1308 + 1309 + /* Put SRIOV requested res to the optional list */ 1310 + pci_dev_res_add_to_list(realloc_head, dev, res, 0, align); 1311 + *children_add_size += r_size; 1312 + *add_align = max(align, *add_align); 1222 1313 1223 1314 return true; 1224 1315 } ··· 1252 1293 * pbus_size_mem() - Size the memory window of a given bus 1253 1294 * 1254 1295 * @bus: The bus 1255 - * @type: The type of bridge resource 1256 - * @min_size: The minimum memory window that must be allocated 1257 - * @add_size: Additional optional memory window 1296 + * @b_res: The bridge window resource 1297 + * @add_size: Additional memory window 1258 1298 * @realloc_head: Track the additional memory window on this list 1259 1299 * 1260 - * Calculate the size of the bus resource for @type and minimal alignment 1300 + * Calculate the size of the bridge window @b_res and minimal alignment 1261 1301 * which guarantees that all child resources fit in this size. 1262 1302 * 1263 1303 * Set the bus resource start/end to indicate the required size if there an ··· 1265 1307 * Add optional resource requests to the @realloc_head list if it is 1266 1308 * supplied. 1267 1309 */ 1268 - static void pbus_size_mem(struct pci_bus *bus, unsigned long type, 1269 - resource_size_t min_size, 1270 - resource_size_t add_size, 1271 - struct list_head *realloc_head) 1310 + static void pbus_size_mem(struct pci_bus *bus, struct resource *b_res, 1311 + resource_size_t add_size, 1312 + struct list_head *realloc_head) 1272 1313 { 1273 1314 struct pci_dev *dev; 1274 1315 resource_size_t min_align, win_align, align, size, size0, size1 = 0; 1275 - resource_size_t aligns[28]; /* Alignments from 1MB to 128TB */ 1316 + resource_size_t aligns[28] = {}; /* Alignments from 1MB to 128TB */ 1276 1317 int order, max_order; 1277 - struct resource *b_res = pbus_select_window_for_type(bus, type); 1278 1318 resource_size_t children_add_size = 0; 1279 - resource_size_t children_add_align = 0; 1280 1319 resource_size_t add_align = 0; 1281 - resource_size_t relaxed_align; 1282 - resource_size_t old_size; 1283 1320 1284 1321 if (!b_res) 1285 1322 return; 1286 1323 1287 1324 /* If resource is already assigned, nothing more to do */ 1288 - if (b_res->parent) 1325 + if (resource_assigned(b_res)) 1289 1326 return; 1290 1327 1291 - memset(aligns, 0, sizeof(aligns)); 1292 1328 max_order = 0; 1293 1329 size = 0; 1294 1330 ··· 1300 1348 if (b_res != pbus_select_window(bus, r)) 1301 1349 continue; 1302 1350 1303 - r_size = resource_size(r); 1304 - 1305 - /* Put SRIOV requested res to the optional list */ 1306 - if (realloc_head && pci_resource_is_optional(dev, i)) { 1307 - add_align = max(pci_resource_alignment(dev, r), add_align); 1308 - add_to_list(realloc_head, dev, r, 0, 0 /* Don't care */); 1309 - children_add_size += r_size; 1310 - continue; 1311 - } 1312 - 1351 + align = pci_resource_alignment(dev, r); 1313 1352 /* 1314 1353 * aligns[0] is for 1MB (since bridge memory 1315 1354 * windows are always at least 1MB aligned), so 1316 1355 * keep "order" from being negative for smaller 1317 1356 * resources. 1318 1357 */ 1319 - align = pci_resource_alignment(dev, r); 1320 - order = __ffs(align) - __ffs(SZ_1M); 1321 - if (order < 0) 1322 - order = 0; 1358 + order = max_t(int, __ffs(align) - __ffs(SZ_1M), 0); 1323 1359 if (order >= ARRAY_SIZE(aligns)) { 1324 1360 pci_warn(dev, "%s %pR: disabling; bad alignment %#llx\n", 1325 1361 r_name, r, (unsigned long long) align); 1326 1362 r->flags = 0; 1327 1363 continue; 1328 1364 } 1365 + 1366 + if (pbus_size_mem_optional(dev, i, align, 1367 + realloc_head, &add_align, 1368 + &children_add_size)) 1369 + continue; 1370 + 1371 + r_size = resource_size(r); 1329 1372 size += max(r_size, align); 1330 - /* 1331 - * Exclude ranges with size > align from calculation of 1332 - * the alignment. 1333 - */ 1334 - if (r_size <= align) 1335 - aligns[order] += align; 1373 + 1374 + aligns[order] += align; 1336 1375 if (order > max_order) 1337 1376 max_order = order; 1338 - 1339 - if (realloc_head) { 1340 - children_add_size += get_res_add_size(realloc_head, r); 1341 - children_add_align = get_res_add_align(realloc_head, r); 1342 - add_align = max(add_align, children_add_align); 1343 - } 1344 1377 } 1345 1378 } 1346 1379 1347 - old_size = resource_size(b_res); 1348 1380 win_align = window_alignment(bus, b_res->flags); 1349 - min_align = calculate_mem_align(aligns, max_order); 1381 + min_align = calculate_head_align(aligns, max_order); 1350 1382 min_align = max(min_align, win_align); 1351 - size0 = calculate_memsize(size, min_size, 0, 0, old_size, min_align); 1383 + size0 = calculate_memsize(size, realloc_head ? 0 : add_size, 1384 + 0, win_align); 1352 1385 1353 1386 if (size0) { 1354 1387 resource_set_range(b_res, min_align, size0); 1355 1388 b_res->flags &= ~IORESOURCE_DISABLED; 1356 1389 } 1357 1390 1358 - if (bus->self && size0 && 1359 - !pbus_upstream_space_available(bus, b_res, size0, min_align)) { 1360 - relaxed_align = 1ULL << (max_order + __ffs(SZ_1M)); 1361 - relaxed_align = max(relaxed_align, win_align); 1362 - min_align = min(min_align, relaxed_align); 1363 - size0 = calculate_memsize(size, min_size, 0, 0, old_size, win_align); 1364 - resource_set_range(b_res, min_align, size0); 1365 - pci_info(bus->self, "bridge window %pR to %pR requires relaxed alignment rules\n", 1366 - b_res, &bus->busn_res); 1367 - } 1368 - 1369 1391 if (realloc_head && (add_size > 0 || children_add_size > 0)) { 1370 1392 add_align = max(min_align, add_align); 1371 - size1 = calculate_memsize(size, min_size, add_size, children_add_size, 1372 - old_size, add_align); 1373 - 1374 - if (bus->self && size1 && 1375 - !pbus_upstream_space_available(bus, b_res, size1, add_align)) { 1376 - relaxed_align = 1ULL << (max_order + __ffs(SZ_1M)); 1377 - relaxed_align = max(relaxed_align, win_align); 1378 - min_align = min(min_align, relaxed_align); 1379 - size1 = calculate_memsize(size, min_size, add_size, children_add_size, 1380 - old_size, win_align); 1381 - pci_info(bus->self, 1382 - "bridge window %pR to %pR requires relaxed alignment rules\n", 1383 - b_res, &bus->busn_res); 1384 - } 1393 + size1 = calculate_memsize(size, add_size, children_add_size, 1394 + win_align); 1385 1395 } 1386 1396 1387 1397 if (!size0 && !size1) { ··· 1356 1442 1357 1443 resource_set_range(b_res, min_align, size0); 1358 1444 b_res->flags |= IORESOURCE_STARTALIGN; 1359 - if (bus->self && size1 > size0 && realloc_head) { 1445 + if (bus->self && realloc_head && (size1 > size0 || add_align > min_align)) { 1360 1446 b_res->flags &= ~IORESOURCE_DISABLED; 1361 - add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align); 1447 + add_size = size1 > size0 ? size1 - size0 : 0; 1448 + pci_dev_res_add_to_list(realloc_head, bus->self, b_res, 1449 + add_size, add_align); 1362 1450 pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n", 1363 1451 b_res, &bus->busn_res, 1364 - (unsigned long long) (size1 - size0), 1452 + (unsigned long long) add_size, 1365 1453 (unsigned long long) add_align); 1366 1454 } 1367 - } 1368 - 1369 - unsigned long pci_cardbus_resource_alignment(struct resource *res) 1370 - { 1371 - if (res->flags & IORESOURCE_IO) 1372 - return pci_cardbus_io_size; 1373 - if (res->flags & IORESOURCE_MEM) 1374 - return pci_cardbus_mem_size; 1375 - return 0; 1376 - } 1377 - 1378 - static void pci_bus_size_cardbus(struct pci_bus *bus, 1379 - struct list_head *realloc_head) 1380 - { 1381 - struct pci_dev *bridge = bus->self; 1382 - struct resource *b_res; 1383 - resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; 1384 - u16 ctrl; 1385 - 1386 - b_res = &bridge->resource[PCI_CB_BRIDGE_IO_0_WINDOW]; 1387 - if (b_res->parent) 1388 - goto handle_b_res_1; 1389 - /* 1390 - * Reserve some resources for CardBus. We reserve a fixed amount 1391 - * of bus space for CardBus bridges. 1392 - */ 1393 - resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size); 1394 - b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; 1395 - if (realloc_head) { 1396 - b_res->end -= pci_cardbus_io_size; 1397 - add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, 1398 - pci_cardbus_io_size); 1399 - } 1400 - 1401 - handle_b_res_1: 1402 - b_res = &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW]; 1403 - if (b_res->parent) 1404 - goto handle_b_res_2; 1405 - resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size); 1406 - b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; 1407 - if (realloc_head) { 1408 - b_res->end -= pci_cardbus_io_size; 1409 - add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, 1410 - pci_cardbus_io_size); 1411 - } 1412 - 1413 - handle_b_res_2: 1414 - /* MEM1 must not be pref MMIO */ 1415 - pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1416 - if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { 1417 - ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; 1418 - pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 1419 - pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1420 - } 1421 - 1422 - /* Check whether prefetchable memory is supported by this bridge. */ 1423 - pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1424 - if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { 1425 - ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; 1426 - pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 1427 - pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1428 - } 1429 - 1430 - b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_0_WINDOW]; 1431 - if (b_res->parent) 1432 - goto handle_b_res_3; 1433 - /* 1434 - * If we have prefetchable memory support, allocate two regions. 1435 - * Otherwise, allocate one region of twice the size. 1436 - */ 1437 - if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { 1438 - resource_set_range(b_res, pci_cardbus_mem_size, 1439 - pci_cardbus_mem_size); 1440 - b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | 1441 - IORESOURCE_STARTALIGN; 1442 - if (realloc_head) { 1443 - b_res->end -= pci_cardbus_mem_size; 1444 - add_to_list(realloc_head, bridge, b_res, 1445 - pci_cardbus_mem_size, pci_cardbus_mem_size); 1446 - } 1447 - 1448 - /* Reduce that to half */ 1449 - b_res_3_size = pci_cardbus_mem_size; 1450 - } 1451 - 1452 - handle_b_res_3: 1453 - b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW]; 1454 - if (b_res->parent) 1455 - goto handle_done; 1456 - resource_set_range(b_res, pci_cardbus_mem_size, b_res_3_size); 1457 - b_res->flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; 1458 - if (realloc_head) { 1459 - b_res->end -= b_res_3_size; 1460 - add_to_list(realloc_head, bridge, b_res, b_res_3_size, 1461 - pci_cardbus_mem_size); 1462 - } 1463 - 1464 - handle_done: 1465 - ; 1466 1455 } 1467 1456 1468 1457 void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head) ··· 1373 1556 struct pci_dev *dev; 1374 1557 resource_size_t additional_io_size = 0, additional_mmio_size = 0, 1375 1558 additional_mmio_pref_size = 0; 1376 - struct resource *pref; 1559 + struct resource *b_res; 1377 1560 struct pci_host_bridge *host; 1378 1561 int hdr_type; 1379 1562 ··· 1384 1567 1385 1568 switch (dev->hdr_type) { 1386 1569 case PCI_HEADER_TYPE_CARDBUS: 1387 - pci_bus_size_cardbus(b, realloc_head); 1570 + if (pci_bus_size_cardbus_bridge(b, realloc_head)) 1571 + continue; 1388 1572 break; 1389 1573 1390 1574 case PCI_HEADER_TYPE_BRIDGE: ··· 1400 1582 host = to_pci_host_bridge(bus->bridge); 1401 1583 if (!host->size_windows) 1402 1584 return; 1403 - pci_bus_for_each_resource(bus, pref) 1404 - if (pref && (pref->flags & IORESOURCE_PREFETCH)) 1405 - break; 1406 1585 hdr_type = -1; /* Intentionally invalid - not a PCI device. */ 1407 1586 } else { 1408 - pref = &bus->self->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 1409 1587 hdr_type = bus->self->hdr_type; 1410 1588 } 1411 1589 ··· 1419 1605 } 1420 1606 fallthrough; 1421 1607 default: 1422 - pbus_size_io(bus, realloc_head ? 0 : additional_io_size, 1423 - additional_io_size, realloc_head); 1608 + pbus_size_io(bus, additional_io_size, realloc_head); 1424 1609 1425 - if (pref && (pref->flags & IORESOURCE_PREFETCH)) { 1426 - pbus_size_mem(bus, 1427 - IORESOURCE_MEM | IORESOURCE_PREFETCH | 1428 - (pref->flags & IORESOURCE_MEM_64), 1429 - realloc_head ? 0 : additional_mmio_pref_size, 1430 - additional_mmio_pref_size, realloc_head); 1610 + b_res = pbus_select_window_for_type(bus, IORESOURCE_MEM | 1611 + IORESOURCE_PREFETCH | 1612 + IORESOURCE_MEM_64); 1613 + if (b_res && (b_res->flags & IORESOURCE_PREFETCH)) { 1614 + pbus_size_mem(bus, b_res, additional_mmio_pref_size, 1615 + realloc_head); 1431 1616 } 1432 1617 1433 - pbus_size_mem(bus, IORESOURCE_MEM, 1434 - realloc_head ? 0 : additional_mmio_size, 1435 - additional_mmio_size, realloc_head); 1618 + b_res = pbus_select_window_for_type(bus, IORESOURCE_MEM); 1619 + if (b_res) { 1620 + pbus_size_mem(bus, b_res, additional_mmio_size, 1621 + realloc_head); 1622 + } 1436 1623 break; 1437 1624 } 1438 1625 } ··· 1471 1656 pci_dev_for_each_resource(dev, r) { 1472 1657 struct pci_bus *b; 1473 1658 1474 - if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) || 1659 + if (resource_assigned(r) || 1660 + !(r->flags & IORESOURCE_PCI_FIXED) || 1475 1661 !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 1476 1662 continue; 1477 1663 1478 1664 b = dev->bus; 1479 - while (b && !r->parent) { 1665 + while (b && !resource_assigned(r)) { 1480 1666 assign_fixed_resource_on_bus(b, r); 1481 1667 b = b->parent; 1482 1668 } ··· 1509 1693 break; 1510 1694 1511 1695 case PCI_HEADER_TYPE_CARDBUS: 1512 - pci_setup_cardbus(b); 1696 + pci_setup_cardbus_bridge(b); 1513 1697 break; 1514 1698 1515 1699 default: ··· 1533 1717 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { 1534 1718 struct resource *r = &dev->resource[i]; 1535 1719 1536 - if (!r->flags || r->parent) 1720 + if (!r->flags || resource_assigned(r)) 1537 1721 continue; 1538 1722 1539 1723 pci_claim_resource(dev, i); ··· 1547 1731 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 1548 1732 struct resource *r = &dev->resource[i]; 1549 1733 1550 - if (!r->flags || r->parent) 1734 + if (!r->flags || resource_assigned(r)) 1735 + continue; 1736 + if (r->flags & IORESOURCE_DISABLED) 1551 1737 continue; 1552 1738 1553 1739 pci_claim_bridge_resource(dev, i); ··· 1616 1798 break; 1617 1799 1618 1800 case PCI_CLASS_BRIDGE_CARDBUS: 1619 - pci_setup_cardbus(b); 1801 + pci_setup_cardbus_bridge(b); 1620 1802 break; 1621 1803 1622 1804 default: ··· 1632 1814 struct pci_dev *dev = bus->self; 1633 1815 int idx, ret; 1634 1816 1635 - if (!b_win->parent) 1817 + if (!resource_assigned(b_win)) 1636 1818 return; 1637 1819 1638 1820 idx = pci_resource_num(dev, b_win); ··· 1828 2010 { 1829 2011 resource_size_t add_size, size = resource_size(res); 1830 2012 1831 - if (res->parent) 2013 + if (resource_assigned(res)) 1832 2014 return; 1833 2015 1834 2016 if (!new_size) ··· 1850 2032 1851 2033 /* If the resource is part of the add_list, remove it now */ 1852 2034 if (add_list) 1853 - remove_from_list(add_list, res); 2035 + pci_dev_res_remove_from_list(add_list, res); 1854 2036 } 1855 2037 1856 2038 static void remove_dev_resource(struct resource *avail, struct pci_dev *dev, ··· 1918 2100 * window. 1919 2101 */ 1920 2102 align = pci_resource_alignment(bridge, res); 1921 - if (!res->parent && align) 2103 + if (!resource_assigned(res) && align) 1922 2104 available[i].start = min(ALIGN(available[i].start, align), 1923 2105 available[i].end + 1); 1924 2106 ··· 2102 2284 2103 2285 /* Restore size and flags */ 2104 2286 list_for_each_entry(fail_res, fail_head, list) 2105 - restore_dev_resource(fail_res); 2287 + pci_dev_res_restore(fail_res); 2106 2288 2107 - free_list(fail_head); 2289 + pci_dev_res_free_list(fail_head); 2108 2290 } 2109 2291 2110 2292 /* ··· 2151 2333 /* Depth last, allocate resources and update the hardware. */ 2152 2334 __pci_bus_assign_resources(bus, add_list, &fail_head); 2153 2335 if (WARN_ON_ONCE(add_list && !list_empty(add_list))) 2154 - free_list(add_list); 2336 + pci_dev_res_free_list(add_list); 2155 2337 tried_times++; 2156 2338 2157 2339 /* Any device complain? */ ··· 2166 2348 dev_info(&bus->dev, 2167 2349 "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n"); 2168 2350 } 2169 - free_list(&fail_head); 2351 + pci_dev_res_free_list(&fail_head); 2170 2352 break; 2171 2353 } 2172 2354 ··· 2214 2396 2215 2397 __pci_bridge_assign_resources(bridge, &add_list, &fail_head); 2216 2398 if (WARN_ON_ONCE(!list_empty(&add_list))) 2217 - free_list(&add_list); 2399 + pci_dev_res_free_list(&add_list); 2218 2400 tried_times++; 2219 2401 2220 2402 if (list_empty(&fail_head)) ··· 2222 2404 2223 2405 if (tried_times >= 2) { 2224 2406 /* Still fail, don't need to try more */ 2225 - free_list(&fail_head); 2407 + pci_dev_res_free_list(&fail_head); 2226 2408 break; 2227 2409 } 2228 2410 ··· 2263 2445 2264 2446 /* Ignore BARs which are still in use */ 2265 2447 if (!res->child) { 2266 - ret = add_to_list(saved, bridge, res, 0, 0); 2448 + ret = pci_dev_res_add_to_list(saved, bridge, res, 0, 0); 2267 2449 if (ret) 2268 2450 return ret; 2269 2451 ··· 2285 2467 __pci_bus_size_bridges(bridge->subordinate, &added); 2286 2468 __pci_bridge_assign_resources(bridge, &added, &failed); 2287 2469 if (WARN_ON_ONCE(!list_empty(&added))) 2288 - free_list(&added); 2470 + pci_dev_res_free_list(&added); 2289 2471 2290 2472 if (!list_empty(&failed)) { 2291 2473 if (pci_required_resource_failed(&failed, type)) 2292 2474 ret = -ENOSPC; 2293 - free_list(&failed); 2475 + pci_dev_res_free_list(&failed); 2294 2476 if (ret) 2295 2477 return ret; 2296 2478 ··· 2338 2520 if (b_win != pbus_select_window(bus, r)) 2339 2521 continue; 2340 2522 2341 - ret = add_to_list(&saved, pdev, r, 0, 0); 2523 + ret = pci_dev_res_add_to_list(&saved, pdev, r, 0, 0); 2342 2524 if (ret) 2343 2525 goto restore; 2344 2526 pci_release_resource(pdev, i); ··· 2356 2538 2357 2539 out: 2358 2540 up_read(&pci_bus_sem); 2359 - free_list(&saved); 2541 + pci_dev_res_free_list(&saved); 2360 2542 return ret; 2361 2543 2362 2544 restore: ··· 2367 2549 2368 2550 i = pci_resource_num(dev, res); 2369 2551 2370 - if (res->parent) { 2552 + if (resource_assigned(res)) { 2371 2553 release_child_resources(res); 2372 2554 pci_release_resource(dev, i); 2373 2555 } 2374 2556 2375 - restore_dev_resource(dev_res); 2557 + pci_dev_res_restore(dev_res); 2376 2558 2377 2559 ret = pci_claim_resource(dev, i); 2378 2560 if (ret) ··· 2404 2586 up_read(&pci_bus_sem); 2405 2587 __pci_bus_assign_resources(bus, &add_list, NULL); 2406 2588 if (WARN_ON_ONCE(!list_empty(&add_list))) 2407 - free_list(&add_list); 2589 + pci_dev_res_free_list(&add_list); 2408 2590 } 2409 2591 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);

+306

drivers/pci/setup-cardbus.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Cardbus bridge setup routines. 4 + */ 5 + 6 + #include <linux/bitfield.h> 7 + #include <linux/errno.h> 8 + #include <linux/ioport.h> 9 + #include <linux/pci.h> 10 + #include <linux/sizes.h> 11 + #include <linux/sprintf.h> 12 + #include <linux/types.h> 13 + 14 + #include "pci.h" 15 + 16 + #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 17 + #define CARDBUS_RESERVE_BUSNR 3 18 + 19 + #define DEFAULT_CARDBUS_IO_SIZE SZ_256 20 + #define DEFAULT_CARDBUS_MEM_SIZE SZ_64M 21 + /* pci=cbmemsize=nnM,cbiosize=nn can override this */ 22 + static unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; 23 + static unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; 24 + 25 + unsigned long pci_cardbus_resource_alignment(struct resource *res) 26 + { 27 + if (res->flags & IORESOURCE_IO) 28 + return pci_cardbus_io_size; 29 + if (res->flags & IORESOURCE_MEM) 30 + return pci_cardbus_mem_size; 31 + return 0; 32 + } 33 + 34 + int pci_bus_size_cardbus_bridge(struct pci_bus *bus, 35 + struct list_head *realloc_head) 36 + { 37 + struct pci_dev *bridge = bus->self; 38 + struct resource *b_res; 39 + resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; 40 + u16 ctrl; 41 + 42 + b_res = &bridge->resource[PCI_CB_BRIDGE_IO_0_WINDOW]; 43 + if (resource_assigned(b_res)) 44 + goto handle_b_res_1; 45 + /* 46 + * Reserve some resources for CardBus. We reserve a fixed amount 47 + * of bus space for CardBus bridges. 48 + */ 49 + resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size); 50 + b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; 51 + if (realloc_head) { 52 + b_res->end -= pci_cardbus_io_size; 53 + pci_dev_res_add_to_list(realloc_head, bridge, b_res, 54 + pci_cardbus_io_size, 55 + pci_cardbus_io_size); 56 + } 57 + 58 + handle_b_res_1: 59 + b_res = &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW]; 60 + if (resource_assigned(b_res)) 61 + goto handle_b_res_2; 62 + resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size); 63 + b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; 64 + if (realloc_head) { 65 + b_res->end -= pci_cardbus_io_size; 66 + pci_dev_res_add_to_list(realloc_head, bridge, b_res, 67 + pci_cardbus_io_size, 68 + pci_cardbus_io_size); 69 + } 70 + 71 + handle_b_res_2: 72 + /* MEM1 must not be pref MMIO */ 73 + pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 74 + if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { 75 + ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; 76 + pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 77 + pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 78 + } 79 + 80 + /* Check whether prefetchable memory is supported by this bridge. */ 81 + pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 82 + if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { 83 + ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; 84 + pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 85 + pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 86 + } 87 + 88 + b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_0_WINDOW]; 89 + if (resource_assigned(b_res)) 90 + goto handle_b_res_3; 91 + /* 92 + * If we have prefetchable memory support, allocate two regions. 93 + * Otherwise, allocate one region of twice the size. 94 + */ 95 + if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { 96 + resource_set_range(b_res, pci_cardbus_mem_size, 97 + pci_cardbus_mem_size); 98 + b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | 99 + IORESOURCE_STARTALIGN; 100 + if (realloc_head) { 101 + b_res->end -= pci_cardbus_mem_size; 102 + pci_dev_res_add_to_list(realloc_head, bridge, b_res, 103 + pci_cardbus_mem_size, 104 + pci_cardbus_mem_size); 105 + } 106 + 107 + /* Reduce that to half */ 108 + b_res_3_size = pci_cardbus_mem_size; 109 + } 110 + 111 + handle_b_res_3: 112 + b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW]; 113 + if (resource_assigned(b_res)) 114 + goto handle_done; 115 + resource_set_range(b_res, pci_cardbus_mem_size, b_res_3_size); 116 + b_res->flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; 117 + if (realloc_head) { 118 + b_res->end -= b_res_3_size; 119 + pci_dev_res_add_to_list(realloc_head, bridge, b_res, 120 + b_res_3_size, pci_cardbus_mem_size); 121 + } 122 + 123 + handle_done: 124 + return 0; 125 + } 126 + 127 + void pci_setup_cardbus_bridge(struct pci_bus *bus) 128 + { 129 + struct pci_dev *bridge = bus->self; 130 + struct resource *res; 131 + struct pci_bus_region region; 132 + 133 + pci_info(bridge, "CardBus bridge to %pR\n", 134 + &bus->busn_res); 135 + 136 + res = bus->resource[0]; 137 + pcibios_resource_to_bus(bridge->bus, &region, res); 138 + if (resource_assigned(res) && res->flags & IORESOURCE_IO) { 139 + /* 140 + * The IO resource is allocated a range twice as large as it 141 + * would normally need. This allows us to set both IO regs. 142 + */ 143 + pci_info(bridge, " bridge window %pR\n", res); 144 + pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, 145 + region.start); 146 + pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, 147 + region.end); 148 + } 149 + 150 + res = bus->resource[1]; 151 + pcibios_resource_to_bus(bridge->bus, &region, res); 152 + if (resource_assigned(res) && res->flags & IORESOURCE_IO) { 153 + pci_info(bridge, " bridge window %pR\n", res); 154 + pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, 155 + region.start); 156 + pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, 157 + region.end); 158 + } 159 + 160 + res = bus->resource[2]; 161 + pcibios_resource_to_bus(bridge->bus, &region, res); 162 + if (resource_assigned(res) && res->flags & IORESOURCE_MEM) { 163 + pci_info(bridge, " bridge window %pR\n", res); 164 + pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, 165 + region.start); 166 + pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, 167 + region.end); 168 + } 169 + 170 + res = bus->resource[3]; 171 + pcibios_resource_to_bus(bridge->bus, &region, res); 172 + if (resource_assigned(res) && res->flags & IORESOURCE_MEM) { 173 + pci_info(bridge, " bridge window %pR\n", res); 174 + pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, 175 + region.start); 176 + pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, 177 + region.end); 178 + } 179 + } 180 + EXPORT_SYMBOL(pci_setup_cardbus_bridge); 181 + 182 + int pci_setup_cardbus(char *str) 183 + { 184 + if (!strncmp(str, "cbiosize=", 9)) { 185 + pci_cardbus_io_size = memparse(str + 9, &str); 186 + return 0; 187 + } else if (!strncmp(str, "cbmemsize=", 10)) { 188 + pci_cardbus_mem_size = memparse(str + 10, &str); 189 + return 0; 190 + } 191 + 192 + return -ENOENT; 193 + } 194 + 195 + int pci_cardbus_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 196 + u32 buses, int max, 197 + unsigned int available_buses, int pass) 198 + { 199 + struct pci_bus *child; 200 + bool fixed_buses; 201 + u8 fixed_sec, fixed_sub; 202 + int next_busnr; 203 + u32 i, j = 0; 204 + 205 + /* 206 + * We need to assign a number to this bus which we always do in the 207 + * second pass. 208 + */ 209 + if (!pass) { 210 + /* 211 + * Temporarily disable forwarding of the configuration 212 + * cycles on all bridges in this bus segment to avoid 213 + * possible conflicts in the second pass between two bridges 214 + * programmed with overlapping bus ranges. 215 + */ 216 + pci_write_config_dword(dev, PCI_PRIMARY_BUS, 217 + buses & PCI_SEC_LATENCY_TIMER_MASK); 218 + return max; 219 + } 220 + 221 + /* Clear errors */ 222 + pci_write_config_word(dev, PCI_STATUS, 0xffff); 223 + 224 + /* Read bus numbers from EA Capability (if present) */ 225 + fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); 226 + if (fixed_buses) 227 + next_busnr = fixed_sec; 228 + else 229 + next_busnr = max + 1; 230 + 231 + /* 232 + * Prevent assigning a bus number that already exists. This can 233 + * happen when a bridge is hot-plugged, so in this case we only 234 + * re-scan this bus. 235 + */ 236 + child = pci_find_bus(pci_domain_nr(bus), next_busnr); 237 + if (!child) { 238 + child = pci_add_new_bus(bus, dev, next_busnr); 239 + if (!child) 240 + return max; 241 + pci_bus_insert_busn_res(child, next_busnr, bus->busn_res.end); 242 + } 243 + max++; 244 + if (available_buses) 245 + available_buses--; 246 + 247 + buses = (buses & PCI_SEC_LATENCY_TIMER_MASK) | 248 + FIELD_PREP(PCI_PRIMARY_BUS_MASK, child->primary) | 249 + FIELD_PREP(PCI_SECONDARY_BUS_MASK, child->busn_res.start) | 250 + FIELD_PREP(PCI_SUBORDINATE_BUS_MASK, child->busn_res.end); 251 + 252 + /* 253 + * yenta.c forces a secondary latency timer of 176. 254 + * Copy that behaviour here. 255 + */ 256 + buses &= ~PCI_SEC_LATENCY_TIMER_MASK; 257 + buses |= FIELD_PREP(PCI_SEC_LATENCY_TIMER_MASK, CARDBUS_LATENCY_TIMER); 258 + 259 + /* We need to blast all three values with a single write */ 260 + pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 261 + 262 + /* 263 + * For CardBus bridges, we leave 4 bus numbers as cards with a 264 + * PCI-to-PCI bridge can be inserted later. 265 + */ 266 + for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { 267 + struct pci_bus *parent = bus; 268 + 269 + if (pci_find_bus(pci_domain_nr(bus), max + i + 1)) 270 + break; 271 + 272 + while (parent->parent) { 273 + if (!pcibios_assign_all_busses() && 274 + (parent->busn_res.end > max) && 275 + (parent->busn_res.end <= max + i)) { 276 + j = 1; 277 + } 278 + parent = parent->parent; 279 + } 280 + if (j) { 281 + /* 282 + * Often, there are two CardBus bridges -- try to 283 + * leave one valid bus number for each one. 284 + */ 285 + i /= 2; 286 + break; 287 + } 288 + } 289 + max += i; 290 + 291 + /* 292 + * Set subordinate bus number to its real value. If fixed 293 + * subordinate bus number exists from EA capability then use it. 294 + */ 295 + if (fixed_buses) 296 + max = fixed_sub; 297 + pci_bus_update_busn_res_end(child, max); 298 + pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 299 + 300 + scnprintf(child->name, sizeof(child->name), "PCI CardBus %04x:%02x", 301 + pci_domain_nr(bus), child->number); 302 + 303 + pbus_validate_busn(child); 304 + 305 + return max; 306 + }

+1 -1

drivers/pci/setup-res.c

··· 359 359 360 360 res->flags &= ~IORESOURCE_UNSET; 361 361 res->flags &= ~IORESOURCE_STARTALIGN; 362 - if (resno >= PCI_BRIDGE_RESOURCES && resno <= PCI_BRIDGE_RESOURCE_END) 362 + if (pci_resource_is_bridge_win(resno)) 363 363 res->flags &= ~IORESOURCE_DISABLED; 364 364 365 365 pci_info(dev, "%s %pR: assigned\n", res_name, res);

+1 -1

drivers/pcmcia/yenta_socket.c

··· 779 779 IORESOURCE_MEM, 780 780 PCI_CB_MEMORY_BASE_1, PCI_CB_MEMORY_LIMIT_1); 781 781 if (program) 782 - pci_setup_cardbus(socket->dev->subordinate); 782 + pci_setup_cardbus_bridge(socket->dev->subordinate); 783 783 } 784 784 785 785

+1 -1

include/linux/ioport.h

··· 338 338 * Check if this resource is added to a resource tree or detached. Caller is 339 339 * responsible for not racing assignment. 340 340 */ 341 - static inline bool resource_assigned(struct resource *res) 341 + static inline bool resource_assigned(const struct resource *res) 342 342 { 343 343 return res->parent; 344 344 }

+5 -1

include/linux/pci.h

··· 1248 1248 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1249 1249 void pci_stop_root_bus(struct pci_bus *bus); 1250 1250 void pci_remove_root_bus(struct pci_bus *bus); 1251 - void pci_setup_cardbus(struct pci_bus *bus); 1251 + #ifdef CONFIG_CARDBUS 1252 + void pci_setup_cardbus_bridge(struct pci_bus *bus); 1253 + #else 1254 + static inline void pci_setup_cardbus_bridge(struct pci_bus *bus) { } 1255 + #endif 1252 1256 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1253 1257 void pci_sort_breadthfirst(void); 1254 1258 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)

+5

include/uapi/linux/pci_regs.h

··· 132 132 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 133 133 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 134 134 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 135 + /* Masks for dword-sized processing of Bus Number and Sec Latency Timer fields */ 136 + #define PCI_PRIMARY_BUS_MASK 0x000000ff 137 + #define PCI_SECONDARY_BUS_MASK 0x0000ff00 138 + #define PCI_SUBORDINATE_BUS_MASK 0x00ff0000 139 + #define PCI_SEC_LATENCY_TIMER_MASK 0xff000000 135 140 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 136 141 #define PCI_IO_LIMIT 0x1d 137 142 #define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */

+1 -1

kernel/resource.c

··· 82 82 83 83 #ifdef CONFIG_PROC_FS 84 84 85 - enum { MAX_IORES_LEVEL = 5 }; 85 + enum { MAX_IORES_LEVEL = 8 }; 86 86 87 87 static void *r_start(struct seq_file *m, loff_t *pos) 88 88 __acquires(resource_lock)

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