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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge branch kvm-arm64/spe-trbe-nvhe into kvmarm-master/next
* kvm-arm64/spe-trbe-nvhe:
: .
: Fix SPE and TRBE nVHE world switch which can otherwise result in
: pretty bad behaviours, as they have the nasty habit of performing
: out of context speculative page table walks.
:
: Patches courtesy of Will Deacon.
: .
KVM: arm64: Don't pass host_debug_state to BRBE world-switch routines
KVM: arm64: Disable SPE Profiling Buffer when running in guest context
KVM: arm64: Disable TRBE Trace Buffer Unit when running in guest context
Signed-off-by: Marc Zyngier <maz@kernel.org>
+95
-25
+2
arch/arm64/include/asm/kvm_host.h
+2
arch/arm64/include/asm/kvm_host.h
···
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struct kvm_guest_debug_arch regs;
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/* Statistical profiling extension */
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u64 pmscr_el1;
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+
u64 pmblimitr_el1;
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/* Self-hosted trace */
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u64 trfcr_el1;
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+
u64 trblimitr_el1;
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/* Values of trap registers for the host before guest entry. */
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u64 mdcr_el2;
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u64 brbcr_el1;
+92
-24
arch/arm64/kvm/hyp/nvhe/debug-sr.c
+92
-24
arch/arm64/kvm/hyp/nvhe/debug-sr.c
···
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#include <asm/kvm_hyp.h>
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#include <asm/kvm_mmu.h>
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-
static void __debug_save_spe(u64 *pmscr_el1)
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+
static void __debug_save_spe(void)
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{
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-
u64 reg;
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+
u64 *pmscr_el1, *pmblimitr_el1;
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-
/* Clear pmscr in case of early return */
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-
*pmscr_el1 = 0;
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+
pmscr_el1 = host_data_ptr(host_debug_state.pmscr_el1);
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pmblimitr_el1 = host_data_ptr(host_debug_state.pmblimitr_el1);
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/*
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* At this point, we know that this CPU implements
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* SPE and is available to the host.
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* Check if the host is actually using it ?
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*/
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-
reg = read_sysreg_s(SYS_PMBLIMITR_EL1);
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-
if (!(reg & BIT(PMBLIMITR_EL1_E_SHIFT)))
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+
*pmblimitr_el1 = read_sysreg_s(SYS_PMBLIMITR_EL1);
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+
if (!(*pmblimitr_el1 & BIT(PMBLIMITR_EL1_E_SHIFT)))
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return;
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/* Yes; save the control register and disable data generation */
···
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/* Now drain all buffered data to memory */
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psb_csync();
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+
dsb(nsh);
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+
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+
/* And disable the profiling buffer */
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write_sysreg_s(0, SYS_PMBLIMITR_EL1);
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isb();
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}
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-
static void __debug_restore_spe(u64 pmscr_el1)
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+
static void __debug_restore_spe(void)
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{
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-
if (!pmscr_el1)
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+
u64 pmblimitr_el1 = *host_data_ptr(host_debug_state.pmblimitr_el1);
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+
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+
if (!(pmblimitr_el1 & BIT(PMBLIMITR_EL1_E_SHIFT)))
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return;
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/* The host page table is installed, but not yet synchronised */
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isb();
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+
/* Re-enable the profiling buffer. */
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+
write_sysreg_s(pmblimitr_el1, SYS_PMBLIMITR_EL1);
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+
isb();
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+
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/* Re-enable data generation */
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-
write_sysreg_el1(pmscr_el1, SYS_PMSCR);
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write_sysreg_el1(*host_data_ptr(host_debug_state.pmscr_el1), SYS_PMSCR);
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}
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static void __trace_do_switch(u64 *saved_trfcr, u64 new_trfcr)
···
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write_sysreg_el1(new_trfcr, SYS_TRFCR);
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}
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-
static bool __trace_needs_drain(void)
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+
static void __trace_drain_and_disable(void)
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{
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-
if (is_protected_kvm_enabled() && host_data_test_flag(HAS_TRBE))
74
-
return read_sysreg_s(SYS_TRBLIMITR_EL1) & TRBLIMITR_EL1_E;
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+
u64 *trblimitr_el1 = host_data_ptr(host_debug_state.trblimitr_el1);
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+
bool needs_drain = is_protected_kvm_enabled() ?
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host_data_test_flag(HAS_TRBE) :
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host_data_test_flag(TRBE_ENABLED);
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-
return host_data_test_flag(TRBE_ENABLED);
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+
if (!needs_drain) {
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+
*trblimitr_el1 = 0;
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+
return;
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+
}
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+
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+
*trblimitr_el1 = read_sysreg_s(SYS_TRBLIMITR_EL1);
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+
if (*trblimitr_el1 & TRBLIMITR_EL1_E) {
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+
/*
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+
* The host has enabled the Trace Buffer Unit so we have
76
+
* to beat the CPU with a stick until it stops accessing
77
+
* memory.
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+
*/
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+
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+
/* First, ensure that our prior write to TRFCR has stuck. */
81
+
isb();
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+
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+
/* Now synchronise with the trace and drain the buffer. */
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+
tsb_csync();
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+
dsb(nsh);
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+
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+
/*
88
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* With no more trace being generated, we can disable the
89
+
* Trace Buffer Unit.
90
+
*/
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+
write_sysreg_s(0, SYS_TRBLIMITR_EL1);
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+
if (cpus_have_final_cap(ARM64_WORKAROUND_2064142)) {
93
+
/*
94
+
* Some CPUs are so good, we have to drain 'em
95
+
* twice.
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+
*/
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+
tsb_csync();
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+
dsb(nsh);
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+
}
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+
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+
/*
102
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* Ensure that the Trace Buffer Unit is disabled before
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+
* we start mucking with the stage-2 and trap
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+
* configuration.
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+
*/
106
+
isb();
107
+
}
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}
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static bool __trace_needs_switch(void)
···
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__trace_do_switch(host_data_ptr(host_debug_state.trfcr_el1),
134
81
*host_data_ptr(trfcr_while_in_guest));
135
-
136
-
if (__trace_needs_drain()) {
137
-
isb();
138
-
tsb_csync();
139
-
}
82
+
__trace_drain_and_disable();
140
83
}
141
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142
85
static void __trace_switch_to_host(void)
143
86
{
87
+
u64 trblimitr_el1 = *host_data_ptr(host_debug_state.trblimitr_el1);
88
+
89
+
if (trblimitr_el1 & TRBLIMITR_EL1_E) {
90
+
/* Re-enable the Trace Buffer Unit for the host. */
91
+
write_sysreg_s(trblimitr_el1, SYS_TRBLIMITR_EL1);
92
+
isb();
93
+
if (cpus_have_final_cap(ARM64_WORKAROUND_2038923)) {
94
+
/*
95
+
* Make sure the unit is re-enabled before we
96
+
* poke TRFCR.
97
+
*/
98
+
isb();
99
+
}
100
+
}
101
+
144
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__trace_do_switch(host_data_ptr(trfcr_while_in_guest),
145
103
*host_data_ptr(host_debug_state.trfcr_el1));
146
104
}
147
105
148
-
static void __debug_save_brbe(u64 *brbcr_el1)
106
+
static void __debug_save_brbe(void)
149
107
{
108
+
u64 *brbcr_el1 = host_data_ptr(host_debug_state.brbcr_el1);
109
+
150
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*brbcr_el1 = 0;
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152
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/* Check if the BRBE is enabled */
···
175
109
write_sysreg_el1(0, SYS_BRBCR);
176
110
}
177
111
178
-
static void __debug_restore_brbe(u64 brbcr_el1)
112
+
static void __debug_restore_brbe(void)
179
113
{
114
+
u64 brbcr_el1 = *host_data_ptr(host_debug_state.brbcr_el1);
115
+
180
116
if (!brbcr_el1)
181
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return;
182
118
···
190
122
{
191
123
/* Disable and flush SPE data generation */
192
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if (host_data_test_flag(HAS_SPE))
193
-
__debug_save_spe(host_data_ptr(host_debug_state.pmscr_el1));
125
+
__debug_save_spe();
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195
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/* Disable BRBE branch records */
196
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if (host_data_test_flag(HAS_BRBE))
197
-
__debug_save_brbe(host_data_ptr(host_debug_state.brbcr_el1));
129
+
__debug_save_brbe();
198
130
199
131
if (__trace_needs_switch())
200
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__trace_switch_to_guest();
···
208
140
void __debug_restore_host_buffers_nvhe(struct kvm_vcpu *vcpu)
209
141
{
210
142
if (host_data_test_flag(HAS_SPE))
211
-
__debug_restore_spe(*host_data_ptr(host_debug_state.pmscr_el1));
143
+
__debug_restore_spe();
212
144
if (host_data_test_flag(HAS_BRBE))
213
-
__debug_restore_brbe(*host_data_ptr(host_debug_state.brbcr_el1));
145
+
__debug_restore_brbe();
214
146
if (__trace_needs_switch())
215
147
__trace_switch_to_host();
216
148
}
+1
-1
arch/arm64/kvm/hyp/nvhe/switch.c
+1
-1
arch/arm64/kvm/hyp/nvhe/switch.c
···
293
293
* We're about to restore some new MMU state. Make sure
294
294
* ongoing page-table walks that have started before we
295
295
* trapped to EL2 have completed. This also synchronises the
296
-
* above disabling of BRBE, SPE and TRBE.
296
+
* above disabling of BRBE.
297
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*
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* See DDI0487I.a D8.1.5 "Out-of-context translation regimes",
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* rule R_LFHQG and subsequent information statements.