tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile into akpm

Pull tile bugfixes from Chris Metcalf:
"This includes a variety of minor bug fixes, mostly to do with testing
"make allyesconfig", "make allmodconfig", "make allnoconfig", inspired
to Tejun Heo's observation about Kconfig.freezer not being included.

The largest changes are just syntax changes removing the tile-specific
use of a macro named INT_MASK, which is way too commonly redefined
throughout driver code"

* 'stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile:
tile: tag some code with #ifdef CONFIG_COMPAT
tile: fix memcpy_*io functions for allnoconfig
tile: export a handful of symbols appropriately
drm: fix compile failure by including <linux/swiotlb.h>
tile: avoid defining INT_MASK macro in <arch/interrupts.h>
tile: provide "screen_info" when enabling VT
drivers/input/joystick/analog.c: enable precise timer
tile: include kernel/Kconfig.freezer in tile Kconfig
tile: remove an unused variable in copy_thread()

Linus Torvalds 73c0d752 983ca836

+413 -394
+2
arch/tile/Kconfig
··· 140 140 141 141 source "init/Kconfig" 142 142 143 + source "kernel/Kconfig.freezer" 144 + 143 145 menu "Tilera-specific configuration" 144 146 145 147 config NR_CPUS
+5 -1
arch/tile/include/asm/io.h
··· 250 250 #define iowrite32 writel 251 251 #define iowrite64 writeq 252 252 253 - static inline void memset_io(void *dst, int val, size_t len) 253 + #if CHIP_HAS_MMIO() || defined(CONFIG_PCI) 254 + 255 + static inline void memset_io(volatile void *dst, int val, size_t len) 254 256 { 255 257 int x; 256 258 BUG_ON((unsigned long)dst & 0x3); ··· 278 276 for (x = 0; x < len; x += 4) 279 277 writel(*(u32 *)(src + x), dst + x); 280 278 } 279 + 280 + #endif 281 281 282 282 /* 283 283 * The Tile architecture does not support IOPORT, even with PCI.
+10 -22
arch/tile/include/asm/irqflags.h
··· 18 18 #include <arch/interrupts.h> 19 19 #include <arch/chip.h> 20 20 21 - #if !defined(__tilegx__) && defined(__ASSEMBLY__) 22 - 23 21 /* 24 22 * The set of interrupts we want to allow when interrupts are nominally 25 23 * disabled. The remainder are effectively "NMI" interrupts from 26 24 * the point of view of the generic Linux code. Note that synchronous 27 25 * interrupts (aka "non-queued") are not blocked by the mask in any case. 28 26 */ 29 - #if CHIP_HAS_AUX_PERF_COUNTERS() 30 - #define LINUX_MASKABLE_INTERRUPTS_HI \ 31 - (~(INT_MASK_HI(INT_PERF_COUNT) | INT_MASK_HI(INT_AUX_PERF_COUNT))) 32 - #else 33 - #define LINUX_MASKABLE_INTERRUPTS_HI \ 34 - (~(INT_MASK_HI(INT_PERF_COUNT))) 35 - #endif 36 - 37 - #else 38 - 39 - #if CHIP_HAS_AUX_PERF_COUNTERS() 40 27 #define LINUX_MASKABLE_INTERRUPTS \ 41 - (~(INT_MASK(INT_PERF_COUNT) | INT_MASK(INT_AUX_PERF_COUNT))) 42 - #else 43 - #define LINUX_MASKABLE_INTERRUPTS \ 44 - (~(INT_MASK(INT_PERF_COUNT))) 45 - #endif 28 + (~((_AC(1,ULL) << INT_PERF_COUNT) | (_AC(1,ULL) << INT_AUX_PERF_COUNT))) 46 29 30 + #if CHIP_HAS_SPLIT_INTR_MASK() 31 + /* The same macro, but for the two 32-bit SPRs separately. */ 32 + #define LINUX_MASKABLE_INTERRUPTS_LO (-1) 33 + #define LINUX_MASKABLE_INTERRUPTS_HI \ 34 + (~((1 << (INT_PERF_COUNT - 32)) | (1 << (INT_AUX_PERF_COUNT - 32)))) 47 35 #endif 48 36 49 37 #ifndef __ASSEMBLY__ ··· 114 126 * to know our current state. 115 127 */ 116 128 DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask); 117 - #define INITIAL_INTERRUPTS_ENABLED INT_MASK(INT_MEM_ERROR) 129 + #define INITIAL_INTERRUPTS_ENABLED (1ULL << INT_MEM_ERROR) 118 130 119 131 /* Disable interrupts. */ 120 132 #define arch_local_irq_disable() \ ··· 153 165 154 166 /* Prevent the given interrupt from being enabled next time we enable irqs. */ 155 167 #define arch_local_irq_mask(interrupt) \ 156 - (__get_cpu_var(interrupts_enabled_mask) &= ~INT_MASK(interrupt)) 168 + (__get_cpu_var(interrupts_enabled_mask) &= ~(1ULL << (interrupt))) 157 169 158 170 /* Prevent the given interrupt from being enabled immediately. */ 159 171 #define arch_local_irq_mask_now(interrupt) do { \ ··· 163 175 164 176 /* Allow the given interrupt to be enabled next time we enable irqs. */ 165 177 #define arch_local_irq_unmask(interrupt) \ 166 - (__get_cpu_var(interrupts_enabled_mask) |= INT_MASK(interrupt)) 178 + (__get_cpu_var(interrupts_enabled_mask) |= (1ULL << (interrupt))) 167 179 168 180 /* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */ 169 181 #define arch_local_irq_unmask_now(interrupt) do { \ ··· 238 250 /* Disable interrupts. */ 239 251 #define IRQ_DISABLE(tmp0, tmp1) \ 240 252 { \ 241 - movei tmp0, -1; \ 253 + movei tmp0, LINUX_MASKABLE_INTERRUPTS_LO; \ 242 254 moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS_HI) \ 243 255 }; \ 244 256 { \
+198 -196
arch/tile/include/uapi/arch/interrupts_32.h
··· 15 15 #ifndef __ARCH_INTERRUPTS_H__ 16 16 #define __ARCH_INTERRUPTS_H__ 17 17 18 + #ifndef __KERNEL__ 18 19 /** Mask for an interrupt. */ 19 20 /* Note: must handle breaking interrupts into high and low words manually. */ 20 21 #define INT_MASK_LO(intno) (1 << (intno)) ··· 23 22 24 23 #ifndef __ASSEMBLER__ 25 24 #define INT_MASK(intno) (1ULL << (intno)) 25 + #endif 26 26 #endif 27 27 28 28 ··· 94 92 95 93 #ifndef __ASSEMBLER__ 96 94 #define QUEUED_INTERRUPTS ( \ 97 - INT_MASK(INT_MEM_ERROR) | \ 98 - INT_MASK(INT_DMATLB_MISS) | \ 99 - INT_MASK(INT_DMATLB_ACCESS) | \ 100 - INT_MASK(INT_SNITLB_MISS) | \ 101 - INT_MASK(INT_SN_NOTIFY) | \ 102 - INT_MASK(INT_SN_FIREWALL) | \ 103 - INT_MASK(INT_IDN_FIREWALL) | \ 104 - INT_MASK(INT_UDN_FIREWALL) | \ 105 - INT_MASK(INT_TILE_TIMER) | \ 106 - INT_MASK(INT_IDN_TIMER) | \ 107 - INT_MASK(INT_UDN_TIMER) | \ 108 - INT_MASK(INT_DMA_NOTIFY) | \ 109 - INT_MASK(INT_IDN_CA) | \ 110 - INT_MASK(INT_UDN_CA) | \ 111 - INT_MASK(INT_IDN_AVAIL) | \ 112 - INT_MASK(INT_UDN_AVAIL) | \ 113 - INT_MASK(INT_PERF_COUNT) | \ 114 - INT_MASK(INT_INTCTRL_3) | \ 115 - INT_MASK(INT_INTCTRL_2) | \ 116 - INT_MASK(INT_INTCTRL_1) | \ 117 - INT_MASK(INT_INTCTRL_0) | \ 118 - INT_MASK(INT_BOOT_ACCESS) | \ 119 - INT_MASK(INT_WORLD_ACCESS) | \ 120 - INT_MASK(INT_I_ASID) | \ 121 - INT_MASK(INT_D_ASID) | \ 122 - INT_MASK(INT_DMA_ASID) | \ 123 - INT_MASK(INT_SNI_ASID) | \ 124 - INT_MASK(INT_DMA_CPL) | \ 125 - INT_MASK(INT_SN_CPL) | \ 126 - INT_MASK(INT_DOUBLE_FAULT) | \ 127 - INT_MASK(INT_AUX_PERF_COUNT) | \ 95 + (1ULL << INT_MEM_ERROR) | \ 96 + (1ULL << INT_DMATLB_MISS) | \ 97 + (1ULL << INT_DMATLB_ACCESS) | \ 98 + (1ULL << INT_SNITLB_MISS) | \ 99 + (1ULL << INT_SN_NOTIFY) | \ 100 + (1ULL << INT_SN_FIREWALL) | \ 101 + (1ULL << INT_IDN_FIREWALL) | \ 102 + (1ULL << INT_UDN_FIREWALL) | \ 103 + (1ULL << INT_TILE_TIMER) | \ 104 + (1ULL << INT_IDN_TIMER) | \ 105 + (1ULL << INT_UDN_TIMER) | \ 106 + (1ULL << INT_DMA_NOTIFY) | \ 107 + (1ULL << INT_IDN_CA) | \ 108 + (1ULL << INT_UDN_CA) | \ 109 + (1ULL << INT_IDN_AVAIL) | \ 110 + (1ULL << INT_UDN_AVAIL) | \ 111 + (1ULL << INT_PERF_COUNT) | \ 112 + (1ULL << INT_INTCTRL_3) | \ 113 + (1ULL << INT_INTCTRL_2) | \ 114 + (1ULL << INT_INTCTRL_1) | \ 115 + (1ULL << INT_INTCTRL_0) | \ 116 + (1ULL << INT_BOOT_ACCESS) | \ 117 + (1ULL << INT_WORLD_ACCESS) | \ 118 + (1ULL << INT_I_ASID) | \ 119 + (1ULL << INT_D_ASID) | \ 120 + (1ULL << INT_DMA_ASID) | \ 121 + (1ULL << INT_SNI_ASID) | \ 122 + (1ULL << INT_DMA_CPL) | \ 123 + (1ULL << INT_SN_CPL) | \ 124 + (1ULL << INT_DOUBLE_FAULT) | \ 125 + (1ULL << INT_AUX_PERF_COUNT) | \ 128 126 0) 129 127 #define NONQUEUED_INTERRUPTS ( \ 130 - INT_MASK(INT_ITLB_MISS) | \ 131 - INT_MASK(INT_ILL) | \ 132 - INT_MASK(INT_GPV) | \ 133 - INT_MASK(INT_SN_ACCESS) | \ 134 - INT_MASK(INT_IDN_ACCESS) | \ 135 - INT_MASK(INT_UDN_ACCESS) | \ 136 - INT_MASK(INT_IDN_REFILL) | \ 137 - INT_MASK(INT_UDN_REFILL) | \ 138 - INT_MASK(INT_IDN_COMPLETE) | \ 139 - INT_MASK(INT_UDN_COMPLETE) | \ 140 - INT_MASK(INT_SWINT_3) | \ 141 - INT_MASK(INT_SWINT_2) | \ 142 - INT_MASK(INT_SWINT_1) | \ 143 - INT_MASK(INT_SWINT_0) | \ 144 - INT_MASK(INT_UNALIGN_DATA) | \ 145 - INT_MASK(INT_DTLB_MISS) | \ 146 - INT_MASK(INT_DTLB_ACCESS) | \ 147 - INT_MASK(INT_SN_STATIC_ACCESS) | \ 128 + (1ULL << INT_ITLB_MISS) | \ 129 + (1ULL << INT_ILL) | \ 130 + (1ULL << INT_GPV) | \ 131 + (1ULL << INT_SN_ACCESS) | \ 132 + (1ULL << INT_IDN_ACCESS) | \ 133 + (1ULL << INT_UDN_ACCESS) | \ 134 + (1ULL << INT_IDN_REFILL) | \ 135 + (1ULL << INT_UDN_REFILL) | \ 136 + (1ULL << INT_IDN_COMPLETE) | \ 137 + (1ULL << INT_UDN_COMPLETE) | \ 138 + (1ULL << INT_SWINT_3) | \ 139 + (1ULL << INT_SWINT_2) | \ 140 + (1ULL << INT_SWINT_1) | \ 141 + (1ULL << INT_SWINT_0) | \ 142 + (1ULL << INT_UNALIGN_DATA) | \ 143 + (1ULL << INT_DTLB_MISS) | \ 144 + (1ULL << INT_DTLB_ACCESS) | \ 145 + (1ULL << INT_SN_STATIC_ACCESS) | \ 148 146 0) 149 147 #define CRITICAL_MASKED_INTERRUPTS ( \ 150 - INT_MASK(INT_MEM_ERROR) | \ 151 - INT_MASK(INT_DMATLB_MISS) | \ 152 - INT_MASK(INT_DMATLB_ACCESS) | \ 153 - INT_MASK(INT_SNITLB_MISS) | \ 154 - INT_MASK(INT_SN_NOTIFY) | \ 155 - INT_MASK(INT_SN_FIREWALL) | \ 156 - INT_MASK(INT_IDN_FIREWALL) | \ 157 - INT_MASK(INT_UDN_FIREWALL) | \ 158 - INT_MASK(INT_TILE_TIMER) | \ 159 - INT_MASK(INT_IDN_TIMER) | \ 160 - INT_MASK(INT_UDN_TIMER) | \ 161 - INT_MASK(INT_DMA_NOTIFY) | \ 162 - INT_MASK(INT_IDN_CA) | \ 163 - INT_MASK(INT_UDN_CA) | \ 164 - INT_MASK(INT_IDN_AVAIL) | \ 165 - INT_MASK(INT_UDN_AVAIL) | \ 166 - INT_MASK(INT_PERF_COUNT) | \ 167 - INT_MASK(INT_INTCTRL_3) | \ 168 - INT_MASK(INT_INTCTRL_2) | \ 169 - INT_MASK(INT_INTCTRL_1) | \ 170 - INT_MASK(INT_INTCTRL_0) | \ 171 - INT_MASK(INT_AUX_PERF_COUNT) | \ 148 + (1ULL << INT_MEM_ERROR) | \ 149 + (1ULL << INT_DMATLB_MISS) | \ 150 + (1ULL << INT_DMATLB_ACCESS) | \ 151 + (1ULL << INT_SNITLB_MISS) | \ 152 + (1ULL << INT_SN_NOTIFY) | \ 153 + (1ULL << INT_SN_FIREWALL) | \ 154 + (1ULL << INT_IDN_FIREWALL) | \ 155 + (1ULL << INT_UDN_FIREWALL) | \ 156 + (1ULL << INT_TILE_TIMER) | \ 157 + (1ULL << INT_IDN_TIMER) | \ 158 + (1ULL << INT_UDN_TIMER) | \ 159 + (1ULL << INT_DMA_NOTIFY) | \ 160 + (1ULL << INT_IDN_CA) | \ 161 + (1ULL << INT_UDN_CA) | \ 162 + (1ULL << INT_IDN_AVAIL) | \ 163 + (1ULL << INT_UDN_AVAIL) | \ 164 + (1ULL << INT_PERF_COUNT) | \ 165 + (1ULL << INT_INTCTRL_3) | \ 166 + (1ULL << INT_INTCTRL_2) | \ 167 + (1ULL << INT_INTCTRL_1) | \ 168 + (1ULL << INT_INTCTRL_0) | \ 169 + (1ULL << INT_AUX_PERF_COUNT) | \ 172 170 0) 173 171 #define CRITICAL_UNMASKED_INTERRUPTS ( \ 174 - INT_MASK(INT_ITLB_MISS) | \ 175 - INT_MASK(INT_ILL) | \ 176 - INT_MASK(INT_GPV) | \ 177 - INT_MASK(INT_SN_ACCESS) | \ 178 - INT_MASK(INT_IDN_ACCESS) | \ 179 - INT_MASK(INT_UDN_ACCESS) | \ 180 - INT_MASK(INT_IDN_REFILL) | \ 181 - INT_MASK(INT_UDN_REFILL) | \ 182 - INT_MASK(INT_IDN_COMPLETE) | \ 183 - INT_MASK(INT_UDN_COMPLETE) | \ 184 - INT_MASK(INT_SWINT_3) | \ 185 - INT_MASK(INT_SWINT_2) | \ 186 - INT_MASK(INT_SWINT_1) | \ 187 - INT_MASK(INT_SWINT_0) | \ 188 - INT_MASK(INT_UNALIGN_DATA) | \ 189 - INT_MASK(INT_DTLB_MISS) | \ 190 - INT_MASK(INT_DTLB_ACCESS) | \ 191 - INT_MASK(INT_BOOT_ACCESS) | \ 192 - INT_MASK(INT_WORLD_ACCESS) | \ 193 - INT_MASK(INT_I_ASID) | \ 194 - INT_MASK(INT_D_ASID) | \ 195 - INT_MASK(INT_DMA_ASID) | \ 196 - INT_MASK(INT_SNI_ASID) | \ 197 - INT_MASK(INT_DMA_CPL) | \ 198 - INT_MASK(INT_SN_CPL) | \ 199 - INT_MASK(INT_DOUBLE_FAULT) | \ 200 - INT_MASK(INT_SN_STATIC_ACCESS) | \ 172 + (1ULL << INT_ITLB_MISS) | \ 173 + (1ULL << INT_ILL) | \ 174 + (1ULL << INT_GPV) | \ 175 + (1ULL << INT_SN_ACCESS) | \ 176 + (1ULL << INT_IDN_ACCESS) | \ 177 + (1ULL << INT_UDN_ACCESS) | \ 178 + (1ULL << INT_IDN_REFILL) | \ 179 + (1ULL << INT_UDN_REFILL) | \ 180 + (1ULL << INT_IDN_COMPLETE) | \ 181 + (1ULL << INT_UDN_COMPLETE) | \ 182 + (1ULL << INT_SWINT_3) | \ 183 + (1ULL << INT_SWINT_2) | \ 184 + (1ULL << INT_SWINT_1) | \ 185 + (1ULL << INT_SWINT_0) | \ 186 + (1ULL << INT_UNALIGN_DATA) | \ 187 + (1ULL << INT_DTLB_MISS) | \ 188 + (1ULL << INT_DTLB_ACCESS) | \ 189 + (1ULL << INT_BOOT_ACCESS) | \ 190 + (1ULL << INT_WORLD_ACCESS) | \ 191 + (1ULL << INT_I_ASID) | \ 192 + (1ULL << INT_D_ASID) | \ 193 + (1ULL << INT_DMA_ASID) | \ 194 + (1ULL << INT_SNI_ASID) | \ 195 + (1ULL << INT_DMA_CPL) | \ 196 + (1ULL << INT_SN_CPL) | \ 197 + (1ULL << INT_DOUBLE_FAULT) | \ 198 + (1ULL << INT_SN_STATIC_ACCESS) | \ 201 199 0) 202 200 #define MASKABLE_INTERRUPTS ( \ 203 - INT_MASK(INT_MEM_ERROR) | \ 204 - INT_MASK(INT_IDN_REFILL) | \ 205 - INT_MASK(INT_UDN_REFILL) | \ 206 - INT_MASK(INT_IDN_COMPLETE) | \ 207 - INT_MASK(INT_UDN_COMPLETE) | \ 208 - INT_MASK(INT_DMATLB_MISS) | \ 209 - INT_MASK(INT_DMATLB_ACCESS) | \ 210 - INT_MASK(INT_SNITLB_MISS) | \ 211 - INT_MASK(INT_SN_NOTIFY) | \ 212 - INT_MASK(INT_SN_FIREWALL) | \ 213 - INT_MASK(INT_IDN_FIREWALL) | \ 214 - INT_MASK(INT_UDN_FIREWALL) | \ 215 - INT_MASK(INT_TILE_TIMER) | \ 216 - INT_MASK(INT_IDN_TIMER) | \ 217 - INT_MASK(INT_UDN_TIMER) | \ 218 - INT_MASK(INT_DMA_NOTIFY) | \ 219 - INT_MASK(INT_IDN_CA) | \ 220 - INT_MASK(INT_UDN_CA) | \ 221 - INT_MASK(INT_IDN_AVAIL) | \ 222 - INT_MASK(INT_UDN_AVAIL) | \ 223 - INT_MASK(INT_PERF_COUNT) | \ 224 - INT_MASK(INT_INTCTRL_3) | \ 225 - INT_MASK(INT_INTCTRL_2) | \ 226 - INT_MASK(INT_INTCTRL_1) | \ 227 - INT_MASK(INT_INTCTRL_0) | \ 228 - INT_MASK(INT_AUX_PERF_COUNT) | \ 201 + (1ULL << INT_MEM_ERROR) | \ 202 + (1ULL << INT_IDN_REFILL) | \ 203 + (1ULL << INT_UDN_REFILL) | \ 204 + (1ULL << INT_IDN_COMPLETE) | \ 205 + (1ULL << INT_UDN_COMPLETE) | \ 206 + (1ULL << INT_DMATLB_MISS) | \ 207 + (1ULL << INT_DMATLB_ACCESS) | \ 208 + (1ULL << INT_SNITLB_MISS) | \ 209 + (1ULL << INT_SN_NOTIFY) | \ 210 + (1ULL << INT_SN_FIREWALL) | \ 211 + (1ULL << INT_IDN_FIREWALL) | \ 212 + (1ULL << INT_UDN_FIREWALL) | \ 213 + (1ULL << INT_TILE_TIMER) | \ 214 + (1ULL << INT_IDN_TIMER) | \ 215 + (1ULL << INT_UDN_TIMER) | \ 216 + (1ULL << INT_DMA_NOTIFY) | \ 217 + (1ULL << INT_IDN_CA) | \ 218 + (1ULL << INT_UDN_CA) | \ 219 + (1ULL << INT_IDN_AVAIL) | \ 220 + (1ULL << INT_UDN_AVAIL) | \ 221 + (1ULL << INT_PERF_COUNT) | \ 222 + (1ULL << INT_INTCTRL_3) | \ 223 + (1ULL << INT_INTCTRL_2) | \ 224 + (1ULL << INT_INTCTRL_1) | \ 225 + (1ULL << INT_INTCTRL_0) | \ 226 + (1ULL << INT_AUX_PERF_COUNT) | \ 229 227 0) 230 228 #define UNMASKABLE_INTERRUPTS ( \ 231 - INT_MASK(INT_ITLB_MISS) | \ 232 - INT_MASK(INT_ILL) | \ 233 - INT_MASK(INT_GPV) | \ 234 - INT_MASK(INT_SN_ACCESS) | \ 235 - INT_MASK(INT_IDN_ACCESS) | \ 236 - INT_MASK(INT_UDN_ACCESS) | \ 237 - INT_MASK(INT_SWINT_3) | \ 238 - INT_MASK(INT_SWINT_2) | \ 239 - INT_MASK(INT_SWINT_1) | \ 240 - INT_MASK(INT_SWINT_0) | \ 241 - INT_MASK(INT_UNALIGN_DATA) | \ 242 - INT_MASK(INT_DTLB_MISS) | \ 243 - INT_MASK(INT_DTLB_ACCESS) | \ 244 - INT_MASK(INT_BOOT_ACCESS) | \ 245 - INT_MASK(INT_WORLD_ACCESS) | \ 246 - INT_MASK(INT_I_ASID) | \ 247 - INT_MASK(INT_D_ASID) | \ 248 - INT_MASK(INT_DMA_ASID) | \ 249 - INT_MASK(INT_SNI_ASID) | \ 250 - INT_MASK(INT_DMA_CPL) | \ 251 - INT_MASK(INT_SN_CPL) | \ 252 - INT_MASK(INT_DOUBLE_FAULT) | \ 253 - INT_MASK(INT_SN_STATIC_ACCESS) | \ 229 + (1ULL << INT_ITLB_MISS) | \ 230 + (1ULL << INT_ILL) | \ 231 + (1ULL << INT_GPV) | \ 232 + (1ULL << INT_SN_ACCESS) | \ 233 + (1ULL << INT_IDN_ACCESS) | \ 234 + (1ULL << INT_UDN_ACCESS) | \ 235 + (1ULL << INT_SWINT_3) | \ 236 + (1ULL << INT_SWINT_2) | \ 237 + (1ULL << INT_SWINT_1) | \ 238 + (1ULL << INT_SWINT_0) | \ 239 + (1ULL << INT_UNALIGN_DATA) | \ 240 + (1ULL << INT_DTLB_MISS) | \ 241 + (1ULL << INT_DTLB_ACCESS) | \ 242 + (1ULL << INT_BOOT_ACCESS) | \ 243 + (1ULL << INT_WORLD_ACCESS) | \ 244 + (1ULL << INT_I_ASID) | \ 245 + (1ULL << INT_D_ASID) | \ 246 + (1ULL << INT_DMA_ASID) | \ 247 + (1ULL << INT_SNI_ASID) | \ 248 + (1ULL << INT_DMA_CPL) | \ 249 + (1ULL << INT_SN_CPL) | \ 250 + (1ULL << INT_DOUBLE_FAULT) | \ 251 + (1ULL << INT_SN_STATIC_ACCESS) | \ 254 252 0) 255 253 #define SYNC_INTERRUPTS ( \ 256 - INT_MASK(INT_ITLB_MISS) | \ 257 - INT_MASK(INT_ILL) | \ 258 - INT_MASK(INT_GPV) | \ 259 - INT_MASK(INT_SN_ACCESS) | \ 260 - INT_MASK(INT_IDN_ACCESS) | \ 261 - INT_MASK(INT_UDN_ACCESS) | \ 262 - INT_MASK(INT_IDN_REFILL) | \ 263 - INT_MASK(INT_UDN_REFILL) | \ 264 - INT_MASK(INT_IDN_COMPLETE) | \ 265 - INT_MASK(INT_UDN_COMPLETE) | \ 266 - INT_MASK(INT_SWINT_3) | \ 267 - INT_MASK(INT_SWINT_2) | \ 268 - INT_MASK(INT_SWINT_1) | \ 269 - INT_MASK(INT_SWINT_0) | \ 270 - INT_MASK(INT_UNALIGN_DATA) | \ 271 - INT_MASK(INT_DTLB_MISS) | \ 272 - INT_MASK(INT_DTLB_ACCESS) | \ 273 - INT_MASK(INT_SN_STATIC_ACCESS) | \ 254 + (1ULL << INT_ITLB_MISS) | \ 255 + (1ULL << INT_ILL) | \ 256 + (1ULL << INT_GPV) | \ 257 + (1ULL << INT_SN_ACCESS) | \ 258 + (1ULL << INT_IDN_ACCESS) | \ 259 + (1ULL << INT_UDN_ACCESS) | \ 260 + (1ULL << INT_IDN_REFILL) | \ 261 + (1ULL << INT_UDN_REFILL) | \ 262 + (1ULL << INT_IDN_COMPLETE) | \ 263 + (1ULL << INT_UDN_COMPLETE) | \ 264 + (1ULL << INT_SWINT_3) | \ 265 + (1ULL << INT_SWINT_2) | \ 266 + (1ULL << INT_SWINT_1) | \ 267 + (1ULL << INT_SWINT_0) | \ 268 + (1ULL << INT_UNALIGN_DATA) | \ 269 + (1ULL << INT_DTLB_MISS) | \ 270 + (1ULL << INT_DTLB_ACCESS) | \ 271 + (1ULL << INT_SN_STATIC_ACCESS) | \ 274 272 0) 275 273 #define NON_SYNC_INTERRUPTS ( \ 276 - INT_MASK(INT_MEM_ERROR) | \ 277 - INT_MASK(INT_DMATLB_MISS) | \ 278 - INT_MASK(INT_DMATLB_ACCESS) | \ 279 - INT_MASK(INT_SNITLB_MISS) | \ 280 - INT_MASK(INT_SN_NOTIFY) | \ 281 - INT_MASK(INT_SN_FIREWALL) | \ 282 - INT_MASK(INT_IDN_FIREWALL) | \ 283 - INT_MASK(INT_UDN_FIREWALL) | \ 284 - INT_MASK(INT_TILE_TIMER) | \ 285 - INT_MASK(INT_IDN_TIMER) | \ 286 - INT_MASK(INT_UDN_TIMER) | \ 287 - INT_MASK(INT_DMA_NOTIFY) | \ 288 - INT_MASK(INT_IDN_CA) | \ 289 - INT_MASK(INT_UDN_CA) | \ 290 - INT_MASK(INT_IDN_AVAIL) | \ 291 - INT_MASK(INT_UDN_AVAIL) | \ 292 - INT_MASK(INT_PERF_COUNT) | \ 293 - INT_MASK(INT_INTCTRL_3) | \ 294 - INT_MASK(INT_INTCTRL_2) | \ 295 - INT_MASK(INT_INTCTRL_1) | \ 296 - INT_MASK(INT_INTCTRL_0) | \ 297 - INT_MASK(INT_BOOT_ACCESS) | \ 298 - INT_MASK(INT_WORLD_ACCESS) | \ 299 - INT_MASK(INT_I_ASID) | \ 300 - INT_MASK(INT_D_ASID) | \ 301 - INT_MASK(INT_DMA_ASID) | \ 302 - INT_MASK(INT_SNI_ASID) | \ 303 - INT_MASK(INT_DMA_CPL) | \ 304 - INT_MASK(INT_SN_CPL) | \ 305 - INT_MASK(INT_DOUBLE_FAULT) | \ 306 - INT_MASK(INT_AUX_PERF_COUNT) | \ 274 + (1ULL << INT_MEM_ERROR) | \ 275 + (1ULL << INT_DMATLB_MISS) | \ 276 + (1ULL << INT_DMATLB_ACCESS) | \ 277 + (1ULL << INT_SNITLB_MISS) | \ 278 + (1ULL << INT_SN_NOTIFY) | \ 279 + (1ULL << INT_SN_FIREWALL) | \ 280 + (1ULL << INT_IDN_FIREWALL) | \ 281 + (1ULL << INT_UDN_FIREWALL) | \ 282 + (1ULL << INT_TILE_TIMER) | \ 283 + (1ULL << INT_IDN_TIMER) | \ 284 + (1ULL << INT_UDN_TIMER) | \ 285 + (1ULL << INT_DMA_NOTIFY) | \ 286 + (1ULL << INT_IDN_CA) | \ 287 + (1ULL << INT_UDN_CA) | \ 288 + (1ULL << INT_IDN_AVAIL) | \ 289 + (1ULL << INT_UDN_AVAIL) | \ 290 + (1ULL << INT_PERF_COUNT) | \ 291 + (1ULL << INT_INTCTRL_3) | \ 292 + (1ULL << INT_INTCTRL_2) | \ 293 + (1ULL << INT_INTCTRL_1) | \ 294 + (1ULL << INT_INTCTRL_0) | \ 295 + (1ULL << INT_BOOT_ACCESS) | \ 296 + (1ULL << INT_WORLD_ACCESS) | \ 297 + (1ULL << INT_I_ASID) | \ 298 + (1ULL << INT_D_ASID) | \ 299 + (1ULL << INT_DMA_ASID) | \ 300 + (1ULL << INT_SNI_ASID) | \ 301 + (1ULL << INT_DMA_CPL) | \ 302 + (1ULL << INT_SN_CPL) | \ 303 + (1ULL << INT_DOUBLE_FAULT) | \ 304 + (1ULL << INT_AUX_PERF_COUNT) | \ 307 305 0) 308 306 #endif /* !__ASSEMBLER__ */ 309 307 #endif /* !__ARCH_INTERRUPTS_H__ */
+174 -172
arch/tile/include/uapi/arch/interrupts_64.h
··· 15 15 #ifndef __ARCH_INTERRUPTS_H__ 16 16 #define __ARCH_INTERRUPTS_H__ 17 17 18 + #ifndef __KERNEL__ 18 19 /** Mask for an interrupt. */ 19 20 #ifdef __ASSEMBLER__ 20 21 /* Note: must handle breaking interrupts into high and low words manually. */ 21 22 #define INT_MASK(intno) (1 << (intno)) 22 23 #else 23 24 #define INT_MASK(intno) (1ULL << (intno)) 25 + #endif 24 26 #endif 25 27 26 28 ··· 87 85 88 86 #ifndef __ASSEMBLER__ 89 87 #define QUEUED_INTERRUPTS ( \ 90 - INT_MASK(INT_MEM_ERROR) | \ 91 - INT_MASK(INT_IDN_COMPLETE) | \ 92 - INT_MASK(INT_UDN_COMPLETE) | \ 93 - INT_MASK(INT_IDN_FIREWALL) | \ 94 - INT_MASK(INT_UDN_FIREWALL) | \ 95 - INT_MASK(INT_TILE_TIMER) | \ 96 - INT_MASK(INT_AUX_TILE_TIMER) | \ 97 - INT_MASK(INT_IDN_TIMER) | \ 98 - INT_MASK(INT_UDN_TIMER) | \ 99 - INT_MASK(INT_IDN_AVAIL) | \ 100 - INT_MASK(INT_UDN_AVAIL) | \ 101 - INT_MASK(INT_IPI_3) | \ 102 - INT_MASK(INT_IPI_2) | \ 103 - INT_MASK(INT_IPI_1) | \ 104 - INT_MASK(INT_IPI_0) | \ 105 - INT_MASK(INT_PERF_COUNT) | \ 106 - INT_MASK(INT_AUX_PERF_COUNT) | \ 107 - INT_MASK(INT_INTCTRL_3) | \ 108 - INT_MASK(INT_INTCTRL_2) | \ 109 - INT_MASK(INT_INTCTRL_1) | \ 110 - INT_MASK(INT_INTCTRL_0) | \ 111 - INT_MASK(INT_BOOT_ACCESS) | \ 112 - INT_MASK(INT_WORLD_ACCESS) | \ 113 - INT_MASK(INT_I_ASID) | \ 114 - INT_MASK(INT_D_ASID) | \ 115 - INT_MASK(INT_DOUBLE_FAULT) | \ 88 + (1ULL << INT_MEM_ERROR) | \ 89 + (1ULL << INT_IDN_COMPLETE) | \ 90 + (1ULL << INT_UDN_COMPLETE) | \ 91 + (1ULL << INT_IDN_FIREWALL) | \ 92 + (1ULL << INT_UDN_FIREWALL) | \ 93 + (1ULL << INT_TILE_TIMER) | \ 94 + (1ULL << INT_AUX_TILE_TIMER) | \ 95 + (1ULL << INT_IDN_TIMER) | \ 96 + (1ULL << INT_UDN_TIMER) | \ 97 + (1ULL << INT_IDN_AVAIL) | \ 98 + (1ULL << INT_UDN_AVAIL) | \ 99 + (1ULL << INT_IPI_3) | \ 100 + (1ULL << INT_IPI_2) | \ 101 + (1ULL << INT_IPI_1) | \ 102 + (1ULL << INT_IPI_0) | \ 103 + (1ULL << INT_PERF_COUNT) | \ 104 + (1ULL << INT_AUX_PERF_COUNT) | \ 105 + (1ULL << INT_INTCTRL_3) | \ 106 + (1ULL << INT_INTCTRL_2) | \ 107 + (1ULL << INT_INTCTRL_1) | \ 108 + (1ULL << INT_INTCTRL_0) | \ 109 + (1ULL << INT_BOOT_ACCESS) | \ 110 + (1ULL << INT_WORLD_ACCESS) | \ 111 + (1ULL << INT_I_ASID) | \ 112 + (1ULL << INT_D_ASID) | \ 113 + (1ULL << INT_DOUBLE_FAULT) | \ 116 114 0) 117 115 #define NONQUEUED_INTERRUPTS ( \ 118 - INT_MASK(INT_SINGLE_STEP_3) | \ 119 - INT_MASK(INT_SINGLE_STEP_2) | \ 120 - INT_MASK(INT_SINGLE_STEP_1) | \ 121 - INT_MASK(INT_SINGLE_STEP_0) | \ 122 - INT_MASK(INT_ITLB_MISS) | \ 123 - INT_MASK(INT_ILL) | \ 124 - INT_MASK(INT_GPV) | \ 125 - INT_MASK(INT_IDN_ACCESS) | \ 126 - INT_MASK(INT_UDN_ACCESS) | \ 127 - INT_MASK(INT_SWINT_3) | \ 128 - INT_MASK(INT_SWINT_2) | \ 129 - INT_MASK(INT_SWINT_1) | \ 130 - INT_MASK(INT_SWINT_0) | \ 131 - INT_MASK(INT_ILL_TRANS) | \ 132 - INT_MASK(INT_UNALIGN_DATA) | \ 133 - INT_MASK(INT_DTLB_MISS) | \ 134 - INT_MASK(INT_DTLB_ACCESS) | \ 116 + (1ULL << INT_SINGLE_STEP_3) | \ 117 + (1ULL << INT_SINGLE_STEP_2) | \ 118 + (1ULL << INT_SINGLE_STEP_1) | \ 119 + (1ULL << INT_SINGLE_STEP_0) | \ 120 + (1ULL << INT_ITLB_MISS) | \ 121 + (1ULL << INT_ILL) | \ 122 + (1ULL << INT_GPV) | \ 123 + (1ULL << INT_IDN_ACCESS) | \ 124 + (1ULL << INT_UDN_ACCESS) | \ 125 + (1ULL << INT_SWINT_3) | \ 126 + (1ULL << INT_SWINT_2) | \ 127 + (1ULL << INT_SWINT_1) | \ 128 + (1ULL << INT_SWINT_0) | \ 129 + (1ULL << INT_ILL_TRANS) | \ 130 + (1ULL << INT_UNALIGN_DATA) | \ 131 + (1ULL << INT_DTLB_MISS) | \ 132 + (1ULL << INT_DTLB_ACCESS) | \ 135 133 0) 136 134 #define CRITICAL_MASKED_INTERRUPTS ( \ 137 - INT_MASK(INT_MEM_ERROR) | \ 138 - INT_MASK(INT_SINGLE_STEP_3) | \ 139 - INT_MASK(INT_SINGLE_STEP_2) | \ 140 - INT_MASK(INT_SINGLE_STEP_1) | \ 141 - INT_MASK(INT_SINGLE_STEP_0) | \ 142 - INT_MASK(INT_IDN_COMPLETE) | \ 143 - INT_MASK(INT_UDN_COMPLETE) | \ 144 - INT_MASK(INT_IDN_FIREWALL) | \ 145 - INT_MASK(INT_UDN_FIREWALL) | \ 146 - INT_MASK(INT_TILE_TIMER) | \ 147 - INT_MASK(INT_AUX_TILE_TIMER) | \ 148 - INT_MASK(INT_IDN_TIMER) | \ 149 - INT_MASK(INT_UDN_TIMER) | \ 150 - INT_MASK(INT_IDN_AVAIL) | \ 151 - INT_MASK(INT_UDN_AVAIL) | \ 152 - INT_MASK(INT_IPI_3) | \ 153 - INT_MASK(INT_IPI_2) | \ 154 - INT_MASK(INT_IPI_1) | \ 155 - INT_MASK(INT_IPI_0) | \ 156 - INT_MASK(INT_PERF_COUNT) | \ 157 - INT_MASK(INT_AUX_PERF_COUNT) | \ 158 - INT_MASK(INT_INTCTRL_3) | \ 159 - INT_MASK(INT_INTCTRL_2) | \ 160 - INT_MASK(INT_INTCTRL_1) | \ 161 - INT_MASK(INT_INTCTRL_0) | \ 135 + (1ULL << INT_MEM_ERROR) | \ 136 + (1ULL << INT_SINGLE_STEP_3) | \ 137 + (1ULL << INT_SINGLE_STEP_2) | \ 138 + (1ULL << INT_SINGLE_STEP_1) | \ 139 + (1ULL << INT_SINGLE_STEP_0) | \ 140 + (1ULL << INT_IDN_COMPLETE) | \ 141 + (1ULL << INT_UDN_COMPLETE) | \ 142 + (1ULL << INT_IDN_FIREWALL) | \ 143 + (1ULL << INT_UDN_FIREWALL) | \ 144 + (1ULL << INT_TILE_TIMER) | \ 145 + (1ULL << INT_AUX_TILE_TIMER) | \ 146 + (1ULL << INT_IDN_TIMER) | \ 147 + (1ULL << INT_UDN_TIMER) | \ 148 + (1ULL << INT_IDN_AVAIL) | \ 149 + (1ULL << INT_UDN_AVAIL) | \ 150 + (1ULL << INT_IPI_3) | \ 151 + (1ULL << INT_IPI_2) | \ 152 + (1ULL << INT_IPI_1) | \ 153 + (1ULL << INT_IPI_0) | \ 154 + (1ULL << INT_PERF_COUNT) | \ 155 + (1ULL << INT_AUX_PERF_COUNT) | \ 156 + (1ULL << INT_INTCTRL_3) | \ 157 + (1ULL << INT_INTCTRL_2) | \ 158 + (1ULL << INT_INTCTRL_1) | \ 159 + (1ULL << INT_INTCTRL_0) | \ 162 160 0) 163 161 #define CRITICAL_UNMASKED_INTERRUPTS ( \ 164 - INT_MASK(INT_ITLB_MISS) | \ 165 - INT_MASK(INT_ILL) | \ 166 - INT_MASK(INT_GPV) | \ 167 - INT_MASK(INT_IDN_ACCESS) | \ 168 - INT_MASK(INT_UDN_ACCESS) | \ 169 - INT_MASK(INT_SWINT_3) | \ 170 - INT_MASK(INT_SWINT_2) | \ 171 - INT_MASK(INT_SWINT_1) | \ 172 - INT_MASK(INT_SWINT_0) | \ 173 - INT_MASK(INT_ILL_TRANS) | \ 174 - INT_MASK(INT_UNALIGN_DATA) | \ 175 - INT_MASK(INT_DTLB_MISS) | \ 176 - INT_MASK(INT_DTLB_ACCESS) | \ 177 - INT_MASK(INT_BOOT_ACCESS) | \ 178 - INT_MASK(INT_WORLD_ACCESS) | \ 179 - INT_MASK(INT_I_ASID) | \ 180 - INT_MASK(INT_D_ASID) | \ 181 - INT_MASK(INT_DOUBLE_FAULT) | \ 162 + (1ULL << INT_ITLB_MISS) | \ 163 + (1ULL << INT_ILL) | \ 164 + (1ULL << INT_GPV) | \ 165 + (1ULL << INT_IDN_ACCESS) | \ 166 + (1ULL << INT_UDN_ACCESS) | \ 167 + (1ULL << INT_SWINT_3) | \ 168 + (1ULL << INT_SWINT_2) | \ 169 + (1ULL << INT_SWINT_1) | \ 170 + (1ULL << INT_SWINT_0) | \ 171 + (1ULL << INT_ILL_TRANS) | \ 172 + (1ULL << INT_UNALIGN_DATA) | \ 173 + (1ULL << INT_DTLB_MISS) | \ 174 + (1ULL << INT_DTLB_ACCESS) | \ 175 + (1ULL << INT_BOOT_ACCESS) | \ 176 + (1ULL << INT_WORLD_ACCESS) | \ 177 + (1ULL << INT_I_ASID) | \ 178 + (1ULL << INT_D_ASID) | \ 179 + (1ULL << INT_DOUBLE_FAULT) | \ 182 180 0) 183 181 #define MASKABLE_INTERRUPTS ( \ 184 - INT_MASK(INT_MEM_ERROR) | \ 185 - INT_MASK(INT_SINGLE_STEP_3) | \ 186 - INT_MASK(INT_SINGLE_STEP_2) | \ 187 - INT_MASK(INT_SINGLE_STEP_1) | \ 188 - INT_MASK(INT_SINGLE_STEP_0) | \ 189 - INT_MASK(INT_IDN_COMPLETE) | \ 190 - INT_MASK(INT_UDN_COMPLETE) | \ 191 - INT_MASK(INT_IDN_FIREWALL) | \ 192 - INT_MASK(INT_UDN_FIREWALL) | \ 193 - INT_MASK(INT_TILE_TIMER) | \ 194 - INT_MASK(INT_AUX_TILE_TIMER) | \ 195 - INT_MASK(INT_IDN_TIMER) | \ 196 - INT_MASK(INT_UDN_TIMER) | \ 197 - INT_MASK(INT_IDN_AVAIL) | \ 198 - INT_MASK(INT_UDN_AVAIL) | \ 199 - INT_MASK(INT_IPI_3) | \ 200 - INT_MASK(INT_IPI_2) | \ 201 - INT_MASK(INT_IPI_1) | \ 202 - INT_MASK(INT_IPI_0) | \ 203 - INT_MASK(INT_PERF_COUNT) | \ 204 - INT_MASK(INT_AUX_PERF_COUNT) | \ 205 - INT_MASK(INT_INTCTRL_3) | \ 206 - INT_MASK(INT_INTCTRL_2) | \ 207 - INT_MASK(INT_INTCTRL_1) | \ 208 - INT_MASK(INT_INTCTRL_0) | \ 182 + (1ULL << INT_MEM_ERROR) | \ 183 + (1ULL << INT_SINGLE_STEP_3) | \ 184 + (1ULL << INT_SINGLE_STEP_2) | \ 185 + (1ULL << INT_SINGLE_STEP_1) | \ 186 + (1ULL << INT_SINGLE_STEP_0) | \ 187 + (1ULL << INT_IDN_COMPLETE) | \ 188 + (1ULL << INT_UDN_COMPLETE) | \ 189 + (1ULL << INT_IDN_FIREWALL) | \ 190 + (1ULL << INT_UDN_FIREWALL) | \ 191 + (1ULL << INT_TILE_TIMER) | \ 192 + (1ULL << INT_AUX_TILE_TIMER) | \ 193 + (1ULL << INT_IDN_TIMER) | \ 194 + (1ULL << INT_UDN_TIMER) | \ 195 + (1ULL << INT_IDN_AVAIL) | \ 196 + (1ULL << INT_UDN_AVAIL) | \ 197 + (1ULL << INT_IPI_3) | \ 198 + (1ULL << INT_IPI_2) | \ 199 + (1ULL << INT_IPI_1) | \ 200 + (1ULL << INT_IPI_0) | \ 201 + (1ULL << INT_PERF_COUNT) | \ 202 + (1ULL << INT_AUX_PERF_COUNT) | \ 203 + (1ULL << INT_INTCTRL_3) | \ 204 + (1ULL << INT_INTCTRL_2) | \ 205 + (1ULL << INT_INTCTRL_1) | \ 206 + (1ULL << INT_INTCTRL_0) | \ 209 207 0) 210 208 #define UNMASKABLE_INTERRUPTS ( \ 211 - INT_MASK(INT_ITLB_MISS) | \ 212 - INT_MASK(INT_ILL) | \ 213 - INT_MASK(INT_GPV) | \ 214 - INT_MASK(INT_IDN_ACCESS) | \ 215 - INT_MASK(INT_UDN_ACCESS) | \ 216 - INT_MASK(INT_SWINT_3) | \ 217 - INT_MASK(INT_SWINT_2) | \ 218 - INT_MASK(INT_SWINT_1) | \ 219 - INT_MASK(INT_SWINT_0) | \ 220 - INT_MASK(INT_ILL_TRANS) | \ 221 - INT_MASK(INT_UNALIGN_DATA) | \ 222 - INT_MASK(INT_DTLB_MISS) | \ 223 - INT_MASK(INT_DTLB_ACCESS) | \ 224 - INT_MASK(INT_BOOT_ACCESS) | \ 225 - INT_MASK(INT_WORLD_ACCESS) | \ 226 - INT_MASK(INT_I_ASID) | \ 227 - INT_MASK(INT_D_ASID) | \ 228 - INT_MASK(INT_DOUBLE_FAULT) | \ 209 + (1ULL << INT_ITLB_MISS) | \ 210 + (1ULL << INT_ILL) | \ 211 + (1ULL << INT_GPV) | \ 212 + (1ULL << INT_IDN_ACCESS) | \ 213 + (1ULL << INT_UDN_ACCESS) | \ 214 + (1ULL << INT_SWINT_3) | \ 215 + (1ULL << INT_SWINT_2) | \ 216 + (1ULL << INT_SWINT_1) | \ 217 + (1ULL << INT_SWINT_0) | \ 218 + (1ULL << INT_ILL_TRANS) | \ 219 + (1ULL << INT_UNALIGN_DATA) | \ 220 + (1ULL << INT_DTLB_MISS) | \ 221 + (1ULL << INT_DTLB_ACCESS) | \ 222 + (1ULL << INT_BOOT_ACCESS) | \ 223 + (1ULL << INT_WORLD_ACCESS) | \ 224 + (1ULL << INT_I_ASID) | \ 225 + (1ULL << INT_D_ASID) | \ 226 + (1ULL << INT_DOUBLE_FAULT) | \ 229 227 0) 230 228 #define SYNC_INTERRUPTS ( \ 231 - INT_MASK(INT_SINGLE_STEP_3) | \ 232 - INT_MASK(INT_SINGLE_STEP_2) | \ 233 - INT_MASK(INT_SINGLE_STEP_1) | \ 234 - INT_MASK(INT_SINGLE_STEP_0) | \ 235 - INT_MASK(INT_IDN_COMPLETE) | \ 236 - INT_MASK(INT_UDN_COMPLETE) | \ 237 - INT_MASK(INT_ITLB_MISS) | \ 238 - INT_MASK(INT_ILL) | \ 239 - INT_MASK(INT_GPV) | \ 240 - INT_MASK(INT_IDN_ACCESS) | \ 241 - INT_MASK(INT_UDN_ACCESS) | \ 242 - INT_MASK(INT_SWINT_3) | \ 243 - INT_MASK(INT_SWINT_2) | \ 244 - INT_MASK(INT_SWINT_1) | \ 245 - INT_MASK(INT_SWINT_0) | \ 246 - INT_MASK(INT_ILL_TRANS) | \ 247 - INT_MASK(INT_UNALIGN_DATA) | \ 248 - INT_MASK(INT_DTLB_MISS) | \ 249 - INT_MASK(INT_DTLB_ACCESS) | \ 229 + (1ULL << INT_SINGLE_STEP_3) | \ 230 + (1ULL << INT_SINGLE_STEP_2) | \ 231 + (1ULL << INT_SINGLE_STEP_1) | \ 232 + (1ULL << INT_SINGLE_STEP_0) | \ 233 + (1ULL << INT_IDN_COMPLETE) | \ 234 + (1ULL << INT_UDN_COMPLETE) | \ 235 + (1ULL << INT_ITLB_MISS) | \ 236 + (1ULL << INT_ILL) | \ 237 + (1ULL << INT_GPV) | \ 238 + (1ULL << INT_IDN_ACCESS) | \ 239 + (1ULL << INT_UDN_ACCESS) | \ 240 + (1ULL << INT_SWINT_3) | \ 241 + (1ULL << INT_SWINT_2) | \ 242 + (1ULL << INT_SWINT_1) | \ 243 + (1ULL << INT_SWINT_0) | \ 244 + (1ULL << INT_ILL_TRANS) | \ 245 + (1ULL << INT_UNALIGN_DATA) | \ 246 + (1ULL << INT_DTLB_MISS) | \ 247 + (1ULL << INT_DTLB_ACCESS) | \ 250 248 0) 251 249 #define NON_SYNC_INTERRUPTS ( \ 252 - INT_MASK(INT_MEM_ERROR) | \ 253 - INT_MASK(INT_IDN_FIREWALL) | \ 254 - INT_MASK(INT_UDN_FIREWALL) | \ 255 - INT_MASK(INT_TILE_TIMER) | \ 256 - INT_MASK(INT_AUX_TILE_TIMER) | \ 257 - INT_MASK(INT_IDN_TIMER) | \ 258 - INT_MASK(INT_UDN_TIMER) | \ 259 - INT_MASK(INT_IDN_AVAIL) | \ 260 - INT_MASK(INT_UDN_AVAIL) | \ 261 - INT_MASK(INT_IPI_3) | \ 262 - INT_MASK(INT_IPI_2) | \ 263 - INT_MASK(INT_IPI_1) | \ 264 - INT_MASK(INT_IPI_0) | \ 265 - INT_MASK(INT_PERF_COUNT) | \ 266 - INT_MASK(INT_AUX_PERF_COUNT) | \ 267 - INT_MASK(INT_INTCTRL_3) | \ 268 - INT_MASK(INT_INTCTRL_2) | \ 269 - INT_MASK(INT_INTCTRL_1) | \ 270 - INT_MASK(INT_INTCTRL_0) | \ 271 - INT_MASK(INT_BOOT_ACCESS) | \ 272 - INT_MASK(INT_WORLD_ACCESS) | \ 273 - INT_MASK(INT_I_ASID) | \ 274 - INT_MASK(INT_D_ASID) | \ 275 - INT_MASK(INT_DOUBLE_FAULT) | \ 250 + (1ULL << INT_MEM_ERROR) | \ 251 + (1ULL << INT_IDN_FIREWALL) | \ 252 + (1ULL << INT_UDN_FIREWALL) | \ 253 + (1ULL << INT_TILE_TIMER) | \ 254 + (1ULL << INT_AUX_TILE_TIMER) | \ 255 + (1ULL << INT_IDN_TIMER) | \ 256 + (1ULL << INT_UDN_TIMER) | \ 257 + (1ULL << INT_IDN_AVAIL) | \ 258 + (1ULL << INT_UDN_AVAIL) | \ 259 + (1ULL << INT_IPI_3) | \ 260 + (1ULL << INT_IPI_2) | \ 261 + (1ULL << INT_IPI_1) | \ 262 + (1ULL << INT_IPI_0) | \ 263 + (1ULL << INT_PERF_COUNT) | \ 264 + (1ULL << INT_AUX_PERF_COUNT) | \ 265 + (1ULL << INT_INTCTRL_3) | \ 266 + (1ULL << INT_INTCTRL_2) | \ 267 + (1ULL << INT_INTCTRL_1) | \ 268 + (1ULL << INT_INTCTRL_0) | \ 269 + (1ULL << INT_BOOT_ACCESS) | \ 270 + (1ULL << INT_WORLD_ACCESS) | \ 271 + (1ULL << INT_I_ASID) | \ 272 + (1ULL << INT_D_ASID) | \ 273 + (1ULL << INT_DOUBLE_FAULT) | \ 276 274 0) 277 275 #endif /* !__ASSEMBLER__ */ 278 276 #endif /* !__ARCH_INTERRUPTS_H__ */
+4
arch/tile/kernel/intvec_64.S
··· 1035 1035 /* Ensure that the syscall number is within the legal range. */ 1036 1036 { 1037 1037 moveli r20, hw2(sys_call_table) 1038 + #ifdef CONFIG_COMPAT 1038 1039 blbs r30, .Lcompat_syscall 1040 + #endif 1039 1041 } 1040 1042 { 1041 1043 cmpltu r21, TREG_SYSCALL_NR_NAME, r21 ··· 1095 1093 j .Lresume_userspace /* jump into middle of interrupt_return */ 1096 1094 } 1097 1095 1096 + #ifdef CONFIG_COMPAT 1098 1097 .Lcompat_syscall: 1099 1098 /* 1100 1099 * Load the base of the compat syscall table in r20, and ··· 1120 1117 { move r15, r4; addxi r4, r4, 0 } 1121 1118 { move r16, r5; addxi r5, r5, 0 } 1122 1119 j .Lload_syscall_pointer 1120 + #endif 1123 1121 1124 1122 .Linvalid_syscall: 1125 1123 /* Report an invalid syscall back to the user program */
+1 -1
arch/tile/kernel/process.c
··· 159 159 int copy_thread(unsigned long clone_flags, unsigned long sp, 160 160 unsigned long arg, struct task_struct *p) 161 161 { 162 - struct pt_regs *childregs = task_pt_regs(p), *regs = current_pt_regs(); 162 + struct pt_regs *childregs = task_pt_regs(p); 163 163 unsigned long ksp; 164 164 unsigned long *callee_regs; 165 165
+2
arch/tile/kernel/reboot.c
··· 16 16 #include <linux/reboot.h> 17 17 #include <linux/smp.h> 18 18 #include <linux/pm.h> 19 + #include <linux/export.h> 19 20 #include <asm/page.h> 20 21 #include <asm/setup.h> 21 22 #include <hv/hypervisor.h> ··· 50 49 51 50 /* No interesting distinction to be made here. */ 52 51 void (*pm_power_off)(void) = NULL; 52 + EXPORT_SYMBOL(pm_power_off);
+5
arch/tile/kernel/setup.c
··· 31 31 #include <linux/timex.h> 32 32 #include <linux/hugetlb.h> 33 33 #include <linux/start_kernel.h> 34 + #include <linux/screen_info.h> 34 35 #include <asm/setup.h> 35 36 #include <asm/sections.h> 36 37 #include <asm/cacheflush.h> ··· 49 48 50 49 /* Chip information */ 51 50 char chip_model[64] __write_once; 51 + 52 + #ifdef CONFIG_VT 53 + struct screen_info screen_info; 54 + #endif 52 55 53 56 struct pglist_data node_data[MAX_NUMNODES] __read_mostly; 54 57 EXPORT_SYMBOL(node_data);
+2 -1
arch/tile/kernel/stack.c
··· 112 112 p->pc, p->sp, p->ex1); 113 113 p = NULL; 114 114 } 115 - if (!kbt->profile || (INT_MASK(p->faultnum) & QUEUED_INTERRUPTS) == 0) 115 + if (!kbt->profile || ((1ULL << p->faultnum) & QUEUED_INTERRUPTS) == 0) 116 116 return p; 117 117 return NULL; 118 118 } ··· 484 484 { 485 485 save_stack_trace_tsk(NULL, trace); 486 486 } 487 + EXPORT_SYMBOL_GPL(save_stack_trace); 487 488 488 489 #endif 489 490
+2
arch/tile/lib/cacheflush.c
··· 12 12 * more details. 13 13 */ 14 14 15 + #include <linux/export.h> 15 16 #include <asm/page.h> 16 17 #include <asm/cacheflush.h> 17 18 #include <arch/icache.h> ··· 166 165 __insn_mtspr(SPR_DSTREAM_PF, old_dstream_pf); 167 166 #endif 168 167 } 168 + EXPORT_SYMBOL_GPL(finv_buffer_remote);
+2
arch/tile/lib/cpumask.c
··· 16 16 #include <linux/ctype.h> 17 17 #include <linux/errno.h> 18 18 #include <linux/smp.h> 19 + #include <linux/export.h> 19 20 20 21 /* 21 22 * Allow cropping out bits beyond the end of the array. ··· 51 50 } while (*bp != '\0' && *bp != '\n'); 52 51 return 0; 53 52 } 53 + EXPORT_SYMBOL(bitmap_parselist_crop);
+2
arch/tile/lib/exports.c
··· 55 55 EXPORT_SYMBOL(hv_dev_close); 56 56 EXPORT_SYMBOL(hv_sysconf); 57 57 EXPORT_SYMBOL(hv_confstr); 58 + EXPORT_SYMBOL(hv_get_rtc); 59 + EXPORT_SYMBOL(hv_set_rtc); 58 60 59 61 /* libgcc.a */ 60 62 uint32_t __udivsi3(uint32_t dividend, uint32_t divisor);
+1
arch/tile/mm/homecache.c
··· 408 408 __set_pte(ptep, pte_set_home(pteval, home)); 409 409 } 410 410 } 411 + EXPORT_SYMBOL(homecache_change_page_home); 411 412 412 413 struct page *homecache_alloc_pages(gfp_t gfp_mask, 413 414 unsigned int order, int home)
+1
drivers/gpu/drm/nouveau/nouveau_bo.c
··· 28 28 */ 29 29 30 30 #include <core/engine.h> 31 + #include <linux/swiotlb.h> 31 32 32 33 #include <subdev/fb.h> 33 34 #include <subdev/vm.h>
+1
drivers/gpu/drm/radeon/radeon_ttm.c
··· 38 38 #include <drm/radeon_drm.h> 39 39 #include <linux/seq_file.h> 40 40 #include <linux/slab.h> 41 + #include <linux/swiotlb.h> 41 42 #include "radeon_reg.h" 42 43 #include "radeon.h" 43 44
+1 -1
drivers/input/joystick/analog.c
··· 162 162 #define GET_TIME(x) do { x = get_cycles(); } while (0) 163 163 #define DELTA(x,y) ((y)-(x)) 164 164 #define TIME_NAME "PCC" 165 - #elif defined(CONFIG_MN10300) 165 + #elif defined(CONFIG_MN10300) || defined(CONFIG_TILE) 166 166 #define GET_TIME(x) do { x = get_cycles(); } while (0) 167 167 #define DELTA(x, y) ((x) - (y)) 168 168 #define TIME_NAME "TSC"