Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
drm/radeon/kms: add FireMV 2400 PCI ID.
drm/radeon/kms: allow R500 regs VAP_ALT_NUM_VERTICES and VAP_INDEX_OFFSET
drivers/gpu/radeon: Add MSPOS regs to safe list.
drm/radeon/kms: disable the tv encoder when tv/cv is not in use
drm/radeon/kms: adjust pll settings for tv
drm/radeon/kms: fix tv dac conflict resolver
drm/radeon/kms/evergreen: don't enable hdmi audio stuff
drm/radeon/kms/atom: fix dual-link DVI on DCE3.2/4.0
drm/radeon/kms: fix rs600 tlb flush
drm/radeon/kms: print GPU family and device id when loading
drm/radeon/kms: fix calculation of mipmapped 3D texture sizes
drm/radeon/kms: only change mode when coherent value changes.
drm/radeon/kms: more atom parser fixes (v2)
+139
-19
+10
drivers/gpu/drm/radeon/atom.c
+10
drivers/gpu/drm/radeon/atom.c
···
908
908
uint8_t attr = U8((*ptr)++), shift;
909
909
uint32_t saved, dst;
910
910
int dptr = *ptr;
911
+
uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
911
912
SDEBUG(" dst: ");
912
913
dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
914
+
/* op needs to full dst value */
915
+
dst = saved;
913
916
shift = atom_get_src(ctx, attr, ptr);
914
917
SDEBUG(" shift: %d\n", shift);
915
918
dst <<= shift;
919
+
dst &= atom_arg_mask[dst_align];
920
+
dst >>= atom_arg_shift[dst_align];
916
921
SDEBUG(" dst: ");
917
922
atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
918
923
}
···
927
922
uint8_t attr = U8((*ptr)++), shift;
928
923
uint32_t saved, dst;
929
924
int dptr = *ptr;
925
+
uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
930
926
SDEBUG(" dst: ");
931
927
dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
928
+
/* op needs to full dst value */
929
+
dst = saved;
932
930
shift = atom_get_src(ctx, attr, ptr);
933
931
SDEBUG(" shift: %d\n", shift);
934
932
dst >>= shift;
933
+
dst &= atom_arg_mask[dst_align];
934
+
dst >>= atom_arg_shift[dst_align];
935
935
SDEBUG(" dst: ");
936
936
atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
937
937
}
+4
drivers/gpu/drm/radeon/atombios_crtc.c
+4
drivers/gpu/drm/radeon/atombios_crtc.c
···
521
521
/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
522
522
if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
523
523
adjusted_clock = mode->clock * 2;
524
+
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
525
+
pll->algo = PLL_ALGO_LEGACY;
526
+
pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
527
+
}
524
528
} else {
525
529
if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
526
530
pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
+15
-6
drivers/gpu/drm/radeon/r100.c
+15
-6
drivers/gpu/drm/radeon/r100.c
···
2891
2891
{
2892
2892
struct radeon_bo *robj;
2893
2893
unsigned long size;
2894
-
unsigned u, i, w, h;
2894
+
unsigned u, i, w, h, d;
2895
2895
int ret;
2896
2896
2897
2897
for (u = 0; u < track->num_texture; u++) {
···
2923
2923
h = h / (1 << i);
2924
2924
if (track->textures[u].roundup_h)
2925
2925
h = roundup_pow_of_two(h);
2926
+
if (track->textures[u].tex_coord_type == 1) {
2927
+
d = (1 << track->textures[u].txdepth) / (1 << i);
2928
+
if (!d)
2929
+
d = 1;
2930
+
} else {
2931
+
d = 1;
2932
+
}
2926
2933
if (track->textures[u].compress_format) {
2927
2934
2928
-
size += r100_track_compress_size(track->textures[u].compress_format, w, h);
2935
+
size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2929
2936
/* compressed textures are block based */
2930
2937
} else
2931
-
size += w * h;
2938
+
size += w * h * d;
2932
2939
}
2933
2940
size *= track->textures[u].cpp;
2934
2941
2935
2942
switch (track->textures[u].tex_coord_type) {
2936
2943
case 0:
2937
-
break;
2938
2944
case 1:
2939
-
size *= (1 << track->textures[u].txdepth);
2940
2945
break;
2941
2946
case 2:
2942
2947
if (track->separate_cube) {
···
3012
3007
}
3013
3008
}
3014
3009
prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3015
-
nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3010
+
if (track->vap_vf_cntl & (1 << 14)) {
3011
+
nverts = track->vap_alt_nverts;
3012
+
} else {
3013
+
nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3014
+
}
3016
3015
switch (prim_walk) {
3017
3016
case 1:
3018
3017
for (i = 0; i < track->num_arrays; i++) {
+1
drivers/gpu/drm/radeon/r100_track.h
+1
drivers/gpu/drm/radeon/r100_track.h
+11
-4
drivers/gpu/drm/radeon/r300.c
+11
-4
drivers/gpu/drm/radeon/r300.c
···
730
730
/* VAP_VF_MAX_VTX_INDX */
731
731
track->max_indx = idx_value & 0x00FFFFFFUL;
732
732
break;
733
+
case 0x2088:
734
+
/* VAP_ALT_NUM_VERTICES - only valid on r500 */
735
+
if (p->rdev->family < CHIP_RV515)
736
+
goto fail;
737
+
track->vap_alt_nverts = idx_value & 0xFFFFFF;
738
+
break;
733
739
case 0x43E4:
734
740
/* SC_SCISSOR1 */
735
741
track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
···
773
767
tmp = idx_value & ~(0x7 << 16);
774
768
tmp |= tile_flags;
775
769
ib[idx] = tmp;
776
-
777
770
i = (reg - 0x4E38) >> 2;
778
771
track->cb[i].pitch = idx_value & 0x3FFE;
779
772
switch (((idx_value >> 21) & 0xF)) {
···
1057
1052
break;
1058
1053
/* fallthrough do not move */
1059
1054
default:
1060
-
printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1061
-
reg, idx);
1062
-
return -EINVAL;
1055
+
goto fail;
1063
1056
}
1064
1057
return 0;
1058
+
fail:
1059
+
printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1060
+
reg, idx);
1061
+
return -EINVAL;
1065
1062
}
1066
1063
1067
1064
static int r300_packet3_check(struct radeon_cs_parser *p,
+1
-1
drivers/gpu/drm/radeon/r600_audio.c
+1
-1
drivers/gpu/drm/radeon/r600_audio.c
···
35
35
*/
36
36
static int r600_audio_chipset_supported(struct radeon_device *rdev)
37
37
{
38
-
return rdev->family >= CHIP_R600
38
+
return (rdev->family >= CHIP_R600 && rdev->family < CHIP_CEDAR)
39
39
|| rdev->family == CHIP_RS600
40
40
|| rdev->family == CHIP_RS690
41
41
|| rdev->family == CHIP_RS740;
+9
drivers/gpu/drm/radeon/r600_hdmi.c
+9
drivers/gpu/drm/radeon/r600_hdmi.c
···
314
314
struct radeon_device *rdev = dev->dev_private;
315
315
uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
316
316
317
+
if (ASIC_IS_DCE4(rdev))
318
+
return;
319
+
317
320
if (!offset)
318
321
return;
319
322
···
487
484
struct radeon_device *rdev = dev->dev_private;
488
485
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
489
486
487
+
if (ASIC_IS_DCE4(rdev))
488
+
return;
489
+
490
490
if (!radeon_encoder->hdmi_offset) {
491
491
r600_hdmi_assign_block(encoder);
492
492
if (!radeon_encoder->hdmi_offset) {
···
530
524
struct drm_device *dev = encoder->dev;
531
525
struct radeon_device *rdev = dev->dev_private;
532
526
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
527
+
528
+
if (ASIC_IS_DCE4(rdev))
529
+
return;
533
530
534
531
if (!radeon_encoder->hdmi_offset) {
535
532
dev_err(rdev->dev, "Disabling not enabled HDMI\n");
+11
-2
drivers/gpu/drm/radeon/radeon_connectors.c
+11
-2
drivers/gpu/drm/radeon/radeon_connectors.c
···
162
162
{
163
163
struct drm_device *dev = connector->dev;
164
164
struct drm_connector *conflict;
165
+
struct radeon_connector *radeon_conflict;
165
166
int i;
166
167
167
168
list_for_each_entry(conflict, &dev->mode_config.connector_list, head) {
168
169
if (conflict == connector)
169
170
continue;
170
171
172
+
radeon_conflict = to_radeon_connector(conflict);
171
173
for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
172
174
if (conflict->encoder_ids[i] == 0)
173
175
break;
···
177
175
/* if the IDs match */
178
176
if (conflict->encoder_ids[i] == encoder->base.id) {
179
177
if (conflict->status != connector_status_connected)
178
+
continue;
179
+
180
+
if (radeon_conflict->use_digital)
180
181
continue;
181
182
182
183
if (priority == true) {
···
292
287
293
288
if (property == rdev->mode_info.coherent_mode_property) {
294
289
struct radeon_encoder_atom_dig *dig;
290
+
bool new_coherent_mode;
295
291
296
292
/* need to find digital encoder on connector */
297
293
encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
···
305
299
return 0;
306
300
307
301
dig = radeon_encoder->enc_priv;
308
-
dig->coherent_mode = val ? true : false;
309
-
radeon_property_change_mode(&radeon_encoder->base);
302
+
new_coherent_mode = val ? true : false;
303
+
if (dig->coherent_mode != new_coherent_mode) {
304
+
dig->coherent_mode = new_coherent_mode;
305
+
radeon_property_change_mode(&radeon_encoder->base);
306
+
}
310
307
}
311
308
312
309
if (property == rdev->mode_info.tv_std_property) {
+52
-1
drivers/gpu/drm/radeon/radeon_device.c
+52
-1
drivers/gpu/drm/radeon/radeon_device.c
···
36
36
#include "radeon.h"
37
37
#include "atom.h"
38
38
39
+
static const char radeon_family_name[][16] = {
40
+
"R100",
41
+
"RV100",
42
+
"RS100",
43
+
"RV200",
44
+
"RS200",
45
+
"R200",
46
+
"RV250",
47
+
"RS300",
48
+
"RV280",
49
+
"R300",
50
+
"R350",
51
+
"RV350",
52
+
"RV380",
53
+
"R420",
54
+
"R423",
55
+
"RV410",
56
+
"RS400",
57
+
"RS480",
58
+
"RS600",
59
+
"RS690",
60
+
"RS740",
61
+
"RV515",
62
+
"R520",
63
+
"RV530",
64
+
"RV560",
65
+
"RV570",
66
+
"R580",
67
+
"R600",
68
+
"RV610",
69
+
"RV630",
70
+
"RV670",
71
+
"RV620",
72
+
"RV635",
73
+
"RS780",
74
+
"RS880",
75
+
"RV770",
76
+
"RV730",
77
+
"RV710",
78
+
"RV740",
79
+
"CEDAR",
80
+
"REDWOOD",
81
+
"JUNIPER",
82
+
"CYPRESS",
83
+
"HEMLOCK",
84
+
"LAST",
85
+
};
86
+
39
87
/*
40
88
* Clear GPU surface registers.
41
89
*/
···
574
526
int r;
575
527
int dma_bits;
576
528
577
-
DRM_INFO("radeon: Initializing kernel modesetting.\n");
578
529
rdev->shutdown = false;
579
530
rdev->dev = &pdev->dev;
580
531
rdev->ddev = ddev;
···
585
538
rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
586
539
rdev->gpu_lockup = false;
587
540
rdev->accel_working = false;
541
+
542
+
DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n",
543
+
radeon_family_name[rdev->family], pdev->vendor, pdev->device);
544
+
588
545
/* mutex initialization are all done here so we
589
546
* can recall function without having locking issues */
590
547
mutex_init(&rdev->cs_mutex);
+2
-1
drivers/gpu/drm/radeon/radeon_drv.c
+2
-1
drivers/gpu/drm/radeon/radeon_drv.c
···
43
43
* - 2.0.0 - initial interface
44
44
* - 2.1.0 - add square tiling interface
45
45
* - 2.2.0 - add r6xx/r7xx const buffer support
46
+
* - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
46
47
*/
47
48
#define KMS_DRIVER_MAJOR 2
48
-
#define KMS_DRIVER_MINOR 2
49
+
#define KMS_DRIVER_MINOR 3
49
50
#define KMS_DRIVER_PATCHLEVEL 0
50
51
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
51
52
int radeon_driver_unload_kms(struct drm_device *dev);
+10
-2
drivers/gpu/drm/radeon/radeon_encoders.c
+10
-2
drivers/gpu/drm/radeon/radeon_encoders.c
···
865
865
else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
866
866
if (dig->coherent_mode)
867
867
args.v3.acConfig.fCoherentMode = 1;
868
+
if (radeon_encoder->pixel_clock > 165000)
869
+
args.v3.acConfig.fDualLinkConnector = 1;
868
870
}
869
871
} else if (ASIC_IS_DCE32(rdev)) {
870
872
args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
···
890
888
else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
891
889
if (dig->coherent_mode)
892
890
args.v2.acConfig.fCoherentMode = 1;
891
+
if (radeon_encoder->pixel_clock > 165000)
892
+
args.v2.acConfig.fDualLinkConnector = 1;
893
893
}
894
894
} else {
895
895
args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
···
1377
1373
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1378
1374
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1379
1375
atombios_dac_setup(encoder, ATOM_ENABLE);
1380
-
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1381
-
atombios_tv_setup(encoder, ATOM_ENABLE);
1376
+
if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1377
+
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1378
+
atombios_tv_setup(encoder, ATOM_ENABLE);
1379
+
else
1380
+
atombios_tv_setup(encoder, ATOM_DISABLE);
1381
+
}
1382
1382
break;
1383
1383
}
1384
1384
atombios_apply_encoder_quirks(encoder, adjusted_mode);
+2
-1
drivers/gpu/drm/radeon/radeon_family.h
+2
-1
drivers/gpu/drm/radeon/radeon_family.h
+2
drivers/gpu/drm/radeon/reg_srcs/r300
+2
drivers/gpu/drm/radeon/reg_srcs/r300
+2
drivers/gpu/drm/radeon/reg_srcs/r420
+2
drivers/gpu/drm/radeon/reg_srcs/r420
+2
drivers/gpu/drm/radeon/reg_srcs/rs600
+2
drivers/gpu/drm/radeon/reg_srcs/rs600
+3
drivers/gpu/drm/radeon/reg_srcs/rv515
+3
drivers/gpu/drm/radeon/reg_srcs/rv515
···
35
35
0x1DA8 VAP_VPORT_ZSCALE
36
36
0x1DAC VAP_VPORT_ZOFFSET
37
37
0x2080 VAP_CNTL
38
+
0x208C VAP_INDEX_OFFSET
38
39
0x2090 VAP_OUT_VTX_FMT_0
39
40
0x2094 VAP_OUT_VTX_FMT_1
40
41
0x20B0 VAP_VTE_CNTL
···
159
158
0x4000 GB_VAP_RASTER_VTX_FMT_0
160
159
0x4004 GB_VAP_RASTER_VTX_FMT_1
161
160
0x4008 GB_ENABLE
161
+
0x4010 GB_MSPOS0
162
+
0x4014 GB_MSPOS1
162
163
0x401C GB_SELECT
163
164
0x4020 GB_AA_CONFIG
164
165
0x4024 GB_FIFO_SIZE
+1
-1
drivers/gpu/drm/radeon/rs600.c
+1
-1
drivers/gpu/drm/radeon/rs600.c
···
159
159
WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
160
160
161
161
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
162
-
tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
162
+
tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
163
163
WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
164
164
165
165
tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
+1
include/drm/drm_pciids.h
+1
include/drm/drm_pciids.h
···
6
6
{0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
7
7
{0x1002, 0x3152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
8
8
{0x1002, 0x3154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
9
+
{0x1002, 0x3155, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
9
10
{0x1002, 0x3E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
10
11
{0x1002, 0x3E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
11
12
{0x1002, 0x4136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP}, \