tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm: atmel-hlcdc: Define XLCDC specific registers

The register address of the XLCDC IP used in SAM9X7 SoC family
are different from the previous HLCDC. Defining those address
space with valid macros.

Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
[manikandan.m@microchip.com: Remove unused macro definitions]
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Acked-by: Lee Jones <lee@kernel.org>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240424053351.589830-3-manikandan.m@microchip.com

authored by

Durai Manickam KR and committed by
Sam Ravnborg 73fc9753 aa71584b

+52
+42
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
··· 15 15 16 16 #include <drm/drm_plane.h> 17 17 18 + /* LCD controller common registers */ 18 19 #define ATMEL_HLCDC_LAYER_CHER 0x0 19 20 #define ATMEL_HLCDC_LAYER_CHDR 0x4 20 21 #define ATMEL_HLCDC_LAYER_CHSR 0x8 ··· 128 127 #define ATMEL_HLCDC_CLUT_SIZE 256 129 128 130 129 #define ATMEL_HLCDC_MAX_LAYERS 6 130 + 131 + /* XLCDC controller specific registers */ 132 + #define ATMEL_XLCDC_LAYER_ENR 0x10 133 + #define ATMEL_XLCDC_LAYER_EN BIT(0) 134 + 135 + #define ATMEL_XLCDC_LAYER_IER 0x0 136 + #define ATMEL_XLCDC_LAYER_IDR 0x4 137 + #define ATMEL_XLCDC_LAYER_ISR 0xc 138 + #define ATMEL_XLCDC_LAYER_OVR_IRQ(p) BIT(2 + (8 * (p))) 139 + 140 + #define ATMEL_XLCDC_LAYER_PLANE_ADDR(p) (((p) * 0x4) + 0x18) 141 + 142 + #define ATMEL_XLCDC_LAYER_DMA_CFG 0 143 + 144 + #define ATMEL_XLCDC_LAYER_DMA BIT(0) 145 + #define ATMEL_XLCDC_LAYER_REP BIT(1) 146 + #define ATMEL_XLCDC_LAYER_DISCEN BIT(4) 147 + 148 + #define ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AS (4 << 6) 149 + #define ATMEL_XLCDC_LAYER_SFACTA_ONE BIT(9) 150 + #define ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AS (6 << 11) 151 + #define ATMEL_XLCDC_LAYER_DFACTA_ONE BIT(14) 152 + 153 + #define ATMEL_XLCDC_LAYER_A0_SHIFT 16 154 + #define ATMEL_XLCDC_LAYER_A0(x) \ 155 + ((x) << ATMEL_XLCDC_LAYER_A0_SHIFT) 156 + 157 + #define ATMEL_XLCDC_LAYER_VSCALER_LUMA_ENABLE BIT(0) 158 + #define ATMEL_XLCDC_LAYER_VSCALER_CHROMA_ENABLE BIT(1) 159 + #define ATMEL_XLCDC_LAYER_HSCALER_LUMA_ENABLE BIT(4) 160 + #define ATMEL_XLCDC_LAYER_HSCALER_CHROMA_ENABLE BIT(5) 161 + 162 + #define ATMEL_XLCDC_LAYER_VXSYCFG_ONE BIT(0) 163 + #define ATMEL_XLCDC_LAYER_VXSYTAP2_ENABLE BIT(4) 164 + #define ATMEL_XLCDC_LAYER_VXSCCFG_ONE BIT(16) 165 + #define ATMEL_XLCDC_LAYER_VXSCTAP2_ENABLE BIT(20) 166 + 167 + #define ATMEL_XLCDC_LAYER_HXSYCFG_ONE BIT(0) 168 + #define ATMEL_XLCDC_LAYER_HXSYTAP2_ENABLE BIT(4) 169 + #define ATMEL_XLCDC_LAYER_HXSCCFG_ONE BIT(16) 170 + #define ATMEL_XLCDC_LAYER_HXSCTAP2_ENABLE BIT(20) 131 171 132 172 /** 133 173 * Atmel HLCDC Layer registers layout structure
+10
include/linux/mfd/atmel-hlcdc.h
··· 22 22 #define ATMEL_HLCDC_DITHER BIT(6) 23 23 #define ATMEL_HLCDC_DISPDLY BIT(7) 24 24 #define ATMEL_HLCDC_MODE_MASK GENMASK(9, 8) 25 + #define ATMEL_XLCDC_MODE_MASK GENMASK(10, 8) 26 + #define ATMEL_XLCDC_DPI BIT(11) 25 27 #define ATMEL_HLCDC_PP BIT(10) 26 28 #define ATMEL_HLCDC_VSPSU BIT(12) 27 29 #define ATMEL_HLCDC_VSPHO BIT(13) ··· 36 34 #define ATMEL_HLCDC_IDR 0x30 37 35 #define ATMEL_HLCDC_IMR 0x34 38 36 #define ATMEL_HLCDC_ISR 0x38 37 + #define ATMEL_XLCDC_ATTRE 0x3c 38 + 39 + #define ATMEL_XLCDC_BASE_UPDATE BIT(0) 40 + #define ATMEL_XLCDC_OVR1_UPDATE BIT(1) 41 + #define ATMEL_XLCDC_OVR3_UPDATE BIT(2) 42 + #define ATMEL_XLCDC_HEO_UPDATE BIT(3) 39 43 40 44 #define ATMEL_HLCDC_CLKPOL BIT(0) 41 45 #define ATMEL_HLCDC_CLKSEL BIT(2) ··· 56 48 #define ATMEL_HLCDC_DISP BIT(2) 57 49 #define ATMEL_HLCDC_PWM BIT(3) 58 50 #define ATMEL_HLCDC_SIP BIT(4) 51 + #define ATMEL_XLCDC_SD BIT(5) 52 + #define ATMEL_XLCDC_CM BIT(6) 59 53 60 54 #define ATMEL_HLCDC_SOF BIT(0) 61 55 #define ATMEL_HLCDC_SYNCDIS BIT(1)