Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pinctrl: spacemit: k3: add initial pin support
For the pinctrl IP of SpacemiT's K3 SoC, it has different register offset
comparing with previous SoC generation, so introduce a function to do the
pin to offset mapping. Also add all the pinctrl data.
Signed-off-by: Yixun Lan <dlan@gentoo.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
authored by
Yixun Lan
and committed by
Linus Walleij
7412311c
5adaa1a8
+352
-6
+2
-2
drivers/pinctrl/spacemit/Kconfig
+2
-2
drivers/pinctrl/spacemit/Kconfig
···
4
4
#
5
5
6
6
config PINCTRL_SPACEMIT_K1
7
-
bool "SpacemiT K1 SoC Pinctrl driver"
7
+
bool "SpacemiT K1/K3 SoC Pinctrl driver"
8
8
depends on ARCH_SPACEMIT || COMPILE_TEST
9
9
depends on OF
10
10
default ARCH_SPACEMIT
···
12
12
select GENERIC_PINMUX_FUNCTIONS
13
13
select GENERIC_PINCONF
14
14
help
15
-
Say Y to select the pinctrl driver for K1 SoC.
15
+
Say Y to select the pinctrl driver for K1/K3 SoC.
16
16
This pin controller allows selecting the mux function for
17
17
each pin. This driver can also be built as a module called
18
18
pinctrl-k1.
+350
-4
drivers/pinctrl/spacemit/pinctrl-k1.c
+350
-4
drivers/pinctrl/spacemit/pinctrl-k1.c
···
66
66
const struct pinctrl_pin_desc *pins;
67
67
const struct spacemit_pin *data;
68
68
u16 npins;
69
+
unsigned int (*pin_to_offset)(unsigned int pin);
69
70
};
70
71
71
72
struct spacemit_pin_mux_config {
···
80
79
};
81
80
82
81
/* map pin id to pinctrl register offset, refer MFPR definition */
83
-
static unsigned int spacemit_pin_to_offset(unsigned int pin)
82
+
static unsigned int spacemit_k1_pin_to_offset(unsigned int pin)
84
83
{
85
84
unsigned int offset = 0;
86
85
···
125
124
return offset << 2;
126
125
}
127
126
127
+
static unsigned int spacemit_k3_pin_to_offset(unsigned int pin)
128
+
{
129
+
unsigned int offset = pin > 130 ? (pin + 2) : pin;
130
+
131
+
return offset << 2;
132
+
}
133
+
128
134
static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl,
129
135
unsigned int pin)
130
136
{
131
-
return pctrl->regs + spacemit_pin_to_offset(pin);
137
+
return pctrl->regs + pctrl->data->pin_to_offset(pin);
132
138
}
133
139
134
140
static u16 spacemit_dt_get_pin(u32 value)
···
185
177
void __iomem *reg;
186
178
u32 value;
187
179
188
-
seq_printf(seq, "offset: 0x%04x ", spacemit_pin_to_offset(pin));
180
+
seq_printf(seq, "offset: 0x%04x ", pctrl->data->pin_to_offset(pin));
189
181
seq_printf(seq, "type: %s ", io_type_desc[type]);
190
182
191
183
reg = spacemit_pin_to_reg(pctrl, pin);
···
1050
1042
.pins = k1_pin_desc,
1051
1043
.data = k1_pin_data,
1052
1044
.npins = ARRAY_SIZE(k1_pin_desc),
1045
+
.pin_to_offset = spacemit_k1_pin_to_offset,
1046
+
};
1047
+
1048
+
static const struct pinctrl_pin_desc k3_pin_desc[] = {
1049
+
PINCTRL_PIN(0, "GPIO_00"),
1050
+
PINCTRL_PIN(1, "GPIO_01"),
1051
+
PINCTRL_PIN(2, "GPIO_02"),
1052
+
PINCTRL_PIN(3, "GPIO_03"),
1053
+
PINCTRL_PIN(4, "GPIO_04"),
1054
+
PINCTRL_PIN(5, "GPIO_05"),
1055
+
PINCTRL_PIN(6, "GPIO_06"),
1056
+
PINCTRL_PIN(7, "GPIO_07"),
1057
+
PINCTRL_PIN(8, "GPIO_08"),
1058
+
PINCTRL_PIN(9, "GPIO_09"),
1059
+
PINCTRL_PIN(10, "GPIO_10"),
1060
+
PINCTRL_PIN(11, "GPIO_11"),
1061
+
PINCTRL_PIN(12, "GPIO_12"),
1062
+
PINCTRL_PIN(13, "GPIO_13"),
1063
+
PINCTRL_PIN(14, "GPIO_14"),
1064
+
PINCTRL_PIN(15, "GPIO_15"),
1065
+
PINCTRL_PIN(16, "GPIO_16"),
1066
+
PINCTRL_PIN(17, "GPIO_17"),
1067
+
PINCTRL_PIN(18, "GPIO_18"),
1068
+
PINCTRL_PIN(19, "GPIO_19"),
1069
+
PINCTRL_PIN(20, "GPIO_20"),
1070
+
PINCTRL_PIN(21, "GPIO_21"),
1071
+
PINCTRL_PIN(22, "GPIO_22"),
1072
+
PINCTRL_PIN(23, "GPIO_23"),
1073
+
PINCTRL_PIN(24, "GPIO_24"),
1074
+
PINCTRL_PIN(25, "GPIO_25"),
1075
+
PINCTRL_PIN(26, "GPIO_26"),
1076
+
PINCTRL_PIN(27, "GPIO_27"),
1077
+
PINCTRL_PIN(28, "GPIO_28"),
1078
+
PINCTRL_PIN(29, "GPIO_29"),
1079
+
PINCTRL_PIN(30, "GPIO_30"),
1080
+
PINCTRL_PIN(31, "GPIO_31"),
1081
+
PINCTRL_PIN(32, "GPIO_32"),
1082
+
PINCTRL_PIN(33, "GPIO_33"),
1083
+
PINCTRL_PIN(34, "GPIO_34"),
1084
+
PINCTRL_PIN(35, "GPIO_35"),
1085
+
PINCTRL_PIN(36, "GPIO_36"),
1086
+
PINCTRL_PIN(37, "GPIO_37"),
1087
+
PINCTRL_PIN(38, "GPIO_38"),
1088
+
PINCTRL_PIN(39, "GPIO_39"),
1089
+
PINCTRL_PIN(40, "GPIO_40"),
1090
+
PINCTRL_PIN(41, "GPIO_41"),
1091
+
PINCTRL_PIN(42, "GPIO_42"),
1092
+
PINCTRL_PIN(43, "GPIO_43"),
1093
+
PINCTRL_PIN(44, "GPIO_44"),
1094
+
PINCTRL_PIN(45, "GPIO_45"),
1095
+
PINCTRL_PIN(46, "GPIO_46"),
1096
+
PINCTRL_PIN(47, "GPIO_47"),
1097
+
PINCTRL_PIN(48, "GPIO_48"),
1098
+
PINCTRL_PIN(49, "GPIO_49"),
1099
+
PINCTRL_PIN(50, "GPIO_50"),
1100
+
PINCTRL_PIN(51, "GPIO_51"),
1101
+
PINCTRL_PIN(52, "GPIO_52"),
1102
+
PINCTRL_PIN(53, "GPIO_53"),
1103
+
PINCTRL_PIN(54, "GPIO_54"),
1104
+
PINCTRL_PIN(55, "GPIO_55"),
1105
+
PINCTRL_PIN(56, "GPIO_56"),
1106
+
PINCTRL_PIN(57, "GPIO_57"),
1107
+
PINCTRL_PIN(58, "GPIO_58"),
1108
+
PINCTRL_PIN(59, "GPIO_59"),
1109
+
PINCTRL_PIN(60, "GPIO_60"),
1110
+
PINCTRL_PIN(61, "GPIO_61"),
1111
+
PINCTRL_PIN(62, "GPIO_62"),
1112
+
PINCTRL_PIN(63, "GPIO_63"),
1113
+
PINCTRL_PIN(64, "GPIO_64"),
1114
+
PINCTRL_PIN(65, "GPIO_65"),
1115
+
PINCTRL_PIN(66, "GPIO_66"),
1116
+
PINCTRL_PIN(67, "GPIO_67"),
1117
+
PINCTRL_PIN(68, "GPIO_68"),
1118
+
PINCTRL_PIN(69, "GPIO_69"),
1119
+
PINCTRL_PIN(70, "GPIO_70"),
1120
+
PINCTRL_PIN(71, "GPIO_71"),
1121
+
PINCTRL_PIN(72, "GPIO_72"),
1122
+
PINCTRL_PIN(73, "GPIO_73"),
1123
+
PINCTRL_PIN(74, "GPIO_74"),
1124
+
PINCTRL_PIN(75, "GPIO_75"),
1125
+
PINCTRL_PIN(76, "GPIO_76"),
1126
+
PINCTRL_PIN(77, "GPIO_77"),
1127
+
PINCTRL_PIN(78, "GPIO_78"),
1128
+
PINCTRL_PIN(79, "GPIO_79"),
1129
+
PINCTRL_PIN(80, "GPIO_80"),
1130
+
PINCTRL_PIN(81, "GPIO_81"),
1131
+
PINCTRL_PIN(82, "GPIO_82"),
1132
+
PINCTRL_PIN(83, "GPIO_83"),
1133
+
PINCTRL_PIN(84, "GPIO_84"),
1134
+
PINCTRL_PIN(85, "GPIO_85"),
1135
+
PINCTRL_PIN(86, "GPIO_86"),
1136
+
PINCTRL_PIN(87, "GPIO_87"),
1137
+
PINCTRL_PIN(88, "GPIO_88"),
1138
+
PINCTRL_PIN(89, "GPIO_89"),
1139
+
PINCTRL_PIN(90, "GPIO_90"),
1140
+
PINCTRL_PIN(91, "GPIO_91"),
1141
+
PINCTRL_PIN(92, "GPIO_92"),
1142
+
PINCTRL_PIN(93, "GPIO_93"),
1143
+
PINCTRL_PIN(94, "GPIO_94"),
1144
+
PINCTRL_PIN(95, "GPIO_95"),
1145
+
PINCTRL_PIN(96, "GPIO_96"),
1146
+
PINCTRL_PIN(97, "GPIO_97"),
1147
+
PINCTRL_PIN(98, "GPIO_98"),
1148
+
PINCTRL_PIN(99, "GPIO_99"),
1149
+
PINCTRL_PIN(100, "GPIO_100"),
1150
+
PINCTRL_PIN(101, "GPIO_101"),
1151
+
PINCTRL_PIN(102, "GPIO_102"),
1152
+
PINCTRL_PIN(103, "GPIO_103"),
1153
+
PINCTRL_PIN(104, "GPIO_104"),
1154
+
PINCTRL_PIN(105, "GPIO_105"),
1155
+
PINCTRL_PIN(106, "GPIO_106"),
1156
+
PINCTRL_PIN(107, "GPIO_107"),
1157
+
PINCTRL_PIN(108, "GPIO_108"),
1158
+
PINCTRL_PIN(109, "GPIO_109"),
1159
+
PINCTRL_PIN(110, "GPIO_110"),
1160
+
PINCTRL_PIN(111, "GPIO_111"),
1161
+
PINCTRL_PIN(112, "GPIO_112"),
1162
+
PINCTRL_PIN(113, "GPIO_113"),
1163
+
PINCTRL_PIN(114, "GPIO_114"),
1164
+
PINCTRL_PIN(115, "GPIO_115"),
1165
+
PINCTRL_PIN(116, "GPIO_116"),
1166
+
PINCTRL_PIN(117, "GPIO_117"),
1167
+
PINCTRL_PIN(118, "GPIO_118"),
1168
+
PINCTRL_PIN(119, "GPIO_119"),
1169
+
PINCTRL_PIN(120, "GPIO_120"),
1170
+
PINCTRL_PIN(121, "GPIO_121"),
1171
+
PINCTRL_PIN(122, "GPIO_122"),
1172
+
PINCTRL_PIN(123, "GPIO_123"),
1173
+
PINCTRL_PIN(124, "GPIO_124"),
1174
+
PINCTRL_PIN(125, "GPIO_125"),
1175
+
PINCTRL_PIN(126, "GPIO_126"),
1176
+
PINCTRL_PIN(127, "GPIO_127"),
1177
+
PINCTRL_PIN(128, "PWR_SCL"),
1178
+
PINCTRL_PIN(129, "PWR_SDA"),
1179
+
PINCTRL_PIN(130, "VCXO_EN"),
1180
+
PINCTRL_PIN(131, "PMIC_INT_N"),
1181
+
PINCTRL_PIN(132, "MMC1_DAT3"),
1182
+
PINCTRL_PIN(133, "MMC1_DAT2"),
1183
+
PINCTRL_PIN(134, "MMC1_DAT1"),
1184
+
PINCTRL_PIN(135, "MMC1_DAT0"),
1185
+
PINCTRL_PIN(136, "MMC1_CMD"),
1186
+
PINCTRL_PIN(137, "MMC1_CLK"),
1187
+
PINCTRL_PIN(138, "QSPI_DAT0"),
1188
+
PINCTRL_PIN(139, "QSPI_DAT1"),
1189
+
PINCTRL_PIN(140, "QSPI_DAT2"),
1190
+
PINCTRL_PIN(141, "QSPI_DAT3"),
1191
+
PINCTRL_PIN(142, "QSPI_CS0"),
1192
+
PINCTRL_PIN(143, "QSPI_CS1"),
1193
+
PINCTRL_PIN(144, "QSPI_CLK"),
1194
+
PINCTRL_PIN(145, "PRI_TDI"),
1195
+
PINCTRL_PIN(146, "PRI_TMS"),
1196
+
PINCTRL_PIN(147, "PRI_TCK"),
1197
+
PINCTRL_PIN(148, "PRI_TDO"),
1198
+
PINCTRL_PIN(149, "PWR_SSP_SCLK"),
1199
+
PINCTRL_PIN(150, "PWR_SSP_FRM"),
1200
+
PINCTRL_PIN(151, "PWR_SSP_TXD"),
1201
+
PINCTRL_PIN(152, "PWR_SSP_RXD"),
1202
+
};
1203
+
1204
+
static const struct spacemit_pin k3_pin_data[ARRAY_SIZE(k3_pin_desc)] = {
1205
+
/* GPIO1 bank */
1206
+
K1_FUNC_PIN(0, 0, IO_TYPE_EXTERNAL),
1207
+
K1_FUNC_PIN(1, 0, IO_TYPE_EXTERNAL),
1208
+
K1_FUNC_PIN(2, 0, IO_TYPE_EXTERNAL),
1209
+
K1_FUNC_PIN(3, 0, IO_TYPE_EXTERNAL),
1210
+
K1_FUNC_PIN(4, 0, IO_TYPE_EXTERNAL),
1211
+
K1_FUNC_PIN(5, 0, IO_TYPE_EXTERNAL),
1212
+
K1_FUNC_PIN(6, 0, IO_TYPE_EXTERNAL),
1213
+
K1_FUNC_PIN(7, 0, IO_TYPE_EXTERNAL),
1214
+
K1_FUNC_PIN(8, 0, IO_TYPE_EXTERNAL),
1215
+
K1_FUNC_PIN(9, 0, IO_TYPE_EXTERNAL),
1216
+
K1_FUNC_PIN(10, 0, IO_TYPE_EXTERNAL),
1217
+
K1_FUNC_PIN(11, 0, IO_TYPE_EXTERNAL),
1218
+
K1_FUNC_PIN(12, 0, IO_TYPE_EXTERNAL),
1219
+
K1_FUNC_PIN(13, 0, IO_TYPE_EXTERNAL),
1220
+
K1_FUNC_PIN(14, 0, IO_TYPE_EXTERNAL),
1221
+
K1_FUNC_PIN(15, 0, IO_TYPE_EXTERNAL),
1222
+
K1_FUNC_PIN(16, 0, IO_TYPE_EXTERNAL),
1223
+
K1_FUNC_PIN(17, 0, IO_TYPE_EXTERNAL),
1224
+
K1_FUNC_PIN(18, 0, IO_TYPE_EXTERNAL),
1225
+
K1_FUNC_PIN(19, 0, IO_TYPE_EXTERNAL),
1226
+
K1_FUNC_PIN(20, 0, IO_TYPE_EXTERNAL),
1227
+
1228
+
/* GPIO2 bank */
1229
+
K1_FUNC_PIN(21, 0, IO_TYPE_EXTERNAL),
1230
+
K1_FUNC_PIN(22, 0, IO_TYPE_EXTERNAL),
1231
+
K1_FUNC_PIN(23, 0, IO_TYPE_EXTERNAL),
1232
+
K1_FUNC_PIN(24, 0, IO_TYPE_EXTERNAL),
1233
+
K1_FUNC_PIN(25, 0, IO_TYPE_EXTERNAL),
1234
+
K1_FUNC_PIN(26, 0, IO_TYPE_EXTERNAL),
1235
+
K1_FUNC_PIN(27, 0, IO_TYPE_EXTERNAL),
1236
+
K1_FUNC_PIN(28, 0, IO_TYPE_EXTERNAL),
1237
+
K1_FUNC_PIN(29, 0, IO_TYPE_EXTERNAL),
1238
+
K1_FUNC_PIN(30, 0, IO_TYPE_EXTERNAL),
1239
+
K1_FUNC_PIN(31, 0, IO_TYPE_EXTERNAL),
1240
+
K1_FUNC_PIN(32, 0, IO_TYPE_EXTERNAL),
1241
+
K1_FUNC_PIN(33, 0, IO_TYPE_EXTERNAL),
1242
+
K1_FUNC_PIN(34, 0, IO_TYPE_EXTERNAL),
1243
+
K1_FUNC_PIN(35, 0, IO_TYPE_EXTERNAL),
1244
+
K1_FUNC_PIN(36, 0, IO_TYPE_EXTERNAL),
1245
+
K1_FUNC_PIN(37, 0, IO_TYPE_EXTERNAL),
1246
+
K1_FUNC_PIN(38, 0, IO_TYPE_EXTERNAL),
1247
+
K1_FUNC_PIN(39, 0, IO_TYPE_EXTERNAL),
1248
+
K1_FUNC_PIN(40, 0, IO_TYPE_EXTERNAL),
1249
+
K1_FUNC_PIN(41, 0, IO_TYPE_EXTERNAL),
1250
+
1251
+
/* GPIO3 bank */
1252
+
K1_FUNC_PIN(42, 0, IO_TYPE_1V8),
1253
+
K1_FUNC_PIN(43, 0, IO_TYPE_1V8),
1254
+
K1_FUNC_PIN(44, 0, IO_TYPE_1V8),
1255
+
K1_FUNC_PIN(45, 0, IO_TYPE_1V8),
1256
+
K1_FUNC_PIN(46, 0, IO_TYPE_1V8),
1257
+
K1_FUNC_PIN(47, 0, IO_TYPE_1V8),
1258
+
K1_FUNC_PIN(48, 0, IO_TYPE_1V8),
1259
+
K1_FUNC_PIN(49, 0, IO_TYPE_1V8),
1260
+
K1_FUNC_PIN(50, 0, IO_TYPE_1V8),
1261
+
K1_FUNC_PIN(51, 0, IO_TYPE_1V8),
1262
+
K1_FUNC_PIN(52, 0, IO_TYPE_1V8),
1263
+
K1_FUNC_PIN(53, 0, IO_TYPE_1V8),
1264
+
K1_FUNC_PIN(54, 0, IO_TYPE_1V8),
1265
+
K1_FUNC_PIN(55, 0, IO_TYPE_1V8),
1266
+
K1_FUNC_PIN(56, 0, IO_TYPE_1V8),
1267
+
K1_FUNC_PIN(57, 0, IO_TYPE_1V8),
1268
+
K1_FUNC_PIN(58, 0, IO_TYPE_1V8),
1269
+
K1_FUNC_PIN(59, 0, IO_TYPE_1V8),
1270
+
K1_FUNC_PIN(60, 0, IO_TYPE_1V8),
1271
+
K1_FUNC_PIN(61, 0, IO_TYPE_1V8),
1272
+
K1_FUNC_PIN(62, 0, IO_TYPE_1V8),
1273
+
K1_FUNC_PIN(63, 0, IO_TYPE_1V8),
1274
+
K1_FUNC_PIN(64, 0, IO_TYPE_1V8),
1275
+
K1_FUNC_PIN(65, 0, IO_TYPE_1V8),
1276
+
K1_FUNC_PIN(66, 0, IO_TYPE_1V8),
1277
+
K1_FUNC_PIN(67, 0, IO_TYPE_1V8),
1278
+
K1_FUNC_PIN(68, 0, IO_TYPE_1V8),
1279
+
K1_FUNC_PIN(69, 0, IO_TYPE_1V8),
1280
+
K1_FUNC_PIN(70, 0, IO_TYPE_1V8),
1281
+
K1_FUNC_PIN(71, 0, IO_TYPE_1V8),
1282
+
K1_FUNC_PIN(72, 0, IO_TYPE_1V8),
1283
+
K1_FUNC_PIN(73, 0, IO_TYPE_1V8),
1284
+
K1_FUNC_PIN(74, 0, IO_TYPE_1V8),
1285
+
K1_FUNC_PIN(75, 0, IO_TYPE_1V8),
1286
+
1287
+
/* GPIO4 bank */
1288
+
K1_FUNC_PIN(76, 0, IO_TYPE_EXTERNAL),
1289
+
K1_FUNC_PIN(77, 0, IO_TYPE_EXTERNAL),
1290
+
K1_FUNC_PIN(78, 0, IO_TYPE_EXTERNAL),
1291
+
K1_FUNC_PIN(79, 0, IO_TYPE_EXTERNAL),
1292
+
K1_FUNC_PIN(80, 0, IO_TYPE_EXTERNAL),
1293
+
K1_FUNC_PIN(81, 0, IO_TYPE_EXTERNAL),
1294
+
K1_FUNC_PIN(82, 0, IO_TYPE_EXTERNAL),
1295
+
K1_FUNC_PIN(83, 0, IO_TYPE_EXTERNAL),
1296
+
K1_FUNC_PIN(84, 0, IO_TYPE_EXTERNAL),
1297
+
K1_FUNC_PIN(85, 0, IO_TYPE_EXTERNAL),
1298
+
K1_FUNC_PIN(86, 0, IO_TYPE_EXTERNAL),
1299
+
K1_FUNC_PIN(87, 0, IO_TYPE_EXTERNAL),
1300
+
K1_FUNC_PIN(88, 0, IO_TYPE_EXTERNAL),
1301
+
K1_FUNC_PIN(89, 0, IO_TYPE_EXTERNAL),
1302
+
K1_FUNC_PIN(90, 0, IO_TYPE_EXTERNAL),
1303
+
K1_FUNC_PIN(91, 0, IO_TYPE_EXTERNAL),
1304
+
K1_FUNC_PIN(92, 0, IO_TYPE_EXTERNAL),
1305
+
K1_FUNC_PIN(93, 0, IO_TYPE_EXTERNAL),
1306
+
K1_FUNC_PIN(94, 0, IO_TYPE_EXTERNAL),
1307
+
K1_FUNC_PIN(95, 0, IO_TYPE_EXTERNAL),
1308
+
K1_FUNC_PIN(96, 0, IO_TYPE_EXTERNAL),
1309
+
K1_FUNC_PIN(97, 0, IO_TYPE_EXTERNAL),
1310
+
K1_FUNC_PIN(98, 0, IO_TYPE_EXTERNAL),
1311
+
1312
+
/* GPIO5 bank */
1313
+
K1_FUNC_PIN(99, 0, IO_TYPE_EXTERNAL),
1314
+
K1_FUNC_PIN(100, 0, IO_TYPE_EXTERNAL),
1315
+
K1_FUNC_PIN(101, 0, IO_TYPE_EXTERNAL),
1316
+
K1_FUNC_PIN(102, 0, IO_TYPE_EXTERNAL),
1317
+
K1_FUNC_PIN(103, 0, IO_TYPE_EXTERNAL),
1318
+
K1_FUNC_PIN(104, 0, IO_TYPE_EXTERNAL),
1319
+
K1_FUNC_PIN(105, 0, IO_TYPE_EXTERNAL),
1320
+
K1_FUNC_PIN(106, 0, IO_TYPE_EXTERNAL),
1321
+
K1_FUNC_PIN(107, 0, IO_TYPE_EXTERNAL),
1322
+
K1_FUNC_PIN(108, 0, IO_TYPE_EXTERNAL),
1323
+
K1_FUNC_PIN(109, 0, IO_TYPE_EXTERNAL),
1324
+
K1_FUNC_PIN(110, 0, IO_TYPE_EXTERNAL),
1325
+
K1_FUNC_PIN(111, 0, IO_TYPE_EXTERNAL),
1326
+
K1_FUNC_PIN(112, 0, IO_TYPE_EXTERNAL),
1327
+
K1_FUNC_PIN(113, 0, IO_TYPE_EXTERNAL),
1328
+
K1_FUNC_PIN(114, 0, IO_TYPE_EXTERNAL),
1329
+
K1_FUNC_PIN(115, 0, IO_TYPE_EXTERNAL),
1330
+
K1_FUNC_PIN(116, 0, IO_TYPE_EXTERNAL),
1331
+
K1_FUNC_PIN(117, 0, IO_TYPE_EXTERNAL),
1332
+
K1_FUNC_PIN(118, 0, IO_TYPE_EXTERNAL),
1333
+
K1_FUNC_PIN(119, 0, IO_TYPE_EXTERNAL),
1334
+
K1_FUNC_PIN(120, 0, IO_TYPE_EXTERNAL),
1335
+
K1_FUNC_PIN(121, 0, IO_TYPE_EXTERNAL),
1336
+
K1_FUNC_PIN(122, 0, IO_TYPE_EXTERNAL),
1337
+
K1_FUNC_PIN(123, 0, IO_TYPE_EXTERNAL),
1338
+
K1_FUNC_PIN(124, 0, IO_TYPE_EXTERNAL),
1339
+
K1_FUNC_PIN(125, 0, IO_TYPE_EXTERNAL),
1340
+
K1_FUNC_PIN(126, 0, IO_TYPE_EXTERNAL),
1341
+
K1_FUNC_PIN(127, 0, IO_TYPE_EXTERNAL),
1342
+
1343
+
/* PMIC */
1344
+
K1_FUNC_PIN(128, 0, IO_TYPE_1V8),
1345
+
K1_FUNC_PIN(129, 0, IO_TYPE_1V8),
1346
+
K1_FUNC_PIN(130, 0, IO_TYPE_1V8),
1347
+
K1_FUNC_PIN(131, 0, IO_TYPE_1V8),
1348
+
1349
+
/* SD/MMC1 */
1350
+
K1_FUNC_PIN(132, 1, IO_TYPE_EXTERNAL),
1351
+
K1_FUNC_PIN(133, 1, IO_TYPE_EXTERNAL),
1352
+
K1_FUNC_PIN(134, 1, IO_TYPE_EXTERNAL),
1353
+
K1_FUNC_PIN(135, 1, IO_TYPE_EXTERNAL),
1354
+
K1_FUNC_PIN(136, 1, IO_TYPE_EXTERNAL),
1355
+
K1_FUNC_PIN(137, 1, IO_TYPE_EXTERNAL),
1356
+
1357
+
/* QSPI */
1358
+
K1_FUNC_PIN(138, 1, IO_TYPE_EXTERNAL),
1359
+
K1_FUNC_PIN(139, 1, IO_TYPE_EXTERNAL),
1360
+
K1_FUNC_PIN(140, 1, IO_TYPE_EXTERNAL),
1361
+
K1_FUNC_PIN(141, 1, IO_TYPE_EXTERNAL),
1362
+
K1_FUNC_PIN(142, 1, IO_TYPE_EXTERNAL),
1363
+
K1_FUNC_PIN(143, 1, IO_TYPE_EXTERNAL),
1364
+
K1_FUNC_PIN(144, 1, IO_TYPE_EXTERNAL),
1365
+
1366
+
/* PMIC */
1367
+
K1_FUNC_PIN(145, 1, IO_TYPE_1V8),
1368
+
K1_FUNC_PIN(146, 1, IO_TYPE_1V8),
1369
+
K1_FUNC_PIN(147, 1, IO_TYPE_1V8),
1370
+
K1_FUNC_PIN(148, 1, IO_TYPE_1V8),
1371
+
K1_FUNC_PIN(149, 1, IO_TYPE_1V8),
1372
+
K1_FUNC_PIN(150, 1, IO_TYPE_1V8),
1373
+
K1_FUNC_PIN(151, 1, IO_TYPE_1V8),
1374
+
K1_FUNC_PIN(152, 1, IO_TYPE_1V8),
1375
+
};
1376
+
1377
+
static const struct spacemit_pinctrl_data k3_pinctrl_data = {
1378
+
.pins = k3_pin_desc,
1379
+
.data = k3_pin_data,
1380
+
.npins = ARRAY_SIZE(k3_pin_desc),
1381
+
.pin_to_offset = spacemit_k3_pin_to_offset,
1053
1382
};
1054
1383
1055
1384
static const struct of_device_id k1_pinctrl_ids[] = {
1056
1385
{ .compatible = "spacemit,k1-pinctrl", .data = &k1_pinctrl_data },
1386
+
{ .compatible = "spacemit,k3-pinctrl", .data = &k3_pinctrl_data },
1057
1387
{ /* sentinel */ }
1058
1388
};
1059
1389
MODULE_DEVICE_TABLE(of, k1_pinctrl_ids);
···
1407
1061
builtin_platform_driver(k1_pinctrl_driver);
1408
1062
1409
1063
MODULE_AUTHOR("Yixun Lan <dlan@gentoo.org>");
1410
-
MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1 SoC");
1064
+
MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1/K3 SoC");
1411
1065
MODULE_LICENSE("GPL");