tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"This is mostly amdgpu/radeon fixes, and imx related fixes.

There is also one one TTM fix, one nouveau fix, and one hdlcd fix.

The AMD ones are some fixes for power management after suspend/resume
one some GPUs, and some vblank fixes.

The IMX ones are for more stricter plane checks and some cleanups.

I'm off until Monday, so therre might be some fixes early next week if
anyone missed me"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (34 commits)
drm/nouveau/tegra: acquire and enable reference clock if needed
drm/amdgpu: total vram size also reduces pin size
drm/amd/powerplay: add uvd/vce dpm enabling flag default.
drm/amd/powerplay: fix issue that resume back, dpm can't work on FIJI.
drm/amdgpu: save and restore the firwmware cache part when suspend resume
drm/amdgpu: save and restore UVD context with suspend and resume
drm/ttm: use phys_addr_t for ttm_bus_placement
drm: ARM HDLCD - fix an error code
drm: ARM HDLCD - get rid of devm_clk_put()
drm/radeon: Only call drm_vblank_on/off between drm_vblank_init/cleanup
drm/amdgpu: fence wait old rcu slot
drm/amdgpu: fix leaking fence in the pageflip code
drm/amdgpu: print vram type rather than just DDR
drm/amdgpu/gmc: use proper register for vram type on Fiji
drm/amdgpu/gmc: move vram type fetching into sw_init
drm/amdgpu: Set vblank_disable_allowed = true
drm/radeon: Set vblank_disable_allowed = true
drm/amd/powerplay: Need to change boot to performance state in resume.
drm/amd/powerplay: add new Fiji function for not setting same ps.
drm/amdgpu: check dpm state before pm system fs initialized.
...

Linus Torvalds 741f37b8 c4004b02

+404 -169
+1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
··· 1591 1591 struct amdgpu_bo *vcpu_bo; 1592 1592 void *cpu_addr; 1593 1593 uint64_t gpu_addr; 1594 + void *saved_bo; 1594 1595 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1595 1596 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1596 1597 struct delayed_work idle_work;
+19 -5
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
··· 816 816 struct drm_device *ddev = adev->ddev; 817 817 struct drm_crtc *crtc; 818 818 uint32_t line_time_us, vblank_lines; 819 + struct cgs_mode_info *mode_info; 819 820 820 821 if (info == NULL) 821 822 return -EINVAL; 823 + 824 + mode_info = info->mode_info; 822 825 823 826 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { 824 827 list_for_each_entry(crtc, ··· 831 828 info->active_display_mask |= (1 << amdgpu_crtc->crtc_id); 832 829 info->display_count++; 833 830 } 834 - if (info->mode_info != NULL && 831 + if (mode_info != NULL && 835 832 crtc->enabled && amdgpu_crtc->enabled && 836 833 amdgpu_crtc->hw_mode.clock) { 837 834 line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) / ··· 839 836 vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end - 840 837 amdgpu_crtc->hw_mode.crtc_vdisplay + 841 838 (amdgpu_crtc->v_border * 2); 842 - info->mode_info->vblank_time_us = vblank_lines * line_time_us; 843 - info->mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode); 844 - info->mode_info->ref_clock = adev->clock.spll.reference_freq; 845 - info->mode_info++; 839 + mode_info->vblank_time_us = vblank_lines * line_time_us; 840 + mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode); 841 + mode_info->ref_clock = adev->clock.spll.reference_freq; 842 + mode_info = NULL; 846 843 } 847 844 } 848 845 } 846 + 847 + return 0; 848 + } 849 + 850 + 851 + static int amdgpu_cgs_notify_dpm_enabled(void *cgs_device, bool enabled) 852 + { 853 + CGS_FUNC_ADEV; 854 + 855 + adev->pm.dpm_enabled = enabled; 849 856 850 857 return 0; 851 858 } ··· 1110 1097 amdgpu_cgs_set_powergating_state, 1111 1098 amdgpu_cgs_set_clockgating_state, 1112 1099 amdgpu_cgs_get_active_displays_info, 1100 + amdgpu_cgs_notify_dpm_enabled, 1113 1101 amdgpu_cgs_call_acpi_method, 1114 1102 amdgpu_cgs_query_system_info, 1115 1103 };
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
··· 57 57 if (!fence_add_callback(fence, &work->cb, amdgpu_flip_callback)) 58 58 return true; 59 59 60 - fence_put(*f); 60 + fence_put(fence); 61 61 return false; 62 62 } 63 63
+6 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
··· 121 121 { 122 122 struct amdgpu_device *adev = ring->adev; 123 123 struct amdgpu_fence *fence; 124 - struct fence **ptr; 124 + struct fence *old, **ptr; 125 125 uint32_t seq; 126 126 127 127 fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL); ··· 141 141 /* This function can't be called concurrently anyway, otherwise 142 142 * emitting the fence would mess up the hardware ring buffer. 143 143 */ 144 - BUG_ON(rcu_dereference_protected(*ptr, 1)); 144 + old = rcu_dereference_protected(*ptr, 1); 145 + if (old && !fence_is_signaled(old)) { 146 + DRM_INFO("rcu slot is busy\n"); 147 + fence_wait(old, false); 148 + } 145 149 146 150 rcu_assign_pointer(*ptr, fence_get(&fence->base)); 147 151
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
··· 219 219 if (r) { 220 220 return r; 221 221 } 222 + adev->ddev->vblank_disable_allowed = true; 223 + 222 224 /* enable msi */ 223 225 adev->irq.msi_enabled = false; 224 226
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
··· 382 382 struct drm_amdgpu_info_vram_gtt vram_gtt; 383 383 384 384 vram_gtt.vram_size = adev->mc.real_vram_size; 385 + vram_gtt.vram_size -= adev->vram_pin_size; 385 386 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size; 386 387 vram_gtt.vram_cpu_accessible_size -= adev->vram_pin_size; 387 388 vram_gtt.gtt_size = adev->mc.gtt_size;
+13 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
··· 476 476 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 477 477 } 478 478 479 + static const char *amdgpu_vram_names[] = { 480 + "UNKNOWN", 481 + "GDDR1", 482 + "DDR2", 483 + "GDDR3", 484 + "GDDR4", 485 + "GDDR5", 486 + "HBM", 487 + "DDR3" 488 + }; 489 + 479 490 int amdgpu_bo_init(struct amdgpu_device *adev) 480 491 { 481 492 /* Add an MTRR for the VRAM */ ··· 495 484 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 496 485 adev->mc.mc_vram_size >> 20, 497 486 (unsigned long long)adev->mc.aper_size >> 20); 498 - DRM_INFO("RAM width %dbits DDR\n", 499 - adev->mc.vram_width); 487 + DRM_INFO("RAM width %dbits %s\n", 488 + adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]); 500 489 return amdgpu_ttm_init(adev); 501 490 } 502 491
+3 -7
drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
··· 143 143 adev->powerplay.pp_handle); 144 144 145 145 #ifdef CONFIG_DRM_AMD_POWERPLAY 146 - if (adev->pp_enabled) { 146 + if (adev->pp_enabled && adev->pm.dpm_enabled) { 147 147 amdgpu_pm_sysfs_init(adev); 148 148 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL); 149 149 } ··· 161 161 adev->powerplay.pp_handle); 162 162 163 163 #ifdef CONFIG_DRM_AMD_POWERPLAY 164 - if (adev->pp_enabled) { 165 - if (amdgpu_dpm == 0) 166 - adev->pm.dpm_enabled = false; 167 - else 168 - adev->pm.dpm_enabled = true; 169 - } 164 + if (adev->pp_enabled) 165 + adev->pm.dpm_enabled = true; 170 166 #endif 171 167 172 168 return ret;
+30 -28
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
··· 241 241 242 242 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 243 243 { 244 - struct amdgpu_ring *ring = &adev->uvd.ring; 245 - int i, r; 244 + unsigned size; 245 + void *ptr; 246 + int i; 246 247 247 248 if (adev->uvd.vcpu_bo == NULL) 248 249 return 0; 249 250 250 - for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 251 - uint32_t handle = atomic_read(&adev->uvd.handles[i]); 252 - if (handle != 0) { 253 - struct fence *fence; 251 + for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) 252 + if (atomic_read(&adev->uvd.handles[i])) 253 + break; 254 254 255 - amdgpu_uvd_note_usage(adev); 255 + if (i == AMDGPU_MAX_UVD_HANDLES) 256 + return 0; 256 257 257 - r = amdgpu_uvd_get_destroy_msg(ring, handle, false, &fence); 258 - if (r) { 259 - DRM_ERROR("Error destroying UVD (%d)!\n", r); 260 - continue; 261 - } 258 + size = amdgpu_bo_size(adev->uvd.vcpu_bo); 259 + ptr = adev->uvd.cpu_addr; 262 260 263 - fence_wait(fence, false); 264 - fence_put(fence); 261 + adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL); 262 + if (!adev->uvd.saved_bo) 263 + return -ENOMEM; 265 264 266 - adev->uvd.filp[i] = NULL; 267 - atomic_set(&adev->uvd.handles[i], 0); 268 - } 269 - } 265 + memcpy(adev->uvd.saved_bo, ptr, size); 270 266 271 267 return 0; 272 268 } ··· 271 275 { 272 276 unsigned size; 273 277 void *ptr; 274 - const struct common_firmware_header *hdr; 275 - unsigned offset; 276 278 277 279 if (adev->uvd.vcpu_bo == NULL) 278 280 return -EINVAL; 279 281 280 - hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 281 - offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 282 - memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset, 283 - (adev->uvd.fw->size) - offset); 284 - 285 282 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 286 - size -= le32_to_cpu(hdr->ucode_size_bytes); 287 283 ptr = adev->uvd.cpu_addr; 288 - ptr += le32_to_cpu(hdr->ucode_size_bytes); 289 284 290 - memset(ptr, 0, size); 285 + if (adev->uvd.saved_bo != NULL) { 286 + memcpy(ptr, adev->uvd.saved_bo, size); 287 + kfree(adev->uvd.saved_bo); 288 + adev->uvd.saved_bo = NULL; 289 + } else { 290 + const struct common_firmware_header *hdr; 291 + unsigned offset; 292 + 293 + hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 294 + offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 295 + memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset, 296 + (adev->uvd.fw->size) - offset); 297 + size -= le32_to_cpu(hdr->ucode_size_bytes); 298 + ptr += le32_to_cpu(hdr->ucode_size_bytes); 299 + memset(ptr, 0, size); 300 + } 291 301 292 302 return 0; 293 303 }
+8 -8
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
··· 903 903 gmc_v7_0_set_gart_funcs(adev); 904 904 gmc_v7_0_set_irq_funcs(adev); 905 905 906 - if (adev->flags & AMD_IS_APU) { 907 - adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 908 - } else { 909 - u32 tmp = RREG32(mmMC_SEQ_MISC0); 910 - tmp &= MC_SEQ_MISC0__MT__MASK; 911 - adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp); 912 - } 913 - 914 906 return 0; 915 907 } 916 908 ··· 918 926 int r; 919 927 int dma_bits; 920 928 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 929 + 930 + if (adev->flags & AMD_IS_APU) { 931 + adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 932 + } else { 933 + u32 tmp = RREG32(mmMC_SEQ_MISC0); 934 + tmp &= MC_SEQ_MISC0__MT__MASK; 935 + adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp); 936 + } 921 937 922 938 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault); 923 939 if (r)
+15 -8
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
··· 863 863 gmc_v8_0_set_gart_funcs(adev); 864 864 gmc_v8_0_set_irq_funcs(adev); 865 865 866 - if (adev->flags & AMD_IS_APU) { 867 - adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 868 - } else { 869 - u32 tmp = RREG32(mmMC_SEQ_MISC0); 870 - tmp &= MC_SEQ_MISC0__MT__MASK; 871 - adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp); 872 - } 873 - 874 866 return 0; 875 867 } 876 868 ··· 873 881 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 874 882 } 875 883 884 + #define mmMC_SEQ_MISC0_FIJI 0xA71 885 + 876 886 static int gmc_v8_0_sw_init(void *handle) 877 887 { 878 888 int r; 879 889 int dma_bits; 880 890 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 891 + 892 + if (adev->flags & AMD_IS_APU) { 893 + adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 894 + } else { 895 + u32 tmp; 896 + 897 + if (adev->asic_type == CHIP_FIJI) 898 + tmp = RREG32(mmMC_SEQ_MISC0_FIJI); 899 + else 900 + tmp = RREG32(mmMC_SEQ_MISC0); 901 + tmp &= MC_SEQ_MISC0__MT__MASK; 902 + adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp); 903 + } 881 904 882 905 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault); 883 906 if (r)
+2 -2
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
··· 224 224 int r; 225 225 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 226 226 227 - r = amdgpu_uvd_suspend(adev); 227 + r = uvd_v4_2_hw_fini(adev); 228 228 if (r) 229 229 return r; 230 230 231 - r = uvd_v4_2_hw_fini(adev); 231 + r = amdgpu_uvd_suspend(adev); 232 232 if (r) 233 233 return r; 234 234
+2 -2
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
··· 220 220 int r; 221 221 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 222 222 223 - r = amdgpu_uvd_suspend(adev); 223 + r = uvd_v5_0_hw_fini(adev); 224 224 if (r) 225 225 return r; 226 226 227 - r = uvd_v5_0_hw_fini(adev); 227 + r = amdgpu_uvd_suspend(adev); 228 228 if (r) 229 229 return r; 230 230
+4 -3
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
··· 214 214 int r; 215 215 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 216 216 217 + r = uvd_v6_0_hw_fini(adev); 218 + if (r) 219 + return r; 220 + 217 221 /* Skip this for APU for now */ 218 222 if (!(adev->flags & AMD_IS_APU)) { 219 223 r = amdgpu_uvd_suspend(adev); 220 224 if (r) 221 225 return r; 222 226 } 223 - r = uvd_v6_0_hw_fini(adev); 224 - if (r) 225 - return r; 226 227 227 228 return r; 228 229 }
+8
drivers/gpu/drm/amd/include/cgs_common.h
··· 589 589 void *cgs_device, 590 590 struct cgs_display_info *info); 591 591 592 + typedef int (*cgs_notify_dpm_enabled)(void *cgs_device, bool enabled); 593 + 592 594 typedef int (*cgs_call_acpi_method)(void *cgs_device, 593 595 uint32_t acpi_method, 594 596 uint32_t acpi_function, ··· 646 644 cgs_set_clockgating_state set_clockgating_state; 647 645 /* display manager */ 648 646 cgs_get_active_displays_info get_active_displays_info; 647 + /* notify dpm enabled */ 648 + cgs_notify_dpm_enabled notify_dpm_enabled; 649 649 /* ACPI */ 650 650 cgs_call_acpi_method call_acpi_method; 651 651 /* get system info */ ··· 738 734 CGS_CALL(set_powergating_state, dev, block_type, state) 739 735 #define cgs_set_clockgating_state(dev, block_type, state) \ 740 736 CGS_CALL(set_clockgating_state, dev, block_type, state) 737 + #define cgs_notify_dpm_enabled(dev, enabled) \ 738 + CGS_CALL(notify_dpm_enabled, dev, enabled) 739 + 741 740 #define cgs_get_active_displays_info(dev, info) \ 742 741 CGS_CALL(get_active_displays_info, dev, info) 742 + 743 743 #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) \ 744 744 CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) 745 745 #define cgs_query_system_info(dev, sys_info) \
+2 -2
drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
··· 137 137 reset_display_configCounter_tasks, 138 138 update_dal_configuration_tasks, 139 139 vari_bright_resume_tasks, 140 - block_adjust_power_state_tasks, 141 140 setup_asic_tasks, 142 141 enable_stutter_mode_tasks, /*must do this in boot state and before SMC is started */ 143 142 enable_dynamic_state_management_tasks, 144 143 enable_clock_power_gatings_tasks, 145 144 enable_disable_bapm_tasks, 146 145 initialize_thermal_controller_tasks, 147 - reset_boot_state_tasks, 146 + get_2d_performance_state_tasks, 147 + set_performance_state_tasks, 148 148 adjust_power_state_tasks, 149 149 enable_disable_fps_tasks, 150 150 notify_hw_power_source_tasks,
+69
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
··· 2389 2389 2390 2390 for(count = 0; count < table->VceLevelCount; count++) { 2391 2391 table->VceLevel[count].Frequency = mm_table->entries[count].eclk; 2392 + table->VceLevel[count].MinVoltage = 0; 2392 2393 table->VceLevel[count].MinVoltage |= 2393 2394 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; 2394 2395 table->VceLevel[count].MinVoltage |= ··· 2466 2465 2467 2466 for (count = 0; count < table->SamuLevelCount; count++) { 2468 2467 /* not sure whether we need evclk or not */ 2468 + table->SamuLevel[count].MinVoltage = 0; 2469 2469 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock; 2470 2470 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc * 2471 2471 VOLTAGE_SCALE) << VDDC_SHIFT; ··· 2564 2562 table->UvdBootLevel = 0; 2565 2563 2566 2564 for (count = 0; count < table->UvdLevelCount; count++) { 2565 + table->UvdLevel[count].MinVoltage = 0; 2567 2566 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; 2568 2567 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk; 2569 2568 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc * ··· 2903 2900 if(FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control) 2904 2901 fiji_populate_smc_voltage_tables(hwmgr, table); 2905 2902 2903 + table->SystemFlags = 0; 2904 + 2906 2905 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2907 2906 PHM_PlatformCaps_AutomaticDCTransition)) 2908 2907 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; ··· 3002 2997 table->MemoryThermThrottleEnable = 1; 3003 2998 table->PCIeBootLinkLevel = 0; /* 0:Gen1 1:Gen2 2:Gen3*/ 3004 2999 table->PCIeGenInterval = 1; 3000 + table->VRConfig = 0; 3005 3001 3006 3002 result = fiji_populate_vr_config(hwmgr, table); 3007 3003 PP_ASSERT_WITH_CODE(0 == result, ··· 5201 5195 return size; 5202 5196 } 5203 5197 5198 + static inline bool fiji_are_power_levels_equal(const struct fiji_performance_level *pl1, 5199 + const struct fiji_performance_level *pl2) 5200 + { 5201 + return ((pl1->memory_clock == pl2->memory_clock) && 5202 + (pl1->engine_clock == pl2->engine_clock) && 5203 + (pl1->pcie_gen == pl2->pcie_gen) && 5204 + (pl1->pcie_lane == pl2->pcie_lane)); 5205 + } 5206 + 5207 + int fiji_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal) 5208 + { 5209 + const struct fiji_power_state *psa = cast_const_phw_fiji_power_state(pstate1); 5210 + const struct fiji_power_state *psb = cast_const_phw_fiji_power_state(pstate2); 5211 + int i; 5212 + 5213 + if (equal == NULL || psa == NULL || psb == NULL) 5214 + return -EINVAL; 5215 + 5216 + /* If the two states don't even have the same number of performance levels they cannot be the same state. */ 5217 + if (psa->performance_level_count != psb->performance_level_count) { 5218 + *equal = false; 5219 + return 0; 5220 + } 5221 + 5222 + for (i = 0; i < psa->performance_level_count; i++) { 5223 + if (!fiji_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) { 5224 + /* If we have found even one performance level pair that is different the states are different. */ 5225 + *equal = false; 5226 + return 0; 5227 + } 5228 + } 5229 + 5230 + /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ 5231 + *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk)); 5232 + *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk)); 5233 + *equal &= (psa->sclk_threshold == psb->sclk_threshold); 5234 + *equal &= (psa->acp_clk == psb->acp_clk); 5235 + 5236 + return 0; 5237 + } 5238 + 5239 + bool fiji_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) 5240 + { 5241 + struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); 5242 + bool is_update_required = false; 5243 + struct cgs_display_info info = {0,0,NULL}; 5244 + 5245 + cgs_get_active_displays_info(hwmgr->device, &info); 5246 + 5247 + if (data->display_timing.num_existing_displays != info.display_count) 5248 + is_update_required = true; 5249 + /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL 5250 + if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { 5251 + cgs_get_min_clock_settings(hwmgr->device, &min_clocks); 5252 + if(min_clocks.engineClockInSR != data->display_timing.minClockInSR) 5253 + is_update_required = true; 5254 + */ 5255 + return is_update_required; 5256 + } 5257 + 5258 + 5204 5259 static const struct pp_hwmgr_func fiji_hwmgr_funcs = { 5205 5260 .backend_init = &fiji_hwmgr_backend_init, 5206 5261 .backend_fini = &tonga_hwmgr_backend_fini, ··· 5297 5230 .register_internal_thermal_interrupt = fiji_register_internal_thermal_interrupt, 5298 5231 .set_fan_control_mode = fiji_set_fan_control_mode, 5299 5232 .get_fan_control_mode = fiji_get_fan_control_mode, 5233 + .check_states_equal = fiji_check_states_equal, 5234 + .check_smc_update_required_for_display_configuration = fiji_check_smc_update_required_for_display_configuration, 5300 5235 .get_pp_table = fiji_get_pp_table, 5301 5236 .set_pp_table = fiji_set_pp_table, 5302 5237 .force_clock_level = fiji_force_clock_level,
+13 -3
drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
··· 58 58 59 59 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress); 60 60 61 + phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM); 62 + phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM); 63 + 61 64 if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) && 62 65 acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION)) 63 66 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest); ··· 133 130 134 131 int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr) 135 132 { 133 + int ret = 1; 134 + bool enabled; 136 135 PHM_FUNC_CHECK(hwmgr); 137 136 138 137 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 139 138 PHM_PlatformCaps_TablelessHardwareInterface)) { 140 139 if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable) 141 - return hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr); 140 + ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr); 142 141 } else { 143 - return phm_dispatch_table(hwmgr, 142 + ret = phm_dispatch_table(hwmgr, 144 143 &(hwmgr->enable_dynamic_state_management), 145 144 NULL, NULL); 146 145 } 147 - return 0; 146 + 147 + enabled = ret == 0 ? true : false; 148 + 149 + cgs_notify_dpm_enabled(hwmgr->device, enabled); 150 + 151 + return ret; 148 152 } 149 153 150 154 int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
+3 -11
drivers/gpu/drm/arm/hdlcd_drv.c
··· 57 57 DRM_ERROR("failed to map control registers area\n"); 58 58 ret = PTR_ERR(hdlcd->mmio); 59 59 hdlcd->mmio = NULL; 60 - goto fail; 60 + return ret; 61 61 } 62 62 63 63 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION); 64 64 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) { 65 65 DRM_ERROR("unknown product id: 0x%x\n", version); 66 - ret = -EINVAL; 67 - goto fail; 66 + return -EINVAL; 68 67 } 69 68 DRM_INFO("found ARM HDLCD version r%dp%d\n", 70 69 (version & HDLCD_VERSION_MAJOR_MASK) >> 8, ··· 72 73 /* Get the optional framebuffer memory resource */ 73 74 ret = of_reserved_mem_device_init(drm->dev); 74 75 if (ret && ret != -ENODEV) 75 - goto fail; 76 + return ret; 76 77 77 78 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32)); 78 79 if (ret) ··· 100 101 drm_crtc_cleanup(&hdlcd->crtc); 101 102 setup_fail: 102 103 of_reserved_mem_device_release(drm->dev); 103 - fail: 104 - devm_clk_put(drm->dev, hdlcd->clk); 105 104 106 105 return ret; 107 106 } ··· 409 412 pm_runtime_put_sync(drm->dev); 410 413 pm_runtime_disable(drm->dev); 411 414 of_reserved_mem_device_release(drm->dev); 412 - devm_clk_put(dev, hdlcd->clk); 413 415 err_free: 414 416 drm_dev_unref(drm); 415 417 ··· 432 436 pm_runtime_put_sync(drm->dev); 433 437 pm_runtime_disable(drm->dev); 434 438 of_reserved_mem_device_release(drm->dev); 435 - if (!IS_ERR(hdlcd->clk)) { 436 - devm_clk_put(drm->dev, hdlcd->clk); 437 - hdlcd->clk = NULL; 438 - } 439 439 drm_mode_config_cleanup(drm); 440 440 drm_dev_unregister(drm); 441 441 drm_dev_unref(drm);
+10 -3
drivers/gpu/drm/imx/dw_hdmi-imx.c
··· 225 225 if (!iores) 226 226 return -ENXIO; 227 227 228 - platform_set_drvdata(pdev, hdmi); 229 - 230 228 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); 231 229 /* 232 230 * If we failed to find the CRTC(s) which this encoder is ··· 243 245 drm_encoder_init(drm, encoder, &dw_hdmi_imx_encoder_funcs, 244 246 DRM_MODE_ENCODER_TMDS, NULL); 245 247 246 - return dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data); 248 + ret = dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data); 249 + 250 + /* 251 + * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(), 252 + * which would have called the encoder cleanup. Do it manually. 253 + */ 254 + if (ret) 255 + drm_encoder_cleanup(encoder); 256 + 257 + return ret; 247 258 } 248 259 249 260 static void dw_hdmi_imx_unbind(struct device *dev, struct device *master,
-10
drivers/gpu/drm/imx/imx-drm-core.c
··· 326 326 { 327 327 struct imx_drm_device *imxdrm = drm->dev_private; 328 328 struct imx_drm_crtc *imx_drm_crtc; 329 - int ret; 330 329 331 330 /* 332 331 * The vblank arrays are dimensioned by MAX_CRTC - we can't ··· 350 351 351 352 *new_crtc = imx_drm_crtc; 352 353 353 - ret = drm_mode_crtc_set_gamma_size(imx_drm_crtc->crtc, 256); 354 - if (ret) 355 - goto err_register; 356 - 357 354 drm_crtc_helper_add(crtc, 358 355 imx_drm_crtc->imx_drm_helper_funcs.crtc_helper_funcs); 359 356 ··· 357 362 imx_drm_crtc->imx_drm_helper_funcs.crtc_funcs, NULL); 358 363 359 364 return 0; 360 - 361 - err_register: 362 - imxdrm->crtc[--imxdrm->pipes] = NULL; 363 - kfree(imx_drm_crtc); 364 - return ret; 365 365 } 366 366 EXPORT_SYMBOL_GPL(imx_drm_add_crtc); 367 367
+104 -17
drivers/gpu/drm/imx/ipuv3-plane.c
··· 72 72 int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb, 73 73 int x, int y) 74 74 { 75 - struct drm_gem_cma_object *cma_obj; 76 - unsigned long eba; 77 - int active; 75 + struct drm_gem_cma_object *cma_obj[3]; 76 + unsigned long eba, ubo, vbo; 77 + int active, i; 78 78 79 - cma_obj = drm_fb_cma_get_gem_obj(fb, 0); 80 - if (!cma_obj) { 81 - DRM_DEBUG_KMS("entry is null.\n"); 82 - return -EFAULT; 79 + for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) { 80 + cma_obj[i] = drm_fb_cma_get_gem_obj(fb, i); 81 + if (!cma_obj[i]) { 82 + DRM_DEBUG_KMS("plane %d entry is null.\n", i); 83 + return -EFAULT; 84 + } 83 85 } 84 86 85 - dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d", 86 - &cma_obj->paddr, x, y); 87 - 88 - eba = cma_obj->paddr + fb->offsets[0] + 87 + eba = cma_obj[0]->paddr + fb->offsets[0] + 89 88 fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x; 89 + 90 + if (eba & 0x7) { 91 + DRM_DEBUG_KMS("base address must be a multiple of 8.\n"); 92 + return -EINVAL; 93 + } 94 + 95 + if (fb->pitches[0] < 1 || fb->pitches[0] > 16384) { 96 + DRM_DEBUG_KMS("pitches out of range.\n"); 97 + return -EINVAL; 98 + } 99 + 100 + if (ipu_plane->enabled && fb->pitches[0] != ipu_plane->stride[0]) { 101 + DRM_DEBUG_KMS("pitches must not change while plane is enabled.\n"); 102 + return -EINVAL; 103 + } 104 + 105 + ipu_plane->stride[0] = fb->pitches[0]; 106 + 107 + switch (fb->pixel_format) { 108 + case DRM_FORMAT_YUV420: 109 + case DRM_FORMAT_YVU420: 110 + /* 111 + * Multiplanar formats have to meet the following restrictions: 112 + * - The (up to) three plane addresses are EBA, EBA+UBO, EBA+VBO 113 + * - EBA, UBO and VBO are a multiple of 8 114 + * - UBO and VBO are unsigned and not larger than 0xfffff8 115 + * - Only EBA may be changed while scanout is active 116 + * - The strides of U and V planes must be identical. 117 + */ 118 + ubo = cma_obj[1]->paddr + fb->offsets[1] + 119 + fb->pitches[1] * y / 2 + x / 2 - eba; 120 + vbo = cma_obj[2]->paddr + fb->offsets[2] + 121 + fb->pitches[2] * y / 2 + x / 2 - eba; 122 + 123 + if ((ubo & 0x7) || (vbo & 0x7)) { 124 + DRM_DEBUG_KMS("U/V buffer offsets must be a multiple of 8.\n"); 125 + return -EINVAL; 126 + } 127 + 128 + if ((ubo > 0xfffff8) || (vbo > 0xfffff8)) { 129 + DRM_DEBUG_KMS("U/V buffer offsets must be positive and not larger than 0xfffff8.\n"); 130 + return -EINVAL; 131 + } 132 + 133 + if (ipu_plane->enabled && ((ipu_plane->u_offset != ubo) || 134 + (ipu_plane->v_offset != vbo))) { 135 + DRM_DEBUG_KMS("U/V buffer offsets must not change while plane is enabled.\n"); 136 + return -EINVAL; 137 + } 138 + 139 + if (fb->pitches[1] != fb->pitches[2]) { 140 + DRM_DEBUG_KMS("U/V pitches must be identical.\n"); 141 + return -EINVAL; 142 + } 143 + 144 + if (fb->pitches[1] < 1 || fb->pitches[1] > 16384) { 145 + DRM_DEBUG_KMS("U/V pitches out of range.\n"); 146 + return -EINVAL; 147 + } 148 + 149 + if (ipu_plane->enabled && 150 + (ipu_plane->stride[1] != fb->pitches[1])) { 151 + DRM_DEBUG_KMS("U/V pitches must not change while plane is enabled.\n"); 152 + return -EINVAL; 153 + } 154 + 155 + ipu_plane->u_offset = ubo; 156 + ipu_plane->v_offset = vbo; 157 + ipu_plane->stride[1] = fb->pitches[1]; 158 + 159 + dev_dbg(ipu_plane->base.dev->dev, 160 + "phys = %pad %pad %pad, x = %d, y = %d", 161 + &cma_obj[0]->paddr, &cma_obj[1]->paddr, 162 + &cma_obj[2]->paddr, x, y); 163 + break; 164 + default: 165 + dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d", 166 + &cma_obj[0]->paddr, x, y); 167 + break; 168 + } 90 169 91 170 if (ipu_plane->enabled) { 92 171 active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch); ··· 280 201 } 281 202 } 282 203 283 - ret = ipu_dmfc_init_channel(ipu_plane->dmfc, crtc_w); 284 - if (ret) { 285 - dev_err(dev, "initializing dmfc channel failed with %d\n", ret); 286 - return ret; 287 - } 288 - 289 204 ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc, 290 205 calc_bandwidth(crtc_w, crtc_h, 291 206 calc_vref(mode)), 64); ··· 287 214 dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret); 288 215 return ret; 289 216 } 217 + 218 + ipu_dmfc_config_wait4eot(ipu_plane->dmfc, crtc_w); 290 219 291 220 ipu_cpmem_zero(ipu_plane->ipu_ch); 292 221 ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h); ··· 307 232 return ret; 308 233 if (interlaced) 309 234 ipu_cpmem_interlaced_scan(ipu_plane->ipu_ch, fb->pitches[0]); 235 + 236 + if (fb->pixel_format == DRM_FORMAT_YUV420) { 237 + ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch, 238 + ipu_plane->stride[1], 239 + ipu_plane->u_offset, 240 + ipu_plane->v_offset); 241 + } else if (fb->pixel_format == DRM_FORMAT_YVU420) { 242 + ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch, 243 + ipu_plane->stride[1], 244 + ipu_plane->v_offset, 245 + ipu_plane->u_offset); 246 + } 310 247 311 248 ipu_plane->w = src_w; 312 249 ipu_plane->h = src_h;
+4
drivers/gpu/drm/imx/ipuv3-plane.h
··· 29 29 int w; 30 30 int h; 31 31 32 + unsigned int u_offset; 33 + unsigned int v_offset; 34 + unsigned int stride[2]; 35 + 32 36 bool enabled; 33 37 }; 34 38
+5
drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
··· 11 11 12 12 struct reset_control *rst; 13 13 struct clk *clk; 14 + struct clk *clk_ref; 14 15 struct clk *clk_pwr; 15 16 16 17 struct regulator *vdd; ··· 37 36 * bypassed). A value of 0 means an IOMMU is never used. 38 37 */ 39 38 u8 iommu_bit; 39 + /* 40 + * Whether the chip requires a reference clock 41 + */ 42 + bool require_ref_clk; 40 43 }; 41 44 42 45 int nvkm_device_tegra_new(const struct nvkm_device_tegra_func *,
+6 -1
drivers/gpu/drm/nouveau/nouveau_platform.c
··· 55 55 .iommu_bit = 34, 56 56 }; 57 57 58 + static const struct nvkm_device_tegra_func gm20b_platform_data = { 59 + .iommu_bit = 34, 60 + .require_ref_clk = true, 61 + }; 62 + 58 63 static const struct of_device_id nouveau_platform_match[] = { 59 64 { 60 65 .compatible = "nvidia,gk20a", ··· 67 62 }, 68 63 { 69 64 .compatible = "nvidia,gm20b", 70 - .data = &gk20a_platform_data, 65 + .data = &gm20b_platform_data, 71 66 }, 72 67 { } 73 68 };
+17
drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
··· 35 35 ret = clk_prepare_enable(tdev->clk); 36 36 if (ret) 37 37 goto err_clk; 38 + if (tdev->clk_ref) { 39 + ret = clk_prepare_enable(tdev->clk_ref); 40 + if (ret) 41 + goto err_clk_ref; 42 + } 38 43 ret = clk_prepare_enable(tdev->clk_pwr); 39 44 if (ret) 40 45 goto err_clk_pwr; ··· 62 57 err_clamp: 63 58 clk_disable_unprepare(tdev->clk_pwr); 64 59 err_clk_pwr: 60 + if (tdev->clk_ref) 61 + clk_disable_unprepare(tdev->clk_ref); 62 + err_clk_ref: 65 63 clk_disable_unprepare(tdev->clk); 66 64 err_clk: 67 65 regulator_disable(tdev->vdd); ··· 79 71 udelay(10); 80 72 81 73 clk_disable_unprepare(tdev->clk_pwr); 74 + if (tdev->clk_ref) 75 + clk_disable_unprepare(tdev->clk_ref); 82 76 clk_disable_unprepare(tdev->clk); 83 77 udelay(10); 84 78 ··· 281 271 tdev->clk = devm_clk_get(&pdev->dev, "gpu"); 282 272 if (IS_ERR(tdev->clk)) { 283 273 ret = PTR_ERR(tdev->clk); 274 + goto free; 275 + } 276 + 277 + if (func->require_ref_clk) 278 + tdev->clk_ref = devm_clk_get(&pdev->dev, "ref"); 279 + if (IS_ERR(tdev->clk_ref)) { 280 + ret = PTR_ERR(tdev->clk_ref); 284 281 goto free; 285 282 } 286 283
+4 -2
drivers/gpu/drm/radeon/atombios_crtc.c
··· 275 275 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 276 276 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); 277 277 atombios_blank_crtc(crtc, ATOM_DISABLE); 278 - drm_vblank_on(dev, radeon_crtc->crtc_id); 278 + if (dev->num_crtcs > radeon_crtc->crtc_id) 279 + drm_vblank_on(dev, radeon_crtc->crtc_id); 279 280 radeon_crtc_load_lut(crtc); 280 281 break; 281 282 case DRM_MODE_DPMS_STANDBY: 282 283 case DRM_MODE_DPMS_SUSPEND: 283 284 case DRM_MODE_DPMS_OFF: 284 - drm_vblank_off(dev, radeon_crtc->crtc_id); 285 + if (dev->num_crtcs > radeon_crtc->crtc_id) 286 + drm_vblank_off(dev, radeon_crtc->crtc_id); 285 287 if (radeon_crtc->enabled) 286 288 atombios_blank_crtc(crtc, ATOM_ENABLE); 287 289 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
+2
drivers/gpu/drm/radeon/radeon_irq_kms.c
··· 291 291 if (r) { 292 292 return r; 293 293 } 294 + rdev->ddev->vblank_disable_allowed = true; 295 + 294 296 /* enable msi */ 295 297 rdev->msi_enabled = 0; 296 298
+4 -2
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
··· 331 331 RADEON_CRTC_DISP_REQ_EN_B)); 332 332 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); 333 333 } 334 - drm_vblank_on(dev, radeon_crtc->crtc_id); 334 + if (dev->num_crtcs > radeon_crtc->crtc_id) 335 + drm_vblank_on(dev, radeon_crtc->crtc_id); 335 336 radeon_crtc_load_lut(crtc); 336 337 break; 337 338 case DRM_MODE_DPMS_STANDBY: 338 339 case DRM_MODE_DPMS_SUSPEND: 339 340 case DRM_MODE_DPMS_OFF: 340 - drm_vblank_off(dev, radeon_crtc->crtc_id); 341 + if (dev->num_crtcs > radeon_crtc->crtc_id) 342 + drm_vblank_off(dev, radeon_crtc->crtc_id); 341 343 if (radeon_crtc->crtc_id) 342 344 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); 343 345 else {
+36 -43
drivers/gpu/ipu-v3/ipu-cpmem.c
··· 395 395 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved); 396 396 397 397 void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch, 398 - u32 pixel_format, int stride, 399 - int u_offset, int v_offset) 398 + unsigned int uv_stride, 399 + unsigned int u_offset, unsigned int v_offset) 400 400 { 401 - switch (pixel_format) { 402 - case V4L2_PIX_FMT_YUV420: 403 - case V4L2_PIX_FMT_YUV422P: 404 - ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1); 405 - ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8); 406 - ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8); 407 - break; 408 - case V4L2_PIX_FMT_YVU420: 409 - ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1); 410 - ipu_ch_param_write_field(ch, IPU_FIELD_UBO, v_offset / 8); 411 - ipu_ch_param_write_field(ch, IPU_FIELD_VBO, u_offset / 8); 412 - break; 413 - case V4L2_PIX_FMT_NV12: 414 - case V4L2_PIX_FMT_NV16: 415 - ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, stride - 1); 416 - ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8); 417 - ipu_ch_param_write_field(ch, IPU_FIELD_VBO, u_offset / 8); 418 - break; 419 - } 401 + ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, uv_stride - 1); 402 + ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8); 403 + ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8); 420 404 } 421 405 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full); 422 406 423 407 void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch, 424 408 u32 pixel_format, int stride, int height) 425 409 { 426 - int u_offset, v_offset; 410 + int fourcc, u_offset, v_offset; 427 411 int uv_stride = 0; 428 412 429 - switch (pixel_format) { 430 - case V4L2_PIX_FMT_YUV420: 431 - case V4L2_PIX_FMT_YVU420: 413 + fourcc = v4l2_pix_fmt_to_drm_fourcc(pixel_format); 414 + switch (fourcc) { 415 + case DRM_FORMAT_YUV420: 432 416 uv_stride = stride / 2; 433 417 u_offset = stride * height; 434 418 v_offset = u_offset + (uv_stride * height / 2); 435 - ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride, 436 - u_offset, v_offset); 437 419 break; 438 - case V4L2_PIX_FMT_YUV422P: 420 + case DRM_FORMAT_YVU420: 421 + uv_stride = stride / 2; 422 + v_offset = stride * height; 423 + u_offset = v_offset + (uv_stride * height / 2); 424 + break; 425 + case DRM_FORMAT_YUV422: 439 426 uv_stride = stride / 2; 440 427 u_offset = stride * height; 441 428 v_offset = u_offset + (uv_stride * height); 442 - ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride, 443 - u_offset, v_offset); 444 429 break; 445 - case V4L2_PIX_FMT_NV12: 446 - case V4L2_PIX_FMT_NV16: 430 + case DRM_FORMAT_NV12: 431 + case DRM_FORMAT_NV16: 432 + uv_stride = stride; 447 433 u_offset = stride * height; 448 - ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride, 449 - u_offset, 0); 434 + v_offset = 0; 450 435 break; 436 + default: 437 + return; 451 438 } 439 + ipu_cpmem_set_yuv_planar_full(ch, uv_stride, u_offset, v_offset); 452 440 } 453 441 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar); 454 442 ··· 672 684 673 685 switch (pix->pixelformat) { 674 686 case V4L2_PIX_FMT_YUV420: 687 + offset = Y_OFFSET(pix, image->rect.left, image->rect.top); 688 + u_offset = U_OFFSET(pix, image->rect.left, 689 + image->rect.top) - offset; 690 + v_offset = V_OFFSET(pix, image->rect.left, 691 + image->rect.top) - offset; 692 + 693 + ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2, 694 + u_offset, v_offset); 695 + break; 675 696 case V4L2_PIX_FMT_YVU420: 676 697 offset = Y_OFFSET(pix, image->rect.left, image->rect.top); 677 698 u_offset = U_OFFSET(pix, image->rect.left, ··· 688 691 v_offset = V_OFFSET(pix, image->rect.left, 689 692 image->rect.top) - offset; 690 693 691 - ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat, 692 - pix->bytesperline, 693 - u_offset, v_offset); 694 + ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2, 695 + v_offset, u_offset); 694 696 break; 695 697 case V4L2_PIX_FMT_YUV422P: 696 698 offset = Y_OFFSET(pix, image->rect.left, image->rect.top); ··· 698 702 v_offset = V2_OFFSET(pix, image->rect.left, 699 703 image->rect.top) - offset; 700 704 701 - ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat, 702 - pix->bytesperline, 705 + ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2, 703 706 u_offset, v_offset); 704 707 break; 705 708 case V4L2_PIX_FMT_NV12: ··· 707 712 image->rect.top) - offset; 708 713 v_offset = 0; 709 714 710 - ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat, 711 - pix->bytesperline, 715 + ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline, 712 716 u_offset, v_offset); 713 717 break; 714 718 case V4L2_PIX_FMT_NV16: ··· 716 722 image->rect.top) - offset; 717 723 v_offset = 0; 718 724 719 - ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat, 720 - pix->bytesperline, 725 + ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline, 721 726 u_offset, v_offset); 722 727 break; 723 728 case V4L2_PIX_FMT_UYVY:
+5 -3
drivers/gpu/ipu-v3/ipu-dmfc.c
··· 350 350 } 351 351 EXPORT_SYMBOL_GPL(ipu_dmfc_alloc_bandwidth); 352 352 353 - int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width) 353 + void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width) 354 354 { 355 355 struct ipu_dmfc_priv *priv = dmfc->priv; 356 356 u32 dmfc_gen1; 357 + 358 + mutex_lock(&priv->mutex); 357 359 358 360 dmfc_gen1 = readl(priv->base + DMFC_GENERAL1); 359 361 ··· 366 364 367 365 writel(dmfc_gen1, priv->base + DMFC_GENERAL1); 368 366 369 - return 0; 367 + mutex_unlock(&priv->mutex); 370 368 } 371 - EXPORT_SYMBOL_GPL(ipu_dmfc_init_channel); 369 + EXPORT_SYMBOL_GPL(ipu_dmfc_config_wait4eot); 372 370 373 371 struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipu_channel) 374 372 {
+1 -1
include/drm/ttm/ttm_bo_api.h
··· 92 92 */ 93 93 struct ttm_bus_placement { 94 94 void *addr; 95 - unsigned long base; 95 + phys_addr_t base; 96 96 unsigned long size; 97 97 unsigned long offset; 98 98 bool is_iomem;
+4 -3
include/video/imx-ipu-v3.h
··· 194 194 int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width); 195 195 void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format); 196 196 void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch, 197 - u32 pixel_format, int stride, 198 - int u_offset, int v_offset); 197 + unsigned int uv_stride, 198 + unsigned int u_offset, 199 + unsigned int v_offset); 199 200 void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch, 200 201 u32 pixel_format, int stride, int height); 201 202 int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc); ··· 237 236 int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc, 238 237 unsigned long bandwidth_mbs, int burstsize); 239 238 void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc); 240 - int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width); 239 + void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width); 241 240 struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel); 242 241 void ipu_dmfc_put(struct dmfc_channel *dmfc); 243 242