clk: qcom: clk-alpha-pll: Add support for controlling Taycan PLLs

Add clock ops for Taycan PLL, add the register offsets for supporting
the PLL.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-4-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Taniya Das and committed by

Bjorn Andersson 1 year ago 745d755b c035a9e2

+21

2 changed files

expand all

drivers

clk

qcom

clk-alpha-pll.c

clk-alpha-pll.h

+14

drivers/clk/qcom/clk-alpha-pll.c

··· 197 197 [PLL_OFF_TEST_CTL_U1] = 0x34, 198 198 [PLL_OFF_TEST_CTL_U2] = 0x38, 199 199 }, 200 + [CLK_ALPHA_PLL_TYPE_TAYCAN_ELU] = { 201 + [PLL_OFF_OPMODE] = 0x04, 202 + [PLL_OFF_STATE] = 0x08, 203 + [PLL_OFF_STATUS] = 0x0c, 204 + [PLL_OFF_L_VAL] = 0x10, 205 + [PLL_OFF_ALPHA_VAL] = 0x14, 206 + [PLL_OFF_USER_CTL] = 0x18, 207 + [PLL_OFF_USER_CTL_U] = 0x1c, 208 + [PLL_OFF_CONFIG_CTL] = 0x20, 209 + [PLL_OFF_CONFIG_CTL_U] = 0x24, 210 + [PLL_OFF_CONFIG_CTL_U1] = 0x28, 211 + [PLL_OFF_TEST_CTL] = 0x2c, 212 + [PLL_OFF_TEST_CTL_U] = 0x30, 213 + }, 200 214 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = { 201 215 [PLL_OFF_OPMODE] = 0x04, 202 216 [PLL_OFF_STATUS] = 0x0c,

drivers/clk/qcom/clk-alpha-pll.h

··· 27 27 CLK_ALPHA_PLL_TYPE_ZONDA_OLE, 28 28 CLK_ALPHA_PLL_TYPE_LUCID_EVO, 29 29 CLK_ALPHA_PLL_TYPE_LUCID_OLE, 30 + CLK_ALPHA_PLL_TYPE_TAYCAN_ELU, 30 31 CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, 31 32 CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, 32 33 CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, ··· 186 185 #define clk_alpha_pll_zonda_ole_ops clk_alpha_pll_zonda_ops 187 186 188 187 extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; 188 + #define clk_alpha_pll_taycan_elu_ops clk_alpha_pll_lucid_evo_ops 189 189 extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops; 190 190 #define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops 191 191 extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; 192 192 #define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops 193 + #define clk_alpha_pll_fixed_taycan_elu_ops clk_alpha_pll_fixed_lucid_evo_ops 193 194 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; 194 195 #define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops 196 + #define clk_alpha_pll_postdiv_taycan_elu_ops clk_alpha_pll_postdiv_lucid_evo_ops 195 197 196 198 extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; 197 199 #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops ··· 222 218 const struct alpha_pll_config *config); 223 219 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 224 220 const struct alpha_pll_config *config); 221 + #define clk_taycan_elu_pll_configure(pll, regmap, config) \ 222 + clk_lucid_evo_pll_configure(pll, regmap, config) 223 + 225 224 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 226 225 const struct alpha_pll_config *config); 227 226 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

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