Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/display: Add CASF strength and winsize
Add register definitions for sharpness strength and
filter window size used by CASF. Provide functions to
read and write these fields.
The sharpness strength value is determined by user input,
while the winsize is based on the resolution. The casf_enable
flag should be set if the platform supports sharpness adjustments
and the user API strength is not zero. Once sharpness is
enabled, update the strength bit of the register whenever
the user changes the strength value, as the enable bit and
winsize bit remain constant.
Introduce helper to enable, disable and update strength.
Add relavant strength and winsize in both enable and disable.
v2: Introduce get_config for casf[Ankit]
v3: Replace 0 with FILTER_STRENGTH_MASK[Ankit]
v4: After updating strength add win_sz register
v5: Replace u16 with u32 for total_pixel
v6: Add casf logging
v7: Add helper for enable and disable casf
Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251028120747.3027332-4-ankit.k.nautiyal@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
authored by
Nemesa Garg
and committed by
Jani Nikula
74ad9ec9
72a583c2
+184
+1
drivers/gpu/drm/i915/Makefile
+1
drivers/gpu/drm/i915/Makefile
+128
drivers/gpu/drm/i915/display/intel_casf.c
+128
drivers/gpu/drm/i915/display/intel_casf.c
···
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// SPDX-License-Identifier: MIT
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/* Copyright © 2025 Intel Corporation */
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#include <drm/drm_print.h>
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#include "i915_reg.h"
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#include "intel_casf.h"
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#include "intel_casf_regs.h"
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#include "intel_de.h"
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#include "intel_display_regs.h"
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#include "intel_display_types.h"
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#define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080)
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#define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160)
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/**
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* DOC: Content Adaptive Sharpness Filter (CASF)
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*
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* Starting from LNL the display engine supports an
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* adaptive sharpening filter, enhancing the image
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* quality. The display hardware utilizes the second
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* pipe scaler for implementing CASF.
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* If sharpness is being enabled then pipe scaling
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* cannot be used.
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* This filter operates on a region of pixels based
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* on the tap size. Coefficients are used to generate
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* an alpha value which blends the sharpened image to
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* original image.
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*/
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void intel_casf_update_strength(struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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int win_size;
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intel_de_rmw(display, SHARPNESS_CTL(crtc->pipe), FILTER_STRENGTH_MASK,
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FILTER_STRENGTH(crtc_state->hw.casf_params.strength));
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win_size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, 1));
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intel_de_write_fw(display, SKL_PS_WIN_SZ(crtc->pipe, 1), win_size);
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}
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static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state)
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{
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const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
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u32 total_pixels = mode->hdisplay * mode->vdisplay;
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if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER)
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crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_3X3;
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else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER)
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crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_5X5;
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else
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crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_7X7;
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}
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int intel_casf_compute_config(struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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if (!HAS_CASF(display))
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return 0;
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if (crtc_state->uapi.sharpness_strength == 0) {
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crtc_state->hw.casf_params.casf_enable = false;
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crtc_state->hw.casf_params.strength = 0;
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return 0;
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}
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crtc_state->hw.casf_params.casf_enable = true;
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/*
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* HW takes a value in form (1.0 + strength) in 4.4 fixed format.
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* Strength is from 0.0-14.9375 ie from 0-239.
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* User can give value from 0-255 but is clamped to 239.
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* Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125.
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* 6.3125 in 4.4 format is b01100101 which is equal to 101.
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* Also 85 + 16 = 101.
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*/
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crtc_state->hw.casf_params.strength =
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min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10;
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intel_casf_compute_win_size(crtc_state);
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return 0;
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}
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void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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u32 sharp;
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sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe));
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if (sharp & FILTER_EN) {
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if (drm_WARN_ON(display->drm,
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REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) < 16))
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crtc_state->hw.casf_params.strength = 0;
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else
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crtc_state->hw.casf_params.strength =
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REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp);
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crtc_state->hw.casf_params.casf_enable = true;
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crtc_state->hw.casf_params.win_size =
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REG_FIELD_GET(FILTER_SIZE_MASK, sharp);
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}
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}
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void intel_casf_enable(struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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u32 sharpness_ctl;
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sharpness_ctl = FILTER_EN | FILTER_STRENGTH(crtc_state->hw.casf_params.strength);
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sharpness_ctl |= crtc_state->hw.casf_params.win_size;
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intel_de_write(display, SHARPNESS_CTL(crtc->pipe), sharpness_ctl);
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}
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void intel_casf_disable(const struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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intel_de_write(display, SHARPNESS_CTL(crtc->pipe), 0);
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}
+19
drivers/gpu/drm/i915/display/intel_casf.h
+19
drivers/gpu/drm/i915/display/intel_casf.h
···
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2025 Intel Corporation
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*/
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#ifndef __INTEL_CASF_H__
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#define __INTEL_CASF_H__
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#include <linux/types.h>
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struct intel_crtc_state;
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int intel_casf_compute_config(struct intel_crtc_state *crtc_state);
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void intel_casf_update_strength(struct intel_crtc_state *new_crtc_state);
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void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state);
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void intel_casf_enable(struct intel_crtc_state *crtc_state);
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void intel_casf_disable(const struct intel_crtc_state *crtc_state);
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#endif /* __INTEL_CASF_H__ */
+22
drivers/gpu/drm/i915/display/intel_casf_regs.h
+22
drivers/gpu/drm/i915/display/intel_casf_regs.h
···
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2025 Intel Corporation
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*/
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#ifndef __INTEL_CASF_REGS_H__
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#define __INTEL_CASF_REGS_H__
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#include "intel_display_reg_defs.h"
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#define _SHARPNESS_CTL_A 0x682B0
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#define _SHARPNESS_CTL_B 0x68AB0
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#define SHARPNESS_CTL(pipe) _MMIO_PIPE(pipe, _SHARPNESS_CTL_A, _SHARPNESS_CTL_B)
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#define FILTER_EN REG_BIT(31)
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#define FILTER_STRENGTH_MASK REG_GENMASK(15, 8)
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#define FILTER_STRENGTH(x) REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x))
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#define FILTER_SIZE_MASK REG_GENMASK(1, 0)
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#define SHARPNESS_FILTER_SIZE_3X3 REG_FIELD_PREP(FILTER_SIZE_MASK, 0)
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#define SHARPNESS_FILTER_SIZE_5X5 REG_FIELD_PREP(FILTER_SIZE_MASK, 1)
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#define SHARPNESS_FILTER_SIZE_7X7 REG_FIELD_PREP(FILTER_SIZE_MASK, 2)
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#endif /* __INTEL_CASF_REGS__ */
+5
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+5
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
···
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intel_vdsc_state_dump(&p, 0, pipe_config);
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drm_printf(&p, "sharpness strength: %d, sharpness tap size: %d, sharpness enable: %d\n",
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pipe_config->hw.casf_params.strength,
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pipe_config->hw.casf_params.win_size,
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pipe_config->hw.casf_params.casf_enable);
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dump_planes:
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if (!state)
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return;
+7
drivers/gpu/drm/i915/display/intel_display_types.h
+7
drivers/gpu/drm/i915/display/intel_display_types.h
···
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INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE,
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};
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struct intel_casf {
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u8 strength;
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u8 win_size;
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bool casf_enable;
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};
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struct intel_crtc_state {
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/*
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* uapi (drm) state. This is the software state shown to userspace.
···
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struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
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struct drm_display_mode mode, pipe_mode, adjusted_mode;
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enum drm_scaling_filter scaling_filter;
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struct intel_casf casf_params;
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} hw;
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/* actual state of LUTs */
+1
drivers/gpu/drm/i915/display/skl_scaler.c
+1
drivers/gpu/drm/i915/display/skl_scaler.c