Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: qcom: Introduce PCIe UNIPHY 28LP driver
Add Qualcomm PCIe UNIPHY 28LP driver support present in Qualcomm IPQ5332
SoC and the phy init sequence.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250220094251.230936-3-quic_varada@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Nitheesh Sekar
and committed by
Vinod Koul
74badb8b
a2e93488
+299
+12
drivers/phy/qualcomm/Kconfig
+12
drivers/phy/qualcomm/Kconfig
···
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management. This driver is required even for peripheral only or
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host only mode configurations.
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config PHY_QCOM_UNIPHY_PCIE_28LP
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bool "PCIE UNIPHY 28LP PHY driver"
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depends on ARCH_QCOM
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depends on HAS_IOMEM
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depends on OF
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select GENERIC_PHY
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help
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Enable this to support the PCIe UNIPHY 28LP phy transceiver that
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is used with PCIe controllers on Qualcomm IPQ5332 chips. It
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handles PHY initialization, clock management required after
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resetting the hardware and power management.
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config PHY_QCOM_USB_HS
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tristate "Qualcomm USB HS PHY module"
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depends on USB_ULPI_BUS
+1
drivers/phy/qualcomm/Makefile
+1
drivers/phy/qualcomm/Makefile
···
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obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
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obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o
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obj-$(CONFIG_PHY_QCOM_EUSB2_REPEATER) += phy-qcom-eusb2-repeater.o
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obj-$(CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP) += phy-qcom-uniphy-pcie-28lp.o
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obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
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obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
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obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
+286
drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
+286
drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
···
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2025, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/units.h>
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+
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#define RST_ASSERT_DELAY_MIN_US 100
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#define RST_ASSERT_DELAY_MAX_US 150
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#define PIPE_CLK_DELAY_MIN_US 5000
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#define PIPE_CLK_DELAY_MAX_US 5100
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#define CLK_EN_DELAY_MIN_US 30
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#define CLK_EN_DELAY_MAX_US 50
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#define CDR_CTRL_REG_1 0x80
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#define CDR_CTRL_REG_2 0x84
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#define CDR_CTRL_REG_3 0x88
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#define CDR_CTRL_REG_4 0x8c
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#define CDR_CTRL_REG_5 0x90
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#define CDR_CTRL_REG_6 0x94
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#define CDR_CTRL_REG_7 0x98
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#define SSCG_CTRL_REG_1 0x9c
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#define SSCG_CTRL_REG_2 0xa0
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#define SSCG_CTRL_REG_3 0xa4
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#define SSCG_CTRL_REG_4 0xa8
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#define SSCG_CTRL_REG_5 0xac
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#define SSCG_CTRL_REG_6 0xb0
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#define PCS_INTERNAL_CONTROL_2 0x2d8
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+
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#define PHY_CFG_PLLCFG 0x220
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#define PHY_CFG_EIOS_DTCT_REG 0x3e4
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#define PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME 0x3e8
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enum qcom_uniphy_pcie_type {
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PHY_TYPE_PCIE = 1,
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PHY_TYPE_PCIE_GEN2,
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PHY_TYPE_PCIE_GEN3,
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};
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struct qcom_uniphy_pcie_regs {
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u32 offset;
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u32 val;
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};
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struct qcom_uniphy_pcie_data {
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int lane_offset; /* offset between the lane register bases */
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u32 phy_type;
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const struct qcom_uniphy_pcie_regs *init_seq;
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u32 init_seq_num;
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u32 pipe_clk_rate;
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};
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struct qcom_uniphy_pcie {
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struct phy phy;
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struct device *dev;
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const struct qcom_uniphy_pcie_data *data;
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struct clk_bulk_data *clks;
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int num_clks;
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struct reset_control *resets;
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void __iomem *base;
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int lanes;
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};
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#define phy_to_dw_phy(x) container_of((x), struct qca_uni_pcie_phy, phy)
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static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = {
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{
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.offset = PHY_CFG_PLLCFG,
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.val = 0x30,
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}, {
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.offset = PHY_CFG_EIOS_DTCT_REG,
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.val = 0x53ef,
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}, {
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.offset = PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME,
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.val = 0xcf,
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},
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};
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static const struct qcom_uniphy_pcie_data ipq5332_data = {
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.lane_offset = 0x800,
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.phy_type = PHY_TYPE_PCIE_GEN3,
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.init_seq = ipq5332_regs,
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.init_seq_num = ARRAY_SIZE(ipq5332_regs),
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.pipe_clk_rate = 250 * MEGA,
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};
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static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy)
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{
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const struct qcom_uniphy_pcie_data *data = phy->data;
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const struct qcom_uniphy_pcie_regs *init_seq;
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void __iomem *base = phy->base;
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int lane, i;
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for (lane = 0; lane < phy->lanes; lane++) {
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init_seq = data->init_seq;
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for (i = 0; i < data->init_seq_num; i++)
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writel(init_seq[i].val, base + init_seq[i].offset);
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base += data->lane_offset;
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}
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}
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static int qcom_uniphy_pcie_power_off(struct phy *x)
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{
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struct qcom_uniphy_pcie *phy = phy_get_drvdata(x);
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clk_bulk_disable_unprepare(phy->num_clks, phy->clks);
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return reset_control_assert(phy->resets);
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}
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static int qcom_uniphy_pcie_power_on(struct phy *x)
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{
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struct qcom_uniphy_pcie *phy = phy_get_drvdata(x);
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int ret;
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ret = reset_control_assert(phy->resets);
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if (ret) {
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dev_err(phy->dev, "reset assert failed (%d)\n", ret);
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return ret;
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}
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usleep_range(RST_ASSERT_DELAY_MIN_US, RST_ASSERT_DELAY_MAX_US);
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ret = reset_control_deassert(phy->resets);
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if (ret) {
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dev_err(phy->dev, "reset deassert failed (%d)\n", ret);
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return ret;
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}
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usleep_range(PIPE_CLK_DELAY_MIN_US, PIPE_CLK_DELAY_MAX_US);
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ret = clk_bulk_prepare_enable(phy->num_clks, phy->clks);
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if (ret) {
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dev_err(phy->dev, "clk prepare and enable failed %d\n", ret);
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return ret;
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}
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usleep_range(CLK_EN_DELAY_MIN_US, CLK_EN_DELAY_MAX_US);
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qcom_uniphy_pcie_init(phy);
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return 0;
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}
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static inline int qcom_uniphy_pcie_get_resources(struct platform_device *pdev,
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struct qcom_uniphy_pcie *phy)
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{
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struct resource *res;
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phy->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(phy->base))
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return PTR_ERR(phy->base);
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phy->num_clks = devm_clk_bulk_get_all(phy->dev, &phy->clks);
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if (phy->num_clks < 0)
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return phy->num_clks;
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phy->resets = devm_reset_control_array_get_exclusive(phy->dev);
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if (IS_ERR(phy->resets))
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return PTR_ERR(phy->resets);
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return 0;
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}
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/*
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* Register a fixed rate pipe clock.
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*
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* The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
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* controls it. The <s>_pipe_clk coming out of the GCC is requested
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* by the PHY driver for its operations.
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* We register the <s>_pipe_clksrc here. The gcc driver takes care
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* of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
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* Below picture shows this relationship.
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*
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* +---------------+
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* | PHY block |<<---------------------------------------+
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* | | |
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* | +-------+ | +-----+ |
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* I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
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* clk | +-------+ | +-----+
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* +---------------+
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*/
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static inline int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, int id)
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{
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const struct qcom_uniphy_pcie_data *data = phy->data;
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struct clk_hw *hw;
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char name[64];
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snprintf(name, sizeof(name), "phy%d_pipe_clk_src", id);
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hw = devm_clk_hw_register_fixed_rate(phy->dev, name, NULL, 0,
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data->pipe_clk_rate);
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if (IS_ERR(hw))
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return dev_err_probe(phy->dev, PTR_ERR(hw),
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"Unable to register %s\n", name);
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return devm_of_clk_add_hw_provider(phy->dev, of_clk_hw_simple_get, hw);
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}
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static const struct of_device_id qcom_uniphy_pcie_id_table[] = {
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{
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.compatible = "qcom,ipq5332-uniphy-pcie-phy",
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.data = &ipq5332_data,
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}, {
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/* Sentinel */
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},
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};
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MODULE_DEVICE_TABLE(of, qcom_uniphy_pcie_id_table);
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static const struct phy_ops pcie_ops = {
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.power_on = qcom_uniphy_pcie_power_on,
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.power_off = qcom_uniphy_pcie_power_off,
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.owner = THIS_MODULE,
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};
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static int qcom_uniphy_pcie_probe(struct platform_device *pdev)
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{
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struct phy_provider *phy_provider;
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struct device *dev = &pdev->dev;
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struct qcom_uniphy_pcie *phy;
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struct phy *generic_phy;
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int ret;
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phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
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if (!phy)
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return -ENOMEM;
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platform_set_drvdata(pdev, phy);
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phy->dev = &pdev->dev;
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phy->data = of_device_get_match_data(dev);
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if (!phy->data)
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return -EINVAL;
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ret = of_property_read_u32(dev_of_node(dev), "num-lanes", &phy->lanes);
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if (ret)
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return dev_err_probe(dev, ret, "Couldn't read num-lanes\n");
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ret = qcom_uniphy_pcie_get_resources(pdev, phy);
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if (ret < 0)
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return dev_err_probe(&pdev->dev, ret,
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"failed to get resources: %d\n", ret);
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generic_phy = devm_phy_create(phy->dev, NULL, &pcie_ops);
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if (IS_ERR(generic_phy))
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return PTR_ERR(generic_phy);
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phy_set_drvdata(generic_phy, phy);
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ret = phy_pipe_clk_register(phy, generic_phy->id);
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if (ret)
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dev_err(&pdev->dev, "failed to register phy pipe clk\n");
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phy_provider = devm_of_phy_provider_register(phy->dev,
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of_phy_simple_xlate);
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if (IS_ERR(phy_provider))
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return PTR_ERR(phy_provider);
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return 0;
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}
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static struct platform_driver qcom_uniphy_pcie_driver = {
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.probe = qcom_uniphy_pcie_probe,
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.driver = {
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.name = "qcom-uniphy-pcie",
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.of_match_table = qcom_uniphy_pcie_id_table,
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},
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};
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module_platform_driver(qcom_uniphy_pcie_driver);
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MODULE_DESCRIPTION("PCIE QCOM UNIPHY driver");
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MODULE_LICENSE("GPL");