Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'pci/controller/rzg3s-host'
- Use pci_generic_config_write(), not custom wrapper, since we don't need
the writability provided by the wrapper (Claudiu Beznea)
- Drop lock around RZG3S_PCI_MSIRS and RZG3S_PCI_PINTRCVIS updates since
they are RW1C registers (Claudiu Beznea)
- Fix a device node reference leak in rzg3s_pcie_host_parse_port() (Felix
Gu)
* pci/controller/rzg3s-host:
PCI: rzg3s-host: Fix device node reference leak in rzg3s_pcie_host_parse_port()
PCI: rzg3s-host: Drop the lock on RZG3S_PCI_MSIRS and RZG3S_PCI_PINTRCVIS
PCI: rzg3s-host: Use pci_generic_config_write() for the root bus
+9
-28
+9
-28
drivers/pci/controller/pcie-rzg3s-host.c
+9
-28
drivers/pci/controller/pcie-rzg3s-host.c
···
73
73
#define RZG3S_PCI_PINTRCVIE_INTX(i) BIT(i)
74
74
#define RZG3S_PCI_PINTRCVIE_MSI BIT(4)
75
75
76
+
/* Register is R/W1C, it doesn't require locking. */
76
77
#define RZG3S_PCI_PINTRCVIS 0x114
77
78
#define RZG3S_PCI_PINTRCVIS_INTX(i) BIT(i)
78
79
#define RZG3S_PCI_PINTRCVIS_MSI BIT(4)
···
115
114
#define RZG3S_PCI_MSIRE_ENA BIT(0)
116
115
117
116
#define RZG3S_PCI_MSIRM(id) (0x608 + (id) * 0x10)
117
+
118
+
/* Register is R/W1C, it doesn't require locking. */
118
119
#define RZG3S_PCI_MSIRS(id) (0x60c + (id) * 0x10)
119
120
120
121
#define RZG3S_PCI_AWBASEL(id) (0x1000 + (id) * 0x20)
···
442
439
return host->pcie + where;
443
440
}
444
441
445
-
/* Serialized by 'pci_lock' */
446
-
static int rzg3s_pcie_root_write(struct pci_bus *bus, unsigned int devfn,
447
-
int where, int size, u32 val)
448
-
{
449
-
struct rzg3s_pcie_host *host = bus->sysdata;
450
-
int ret;
451
-
452
-
/* Enable access control to the CFGU */
453
-
writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
454
-
host->axi + RZG3S_PCI_PERM);
455
-
456
-
ret = pci_generic_config_write(bus, devfn, where, size, val);
457
-
458
-
/* Disable access control to the CFGU */
459
-
writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
460
-
461
-
return ret;
462
-
}
463
-
464
442
static struct pci_ops rzg3s_pcie_root_ops = {
465
443
.read = pci_generic_config_read,
466
-
.write = rzg3s_pcie_root_write,
444
+
.write = pci_generic_config_write,
467
445
.map_bus = rzg3s_pcie_root_map_bus,
468
446
};
469
447
···
509
525
struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi);
510
526
u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG;
511
527
u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG;
512
-
513
-
guard(raw_spinlock_irqsave)(&host->hw_lock);
514
528
515
529
writel_relaxed(BIT(reg_bit), host->axi + RZG3S_PCI_MSIRS(reg_id));
516
530
}
···
841
859
{
842
860
struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d);
843
861
844
-
guard(raw_spinlock_irqsave)(&host->hw_lock);
845
-
846
862
rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS,
847
863
RZG3S_PCI_PINTRCVIS_INTX(d->hwirq),
848
864
RZG3S_PCI_PINTRCVIS_INTX(d->hwirq));
···
1045
1065
writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L);
1046
1066
writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U);
1047
1067
1068
+
/* Disable access control to the CFGU */
1069
+
writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
1070
+
1048
1071
/* Update bus info */
1049
1072
writeb_relaxed(primary_bus, host->pcie + PCI_PRIMARY_BUS);
1050
1073
writeb_relaxed(secondary_bus, host->pcie + PCI_SECONDARY_BUS);
1051
1074
writeb_relaxed(subordinate_bus, host->pcie + PCI_SUBORDINATE_BUS);
1052
-
1053
-
/* Disable access control to the CFGU */
1054
-
writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
1055
1075
1056
1076
return 0;
1057
1077
}
···
1142
1162
1143
1163
static int rzg3s_pcie_host_parse_port(struct rzg3s_pcie_host *host)
1144
1164
{
1145
-
struct device_node *of_port = of_get_next_child(host->dev->of_node, NULL);
1165
+
struct device_node *of_port __free(device_node) =
1166
+
of_get_next_child(host->dev->of_node, NULL);
1146
1167
struct rzg3s_pcie_port *port = &host->port;
1147
1168
int ret;
1148
1169