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drm/radeon: Use RMW accessors for changing LNKCTL2

Convert open coded RMW accesses for LNKCTL2 to use
pcie_capability_clear_and_set_word() which makes its easier to
understand what the code tries to do.

LNKCTL2 is not really owned by any driver because it is a collection of
control bits that PCI core might need to touch. RMW accessors already
have support for proper locking for a selected set of registers
(LNKCTL2 is not yet among them but likely will be in the future) to
avoid losing concurrent updates.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Suggested-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Ilpo Järvinen and committed by
Alex Deucher 756762ae 145242ed

+30 -50
+15 -25
drivers/gpu/drm/radeon/cik.c
··· 9592 9592 PCI_EXP_LNKCTL_HAWD); 9593 9593 9594 9594 /* linkctl2 */ 9595 - pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 9596 - &tmp16); 9597 - tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 9598 - PCI_EXP_LNKCTL2_TX_MARGIN); 9599 - tmp16 |= (bridge_cfg2 & 9600 - (PCI_EXP_LNKCTL2_ENTER_COMP | 9601 - PCI_EXP_LNKCTL2_TX_MARGIN)); 9602 - pcie_capability_write_word(root, 9603 - PCI_EXP_LNKCTL2, 9604 - tmp16); 9605 - 9606 - pcie_capability_read_word(rdev->pdev, 9607 - PCI_EXP_LNKCTL2, 9608 - &tmp16); 9609 - tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 9610 - PCI_EXP_LNKCTL2_TX_MARGIN); 9611 - tmp16 |= (gpu_cfg2 & 9612 - (PCI_EXP_LNKCTL2_ENTER_COMP | 9613 - PCI_EXP_LNKCTL2_TX_MARGIN)); 9614 - pcie_capability_write_word(rdev->pdev, 9615 - PCI_EXP_LNKCTL2, 9616 - tmp16); 9595 + pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL2, 9596 + PCI_EXP_LNKCTL2_ENTER_COMP | 9597 + PCI_EXP_LNKCTL2_TX_MARGIN, 9598 + bridge_cfg2 | 9599 + (PCI_EXP_LNKCTL2_ENTER_COMP | 9600 + PCI_EXP_LNKCTL2_TX_MARGIN)); 9601 + pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL2, 9602 + PCI_EXP_LNKCTL2_ENTER_COMP | 9603 + PCI_EXP_LNKCTL2_TX_MARGIN, 9604 + gpu_cfg2 | 9605 + (PCI_EXP_LNKCTL2_ENTER_COMP | 9606 + PCI_EXP_LNKCTL2_TX_MARGIN)); 9617 9607 9618 9608 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 9619 9609 tmp &= ~LC_SET_QUIESCE; ··· 9617 9627 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; 9618 9628 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 9619 9629 9620 - pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16); 9621 - tmp16 &= ~PCI_EXP_LNKCTL2_TLS; 9630 + tmp16 = 0; 9622 9631 if (speed_cap == PCIE_SPEED_8_0GT) 9623 9632 tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ 9624 9633 else if (speed_cap == PCIE_SPEED_5_0GT) 9625 9634 tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ 9626 9635 else 9627 9636 tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ 9628 - pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16); 9637 + pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL2, 9638 + PCI_EXP_LNKCTL2_TLS, tmp16); 9629 9639 9630 9640 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 9631 9641 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
+15 -25
drivers/gpu/drm/radeon/si.c
··· 7174 7174 PCI_EXP_LNKCTL_HAWD); 7175 7175 7176 7176 /* linkctl2 */ 7177 - pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 7178 - &tmp16); 7179 - tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 7180 - PCI_EXP_LNKCTL2_TX_MARGIN); 7181 - tmp16 |= (bridge_cfg2 & 7182 - (PCI_EXP_LNKCTL2_ENTER_COMP | 7183 - PCI_EXP_LNKCTL2_TX_MARGIN)); 7184 - pcie_capability_write_word(root, 7185 - PCI_EXP_LNKCTL2, 7186 - tmp16); 7187 - 7188 - pcie_capability_read_word(rdev->pdev, 7189 - PCI_EXP_LNKCTL2, 7190 - &tmp16); 7191 - tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 7192 - PCI_EXP_LNKCTL2_TX_MARGIN); 7193 - tmp16 |= (gpu_cfg2 & 7194 - (PCI_EXP_LNKCTL2_ENTER_COMP | 7195 - PCI_EXP_LNKCTL2_TX_MARGIN)); 7196 - pcie_capability_write_word(rdev->pdev, 7197 - PCI_EXP_LNKCTL2, 7198 - tmp16); 7177 + pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL2, 7178 + PCI_EXP_LNKCTL2_ENTER_COMP | 7179 + PCI_EXP_LNKCTL2_TX_MARGIN, 7180 + bridge_cfg2 & 7181 + (PCI_EXP_LNKCTL2_ENTER_COMP | 7182 + PCI_EXP_LNKCTL2_TX_MARGIN)); 7183 + pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL2, 7184 + PCI_EXP_LNKCTL2_ENTER_COMP | 7185 + PCI_EXP_LNKCTL2_TX_MARGIN, 7186 + gpu_cfg2 & 7187 + (PCI_EXP_LNKCTL2_ENTER_COMP | 7188 + PCI_EXP_LNKCTL2_TX_MARGIN)); 7199 7189 7200 7190 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 7201 7191 tmp &= ~LC_SET_QUIESCE; ··· 7199 7209 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; 7200 7210 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 7201 7211 7202 - pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16); 7203 - tmp16 &= ~PCI_EXP_LNKCTL2_TLS; 7212 + tmp16 = 0; 7204 7213 if (speed_cap == PCIE_SPEED_8_0GT) 7205 7214 tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ 7206 7215 else if (speed_cap == PCIE_SPEED_5_0GT) 7207 7216 tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ 7208 7217 else 7209 7218 tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ 7210 - pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16); 7219 + pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL2, 7220 + PCI_EXP_LNKCTL2_TLS, tmp16); 7211 7221 7212 7222 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 7213 7223 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;