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leds: leds-is31fl32xx: Add support for is31fl3236a

Also add an additional and optional control register for setting the
output PWM frequency to 22kHz. The default is 3kHz and this option puts
the operational frequency outside of the audible range.

Signed-off-by: Pawel Zalewski <pzalewski@thegoodpenguin.co.uk>
Link: https://lore.kernel.org/r/20250723-leds-is31fl3236a-v6-3-210328058625@thegoodpenguin.co.uk
Signed-off-by: Lee Jones <lee@kernel.org>

authored by

Pawel Zalewski and committed by
Lee Jones
758e7433 8f5ae30d

+41 -6
+41 -6
drivers/leds/leds-is31fl32xx.c
··· 32 32 #define IS31FL3216_CONFIG_SSD_ENABLE BIT(7) 33 33 #define IS31FL3216_CONFIG_SSD_DISABLE 0 34 34 35 + #define IS31FL32XX_PWM_FREQUENCY_22KHZ 0x01 36 + 35 37 struct is31fl32xx_priv; 36 38 struct is31fl32xx_led_data { 37 39 struct led_classdev cdev; ··· 55 53 * @pwm_update_reg : address of PWM Update register 56 54 * @global_control_reg : address of Global Control register (optional) 57 55 * @reset_reg : address of Reset register (optional) 56 + * @output_frequency_setting_reg: address of output frequency register (optional) 58 57 * @pwm_register_base : address of first PWM register 59 58 * @pwm_registers_reversed: : true if PWM registers count down instead of up 60 59 * @led_control_register_base : address of first LED control register (optional) ··· 79 76 u8 pwm_update_reg; 80 77 u8 global_control_reg; 81 78 u8 reset_reg; 79 + u8 output_frequency_setting_reg; 82 80 u8 pwm_register_base; 83 81 bool pwm_registers_reversed; 84 82 u8 led_control_register_base; ··· 94 90 .pwm_update_reg = 0x25, 95 91 .global_control_reg = 0x4a, 96 92 .reset_reg = 0x4f, 93 + .output_frequency_setting_reg = IS31FL32XX_REG_NONE, 94 + .pwm_register_base = 0x01, 95 + .led_control_register_base = 0x26, 96 + .enable_bits_per_led_control_register = 1, 97 + }; 98 + 99 + static const struct is31fl32xx_chipdef is31fl3236a_cdef = { 100 + .channels = 36, 101 + .shutdown_reg = 0x00, 102 + .pwm_update_reg = 0x25, 103 + .global_control_reg = 0x4a, 104 + .reset_reg = 0x4f, 105 + .output_frequency_setting_reg = 0x4b, 97 106 .pwm_register_base = 0x01, 98 107 .led_control_register_base = 0x26, 99 108 .enable_bits_per_led_control_register = 1, ··· 118 101 .pwm_update_reg = 0x25, 119 102 .global_control_reg = 0x4a, 120 103 .reset_reg = 0x4f, 104 + .output_frequency_setting_reg = IS31FL32XX_REG_NONE, 121 105 .pwm_register_base = 0x05, 122 106 .led_control_register_base = 0x2a, 123 107 .enable_bits_per_led_control_register = 1, ··· 130 112 .pwm_update_reg = 0x16, 131 113 .global_control_reg = IS31FL32XX_REG_NONE, 132 114 .reset_reg = 0x17, 115 + .output_frequency_setting_reg = IS31FL32XX_REG_NONE, 133 116 .pwm_register_base = 0x01, 134 117 .led_control_register_base = 0x13, 135 118 .enable_bits_per_led_control_register = 6, ··· 145 126 .pwm_update_reg = 0xB0, 146 127 .global_control_reg = IS31FL32XX_REG_NONE, 147 128 .reset_reg = IS31FL32XX_REG_NONE, 129 + .output_frequency_setting_reg = IS31FL32XX_REG_NONE, 148 130 .pwm_register_base = 0x10, 149 131 .pwm_registers_reversed = true, 150 132 .led_control_register_base = 0x01, ··· 383 363 static int is31fl32xx_parse_dt(struct device *dev, 384 364 struct is31fl32xx_priv *priv) 385 365 { 366 + const struct is31fl32xx_chipdef *cdef = priv->cdef; 386 367 int ret = 0; 368 + 369 + if ((cdef->output_frequency_setting_reg != IS31FL32XX_REG_NONE) && 370 + of_property_read_bool(dev_of_node(dev), "issi,22khz-pwm")) { 371 + 372 + ret = is31fl32xx_write(priv, cdef->output_frequency_setting_reg, 373 + IS31FL32XX_PWM_FREQUENCY_22KHZ); 374 + 375 + if (ret) { 376 + dev_err(dev, "Failed to write output PWM frequency register\n"); 377 + return ret; 378 + } 379 + } 387 380 388 381 for_each_available_child_of_node_scoped(dev_of_node(dev), child) { 389 382 struct led_init_data init_data = {}; ··· 437 404 } 438 405 439 406 static const struct of_device_id of_is31fl32xx_match[] = { 440 - { .compatible = "issi,is31fl3236", .data = &is31fl3236_cdef, }, 441 - { .compatible = "issi,is31fl3235", .data = &is31fl3235_cdef, }, 442 - { .compatible = "issi,is31fl3218", .data = &is31fl3218_cdef, }, 443 - { .compatible = "si-en,sn3218", .data = &is31fl3218_cdef, }, 444 - { .compatible = "issi,is31fl3216", .data = &is31fl3216_cdef, }, 445 - { .compatible = "si-en,sn3216", .data = &is31fl3216_cdef, }, 407 + { .compatible = "issi,is31fl3236", .data = &is31fl3236_cdef, }, 408 + { .compatible = "issi,is31fl3236a", .data = &is31fl3236a_cdef, }, 409 + { .compatible = "issi,is31fl3235", .data = &is31fl3235_cdef, }, 410 + { .compatible = "issi,is31fl3218", .data = &is31fl3218_cdef, }, 411 + { .compatible = "si-en,sn3218", .data = &is31fl3218_cdef, }, 412 + { .compatible = "issi,is31fl3216", .data = &is31fl3216_cdef, }, 413 + { .compatible = "si-en,sn3216", .data = &is31fl3216_cdef, }, 446 414 {}, 447 415 }; 448 416 ··· 500 466 */ 501 467 static const struct i2c_device_id is31fl32xx_id[] = { 502 468 { "is31fl3236" }, 469 + { "is31fl3236a" }, 503 470 { "is31fl3235" }, 504 471 { "is31fl3218" }, 505 472 { "sn3218" },