tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'qcom-arm32-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

Qualcomm Arm32 DeviceTree updates for v6.16

Introduce support for the AP8064-based LG Nexus 4. MSM8226 is extended
with modem-related features, the LTE-capable variant MSM8926 is
introduced, and modem support is enabled on Samsung Galaxy Tab 4.

Display-related clocks and power-domains are defined for the simple
framebuffer of Motorola Moto G, to allow booting without
clk_ignore_unused and pd_ignore_unused.

On MSM8960 SDCC BAM and thermal sensor (tsens) is introduced.

* tag 'qcom-arm32-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
ARM: dts: qcom: apq8064: move replicator out of soc node
ARM: dts: qcom: apq8064: use new compatible for SPS SIC device
ARM: dts: qcom: apq8064: use new compatible for SFPB device
ARM: dts: qcom: apq8064 merge hw splinlock into corresponding syscon device
ARM: dts: qcom: apq8064: add missing clocks to the timer node
ARM: dts: qcom: apq8064-lg-nexus4-mako: Enable WiFi
ARM: dts: qcom: msm8226-motorola-falcon: specify vddio_disp output voltage
ARM: dts: qcom: msm8226-motorola-falcon: limit TPS65132 to 5.4V
ARM: dts: qcom: msm8226-motorola-falcon: add I2C clock frequencies
ARM: dts: qcom: msm8226-motorola-falcon: add clocks, power-domain to simpleFB
ARM: dts: qcom: ipq4019: Drop redundant CPU "clock-latency"
ARM: dts: qcom: sdx55/sdx65: Fix CPU power-domain-names
ARM: dts: qcom: msm8974: Use the header with DSI phy clock IDs
ARM: dts: qcom: msm8226: Use the header with DSI phy clock IDs

Link: https://lore.kernel.org/r/20250513214111.43401-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann 759dd3fe 2b183108

+99 -67
+18 -4
arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts
··· 31 31 vsp-supply = <&reg_lcd_pos>; 32 32 vsn-supply = <&reg_lcd_neg>; 33 33 vddio-supply = <&vddio_disp_vreg>; 34 + clocks = <&mmcc MDSS_AHB_CLK>, 35 + <&mmcc MDSS_AXI_CLK>, 36 + <&mmcc MDSS_BYTE0_CLK>, 37 + <&mmcc MDSS_ESC0_CLK>, 38 + <&mmcc MDSS_MDP_CLK>, 39 + <&mmcc MMSS_MISC_AHB_CLK>, 40 + <&mmcc MDSS_PCLK0_CLK>, 41 + <&mmcc MDSS_VSYNC_CLK>; 42 + power-domains = <&mmcc MDSS_GDSC>; 34 43 }; 35 44 }; 36 45 ··· 62 53 }; 63 54 }; 64 55 56 + /* TI TPS22902 */ 65 57 vddio_disp_vreg: regulator-vddio-disp { 66 58 compatible = "regulator-fixed"; 67 59 regulator-name = "vddio_disp"; 60 + regulator-min-microvolt = <1800000>; 61 + regulator-max-microvolt = <1800000>; 68 62 gpio = <&tlmm 34 GPIO_ACTIVE_HIGH>; 69 63 vin-supply = <&pm8226_l8>; 70 64 startup-delay-us = <300>; ··· 109 97 }; 110 98 111 99 &blsp1_i2c2 { 100 + clock-frequency = <100000>; 112 101 status = "okay"; 113 102 114 103 magnetometer@c { ··· 139 126 }; 140 127 141 128 &blsp1_i2c3 { 129 + clock-frequency = <400000>; 142 130 status = "okay"; 143 131 144 132 regulator@3e { ··· 150 136 151 137 reg_lcd_pos: outp { 152 138 regulator-name = "outp"; 153 - regulator-min-microvolt = <4000000>; 154 - regulator-max-microvolt = <6000000>; 139 + regulator-min-microvolt = <5400000>; 140 + regulator-max-microvolt = <5400000>; 155 141 regulator-active-discharge = <1>; 156 142 regulator-boot-on; 157 143 enable-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>; ··· 159 145 160 146 reg_lcd_neg: outn { 161 147 regulator-name = "outn"; 162 - regulator-min-microvolt = <4000000>; 163 - regulator-max-microvolt = <6000000>; 148 + regulator-min-microvolt = <5400000>; 149 + regulator-max-microvolt = <5400000>; 164 150 regulator-active-discharge = <1>; 165 151 regulator-boot-on; 166 152 enable-gpios = <&tlmm 33 GPIO_ACTIVE_HIGH>;
+18
arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts
··· 86 86 status = "okay"; 87 87 }; 88 88 89 + &riva { 90 + pinctrl-names = "default"; 91 + pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>; 92 + 93 + vddcx-supply = <&pm8921_s3>; 94 + vddmx-supply = <&pm8921_l24>; 95 + vddpx-supply = <&pm8921_s4>; 96 + 97 + status = "okay"; 98 + 99 + iris { 100 + vddxo-supply = <&pm8921_l4>; 101 + vddrfa-supply = <&pm8921_s2>; 102 + vddpa-supply = <&pm8921_l10>; 103 + vdddig-supply = <&pm8921_lvs2>; 104 + }; 105 + }; 106 + 89 107 &rpm { 90 108 regulators { 91 109 compatible = "qcom,rpm-pm8921-regulators";
+43 -45
arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
··· 213 213 }; 214 214 }; 215 215 216 - sfpb_mutex: hwmutex { 217 - compatible = "qcom,sfpb-mutex"; 218 - syscon = <&sfpb_wrapper_mutex 0x604 0x4>; 219 - #hwlock-cells = <1>; 220 - }; 221 - 222 216 smem { 223 217 compatible = "qcom,smem"; 224 218 memory-region = <&smem_region>; ··· 278 284 }; 279 285 }; 280 286 287 + replicator { 288 + compatible = "arm,coresight-static-replicator"; 289 + 290 + clocks = <&rpmcc RPM_QDSS_CLK>; 291 + clock-names = "apb_pclk"; 292 + 293 + in-ports { 294 + port { 295 + replicator_in: endpoint { 296 + remote-endpoint = <&funnel_out>; 297 + }; 298 + }; 299 + }; 300 + 301 + out-ports { 302 + #address-cells = <1>; 303 + #size-cells = <0>; 304 + 305 + port@0 { 306 + reg = <0>; 307 + replicator_out0: endpoint { 308 + remote-endpoint = <&etb_in>; 309 + }; 310 + }; 311 + 312 + port@1 { 313 + reg = <1>; 314 + replicator_out1: endpoint { 315 + remote-endpoint = <&tpiu_in>; 316 + }; 317 + }; 318 + }; 319 + }; 320 + 281 321 soc: soc { 282 322 #address-cells = <1>; 283 323 #size-cells = <1>; ··· 333 305 pinctrl-0 = <&ps_hold_default_state>; 334 306 }; 335 307 336 - sfpb_wrapper_mutex: syscon@1200000 { 337 - compatible = "syscon"; 338 - reg = <0x01200000 0x8000>; 308 + sfpb_mutex: hwmutex@1200600 { 309 + compatible = "qcom,sfpb-mutex"; 310 + reg = <0x01200600 0x100>; 311 + #hwlock-cells = <1>; 339 312 }; 340 313 341 314 intc: interrupt-controller@2000000 { ··· 355 326 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 356 327 reg = <0x0200a000 0x100>; 357 328 clock-frequency = <27000000>; 329 + clocks = <&sleep_clk>; 330 + clock-names = "sleep"; 358 331 cpu-offset = <0x80000>; 359 332 }; 360 333 ··· 436 405 }; 437 406 }; 438 407 439 - sps_sic_non_secure: sps-sic-non-secure@12100000 { 440 - compatible = "syscon"; 408 + sps_sic_non_secure: interrupt-controller@12100000 { 409 + compatible = "qcom,apq8064-sps-sic", "syscon"; 441 410 reg = <0x12100000 0x10000>; 442 411 }; 443 412 ··· 1120 1089 }; 1121 1090 1122 1091 mmss_sfpb: syscon@5700000 { 1123 - compatible = "syscon"; 1092 + compatible = "qcom,apq8064-mmss-sfpb", "syscon"; 1124 1093 reg = <0x5700000 0x70>; 1125 1094 }; 1126 1095 ··· 1558 1527 port { 1559 1528 tpiu_in: endpoint { 1560 1529 remote-endpoint = <&replicator_out1>; 1561 - }; 1562 - }; 1563 - }; 1564 - }; 1565 - 1566 - replicator { 1567 - compatible = "arm,coresight-static-replicator"; 1568 - 1569 - clocks = <&rpmcc RPM_QDSS_CLK>; 1570 - clock-names = "apb_pclk"; 1571 - 1572 - out-ports { 1573 - #address-cells = <1>; 1574 - #size-cells = <0>; 1575 - 1576 - port@0 { 1577 - reg = <0>; 1578 - replicator_out0: endpoint { 1579 - remote-endpoint = <&etb_in>; 1580 - }; 1581 - }; 1582 - port@1 { 1583 - reg = <1>; 1584 - replicator_out1: endpoint { 1585 - remote-endpoint = <&tpiu_in>; 1586 - }; 1587 - }; 1588 - }; 1589 - 1590 - in-ports { 1591 - port { 1592 - replicator_in: endpoint { 1593 - remote-endpoint = <&funnel_out>; 1594 1530 }; 1595 1531 }; 1596 1532 };
-4
arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
··· 53 53 reg = <0x0>; 54 54 clocks = <&gcc GCC_APPS_CLK_SRC>; 55 55 clock-frequency = <0>; 56 - clock-latency = <256000>; 57 56 operating-points-v2 = <&cpu0_opp_table>; 58 57 }; 59 58 ··· 66 67 reg = <0x1>; 67 68 clocks = <&gcc GCC_APPS_CLK_SRC>; 68 69 clock-frequency = <0>; 69 - clock-latency = <256000>; 70 70 operating-points-v2 = <&cpu0_opp_table>; 71 71 }; 72 72 ··· 79 81 reg = <0x2>; 80 82 clocks = <&gcc GCC_APPS_CLK_SRC>; 81 83 clock-frequency = <0>; 82 - clock-latency = <256000>; 83 84 operating-points-v2 = <&cpu0_opp_table>; 84 85 }; 85 86 ··· 92 95 reg = <0x3>; 93 96 clocks = <&gcc GCC_APPS_CLK_SRC>; 94 97 clock-frequency = <0>; 95 - clock-latency = <256000>; 96 98 operating-points-v2 = <&cpu0_opp_table>; 97 99 }; 98 100
+5 -4
arch/arm/boot/dts/qcom/qcom-msm8226.dtsi
··· 6 6 /dts-v1/; 7 7 8 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 + #include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 9 10 #include <dt-bindings/clock/qcom,gcc-msm8974.h> 10 11 #include <dt-bindings/clock/qcom,mmcc-msm8974.h> 11 12 #include <dt-bindings/clock/qcom,rpmcc.h> ··· 1139 1138 <&gcc GPLL0_VOTE>, 1140 1139 <&gcc GPLL1_VOTE>, 1141 1140 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 1142 - <&mdss_dsi0_phy 1>, 1143 - <&mdss_dsi0_phy 0>; 1141 + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 1142 + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>; 1144 1143 clock-names = "xo", 1145 1144 "mmss_gpll0_vote", 1146 1145 "gpll0_vote", ··· 1216 1215 1217 1216 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1218 1217 <&mmcc PCLK0_CLK_SRC>; 1219 - assigned-clock-parents = <&mdss_dsi0_phy 0>, 1220 - <&mdss_dsi0_phy 1>; 1218 + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1219 + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1221 1220 1222 1221 clocks = <&mmcc MDSS_MDP_CLK>, 1223 1222 <&mmcc MDSS_AHB_CLK>,
+13 -8
arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
··· 3 3 4 4 #include <dt-bindings/interconnect/qcom,msm8974.h> 5 5 #include <dt-bindings/interrupt-controller/arm-gic.h> 6 + #include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 6 7 #include <dt-bindings/clock/qcom,gcc-msm8974.h> 7 8 #include <dt-bindings/clock/qcom,mmcc-msm8974.h> 8 9 #include <dt-bindings/clock/qcom,rpmcc.h> ··· 1872 1871 <&gcc GPLL0_VOTE>, 1873 1872 <&gcc GPLL1_VOTE>, 1874 1873 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 1875 - <&mdss_dsi0_phy 1>, 1876 - <&mdss_dsi0_phy 0>, 1877 - <&mdss_dsi1_phy 1>, 1878 - <&mdss_dsi1_phy 0>, 1874 + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 1875 + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1876 + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 1877 + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 1879 1878 <0>, 1880 1879 <0>, 1881 1880 <0>; ··· 1962 1961 interrupt-parent = <&mdss>; 1963 1962 interrupts = <4>; 1964 1963 1965 - assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 1966 - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1964 + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1965 + <&mmcc PCLK0_CLK_SRC>; 1966 + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1967 + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1967 1968 1968 1969 clocks = <&mmcc MDSS_MDP_CLK>, 1969 1970 <&mmcc MDSS_AHB_CLK>, ··· 2035 2032 interrupt-parent = <&mdss>; 2036 2033 interrupts = <4>; 2037 2034 2038 - assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 2039 - assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 2035 + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, 2036 + <&mmcc PCLK1_CLK_SRC>; 2037 + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 2038 + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 2040 2039 2041 2040 clocks = <&mmcc MDSS_MDP_CLK>, 2042 2041 <&mmcc MDSS_AHB_CLK>,
+1 -1
arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
··· 57 57 enable-method = "psci"; 58 58 clocks = <&apcs>; 59 59 power-domains = <&rpmhpd SDX55_CX>; 60 - power-domain-names = "rpmhpd"; 60 + power-domain-names = "perf"; 61 61 operating-points-v2 = <&cpu_opp_table>; 62 62 }; 63 63 };
+1 -1
arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
··· 58 58 enable-method = "psci"; 59 59 clocks = <&apcs>; 60 60 power-domains = <&rpmhpd SDX65_CX_AO>; 61 - power-domain-names = "rpmhpd"; 61 + power-domain-names = "perf"; 62 62 operating-points-v2 = <&cpu_opp_table>; 63 63 }; 64 64 };