Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v7.0-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij:
- Implement .get_direction() in the spmi-gpio gpio_chip
Recent changes makes this start to print warnings and it's not nice,
let's just fix it
- Clamp the return value of gpio_get() in the Renesas RZA1 driver
- Add the GPIO_GENERIC dependency to the STM32 HDP driver
- Modify the Mediatek driver to accept devices that do not use external
interrupts (EINT) at all
- Fix flag propagation in the Sunxi driver, so that we can fix an issue
with uninitialized pins in a follow-up patch using said flags
* tag 'pinctrl-v7.0-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: sunxi: fix gpiochip_lock_as_irq() failure when pinmux is unknown
pinctrl: sunxi: pass down flags to pinctrl routines
pinctrl: mediatek: common: Fix probe failure for devices without EINT
pinctrl: stm32: fix HDP driver dependency on GPIO_GENERIC
pinctrl: renesas: rza1: Normalize return value of gpio_get()
pinctrl: qcom: spmi-gpio: implement .get_direction()
pinctrl: renesas: rzt2h: Fix invalid wait context
pinctrl: renesas: rzt2h: Fix device node leak in rzt2h_gpio_register()
+67
-23
+6
-3
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+6
-3
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
···
1135
1135
goto chip_error;
1136
1136
}
1137
1137
1138
-
ret = mtk_eint_init(pctl, pdev);
1139
-
if (ret)
1140
-
goto chip_error;
1138
+
/* Only initialize EINT if we have EINT pins */
1139
+
if (data->eint_hw.ap_num > 0) {
1140
+
ret = mtk_eint_init(pctl, pdev);
1141
+
if (ret)
1142
+
goto chip_error;
1143
+
}
1141
1144
1142
1145
return 0;
1143
1146
+16
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
+16
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
···
723
723
.pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
724
724
};
725
725
726
+
static int pmic_gpio_get_direction(struct gpio_chip *chip, unsigned pin)
727
+
{
728
+
struct pmic_gpio_state *state = gpiochip_get_data(chip);
729
+
struct pmic_gpio_pad *pad;
730
+
731
+
pad = state->ctrl->desc->pins[pin].drv_data;
732
+
733
+
if (!pad->is_enabled || pad->analog_pass ||
734
+
(!pad->input_enabled && !pad->output_enabled))
735
+
return -EINVAL;
736
+
737
+
/* Make sure the state is aligned on what pmic_gpio_get() returns */
738
+
return pad->input_enabled ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
739
+
}
740
+
726
741
static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
727
742
{
728
743
struct pmic_gpio_state *state = gpiochip_get_data(chip);
···
816
801
}
817
802
818
803
static const struct gpio_chip pmic_gpio_gpio_template = {
804
+
.get_direction = pmic_gpio_get_direction,
819
805
.direction_input = pmic_gpio_direction_input,
820
806
.direction_output = pmic_gpio_direction_output,
821
807
.get = pmic_gpio_get,
+1
-1
drivers/pinctrl/renesas/pinctrl-rza1.c
+1
-1
drivers/pinctrl/renesas/pinctrl-rza1.c
+8
-7
drivers/pinctrl/renesas/pinctrl-rzt2h.c
+8
-7
drivers/pinctrl/renesas/pinctrl-rzt2h.c
···
85
85
struct gpio_chip gpio_chip;
86
86
struct pinctrl_gpio_range gpio_range;
87
87
DECLARE_BITMAP(used_irqs, RZT2H_INTERRUPTS_NUM);
88
-
spinlock_t lock; /* lock read/write registers */
88
+
raw_spinlock_t lock; /* lock read/write registers */
89
89
struct mutex mutex; /* serialize adding groups and functions */
90
90
bool safety_port_enabled;
91
91
atomic_t wakeup_path;
···
145
145
u64 reg64;
146
146
u16 reg16;
147
147
148
-
guard(spinlock_irqsave)(&pctrl->lock);
148
+
guard(raw_spinlock_irqsave)(&pctrl->lock);
149
149
150
150
/* Set pin to 'Non-use (Hi-Z input protection)' */
151
151
reg16 = rzt2h_pinctrl_readw(pctrl, port, PM(port));
···
474
474
if (ret)
475
475
return ret;
476
476
477
-
guard(spinlock_irqsave)(&pctrl->lock);
477
+
guard(raw_spinlock_irqsave)(&pctrl->lock);
478
478
479
479
/* Select GPIO mode in PMC Register */
480
480
rzt2h_pinctrl_set_gpio_en(pctrl, port, bit, true);
···
487
487
{
488
488
u16 reg;
489
489
490
-
guard(spinlock_irqsave)(&pctrl->lock);
490
+
guard(raw_spinlock_irqsave)(&pctrl->lock);
491
491
492
492
reg = rzt2h_pinctrl_readw(pctrl, port, PM(port));
493
493
reg &= ~PM_PIN_MASK(bit);
···
509
509
if (ret)
510
510
return ret;
511
511
512
-
guard(spinlock_irqsave)(&pctrl->lock);
512
+
guard(raw_spinlock_irqsave)(&pctrl->lock);
513
513
514
514
if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit)) {
515
515
/*
···
547
547
u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
548
548
u8 reg;
549
549
550
-
guard(spinlock_irqsave)(&pctrl->lock);
550
+
guard(raw_spinlock_irqsave)(&pctrl->lock);
551
551
552
552
reg = rzt2h_pinctrl_readb(pctrl, port, P(port));
553
553
if (value)
···
833
833
if (ret)
834
834
return dev_err_probe(dev, ret, "Unable to parse gpio-ranges\n");
835
835
836
+
of_node_put(of_args.np);
836
837
if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
837
838
of_args.args[2] != pctrl->data->n_port_pins)
838
839
return dev_err_probe(dev, -EINVAL,
···
965
964
if (ret)
966
965
return ret;
967
966
968
-
spin_lock_init(&pctrl->lock);
967
+
raw_spin_lock_init(&pctrl->lock);
969
968
mutex_init(&pctrl->mutex);
970
969
platform_set_drvdata(pdev, pctrl);
971
970
+1
drivers/pinctrl/stm32/Kconfig
+1
drivers/pinctrl/stm32/Kconfig
+32
-11
drivers/pinctrl/sunxi/pinctrl-sunxi.c
+32
-11
drivers/pinctrl/sunxi/pinctrl-sunxi.c
···
157
157
const char *pin_name,
158
158
const char *func_name)
159
159
{
160
+
unsigned long variant = pctl->flags & SUNXI_PINCTRL_VARIANT_MASK;
160
161
int i;
161
162
162
163
for (i = 0; i < pctl->desc->npins; i++) {
···
169
168
while (func->name) {
170
169
if (!strcmp(func->name, func_name) &&
171
170
(!func->variant ||
172
-
func->variant & pctl->variant))
171
+
func->variant & variant))
173
172
return func;
174
173
175
174
func++;
···
210
209
const u16 pin_num,
211
210
const u8 muxval)
212
211
{
212
+
unsigned long variant = pctl->flags & SUNXI_PINCTRL_VARIANT_MASK;
213
+
213
214
for (unsigned int i = 0; i < pctl->desc->npins; i++) {
214
215
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
215
216
struct sunxi_desc_function *func = pin->functions;
···
219
216
if (pin->pin.number != pin_num)
220
217
continue;
221
218
222
-
if (pin->variant && !(pctl->variant & pin->variant))
219
+
if (pin->variant && !(variant & pin->variant))
223
220
continue;
224
221
225
222
while (func->name) {
···
1092
1089
{
1093
1090
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1094
1091
struct sunxi_desc_function *func;
1092
+
unsigned int offset;
1093
+
u32 reg, shift, mask;
1094
+
u8 disabled_mux, muxval;
1095
1095
int ret;
1096
1096
1097
1097
func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
···
1102
1096
if (!func)
1103
1097
return -EINVAL;
1104
1098
1105
-
ret = gpiochip_lock_as_irq(pctl->chip,
1106
-
pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
1099
+
offset = pctl->irq_array[d->hwirq] - pctl->desc->pin_base;
1100
+
sunxi_mux_reg(pctl, offset, ®, &shift, &mask);
1101
+
muxval = (readl(pctl->membase + reg) & mask) >> shift;
1102
+
1103
+
/* Change muxing to GPIO INPUT mode if at reset value */
1104
+
if (pctl->flags & SUNXI_PINCTRL_NEW_REG_LAYOUT)
1105
+
disabled_mux = SUN4I_FUNC_DISABLED_NEW;
1106
+
else
1107
+
disabled_mux = SUN4I_FUNC_DISABLED_OLD;
1108
+
1109
+
if (muxval == disabled_mux)
1110
+
sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq],
1111
+
SUN4I_FUNC_INPUT);
1112
+
1113
+
ret = gpiochip_lock_as_irq(pctl->chip, offset);
1107
1114
if (ret) {
1108
1115
dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
1109
1116
irqd_to_hwirq(d));
···
1357
1338
static int sunxi_pinctrl_build_state(struct platform_device *pdev)
1358
1339
{
1359
1340
struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
1341
+
unsigned long variant = pctl->flags & SUNXI_PINCTRL_VARIANT_MASK;
1360
1342
void *ptr;
1361
1343
int i;
1362
1344
···
1382
1362
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1383
1363
struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups;
1384
1364
1385
-
if (pin->variant && !(pctl->variant & pin->variant))
1365
+
if (pin->variant && !(variant & pin->variant))
1386
1366
continue;
1387
1367
1388
1368
group->name = pin->pin.name;
···
1407
1387
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1408
1388
struct sunxi_desc_function *func;
1409
1389
1410
-
if (pin->variant && !(pctl->variant & pin->variant))
1390
+
if (pin->variant && !(variant & pin->variant))
1411
1391
continue;
1412
1392
1413
1393
for (func = pin->functions; func->name; func++) {
1414
-
if (func->variant && !(pctl->variant & func->variant))
1394
+
if (func->variant && !(variant & func->variant))
1415
1395
continue;
1416
1396
1417
1397
/* Create interrupt mapping while we're at it */
···
1439
1419
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1440
1420
struct sunxi_desc_function *func;
1441
1421
1442
-
if (pin->variant && !(pctl->variant & pin->variant))
1422
+
if (pin->variant && !(variant & pin->variant))
1443
1423
continue;
1444
1424
1445
1425
for (func = pin->functions; func->name; func++) {
1446
1426
struct sunxi_pinctrl_function *func_item;
1447
1427
const char **func_grp;
1448
1428
1449
-
if (func->variant && !(pctl->variant & func->variant))
1429
+
if (func->variant && !(variant & func->variant))
1450
1430
continue;
1451
1431
1452
1432
func_item = sunxi_pinctrl_find_function_by_name(pctl,
···
1588
1568
1589
1569
pctl->dev = &pdev->dev;
1590
1570
pctl->desc = desc;
1591
-
pctl->variant = flags & SUNXI_PINCTRL_VARIANT_MASK;
1571
+
pctl->flags = flags;
1592
1572
if (flags & SUNXI_PINCTRL_NEW_REG_LAYOUT) {
1593
1573
pctl->bank_mem_size = D1_BANK_MEM_SIZE;
1594
1574
pctl->pull_regs_offset = D1_PULL_REGS_OFFSET;
···
1624
1604
1625
1605
for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) {
1626
1606
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1607
+
unsigned long variant = pctl->flags & SUNXI_PINCTRL_VARIANT_MASK;
1627
1608
1628
-
if (pin->variant && !(pctl->variant & pin->variant))
1609
+
if (pin->variant && !(variant & pin->variant))
1629
1610
continue;
1630
1611
1631
1612
pins[pin_idx++] = pin->pin;
+3
-1
drivers/pinctrl/sunxi/pinctrl-sunxi.h
+3
-1
drivers/pinctrl/sunxi/pinctrl-sunxi.h
···
86
86
87
87
#define SUN4I_FUNC_INPUT 0
88
88
#define SUN4I_FUNC_IRQ 6
89
+
#define SUN4I_FUNC_DISABLED_OLD 7
90
+
#define SUN4I_FUNC_DISABLED_NEW 15
89
91
90
92
#define SUNXI_PINCTRL_VARIANT_MASK GENMASK(7, 0)
91
93
#define SUNXI_PINCTRL_NEW_REG_LAYOUT BIT(8)
···
176
174
unsigned *irq_array;
177
175
raw_spinlock_t lock;
178
176
struct pinctrl_dev *pctl_dev;
179
-
unsigned long variant;
177
+
unsigned long flags;
180
178
u32 bank_mem_size;
181
179
u32 pull_regs_offset;
182
180
u32 dlevel_field_width;