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pwm: tiehrpwm: Enable pwmchip's parent device before setting configuration

The period and duty cycle configurations on J7200 and J784S4 SoCs
does not get reflected after setting them using sysfs nodes.
This is because at the end of ehrpwm_pwm_config function,
the put_sync function is called which resets the hardware.

Hold the PWM controller out of low-power mode during .apply() to
make sure it accepts the writes to its registers.

This renders the calls to pm_runtime_get_sync() and
pm_runtime_put_sync() in ehrpwm_pwm_config() into no-ops, so
these can be dropped.

Fixes: 5f027d9b83db ("pwm: tiehrpwm: Implement .apply() callback")
Signed-off-by: Gokul Praveen <g-praveen@ti.com>
Suggested-by: Uwe Kleine-König <ukleinek@kernel.org>
Link: https://patch.msgid.link/20260121061134.15466-1-g-praveen@ti.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>

authored by

Gokul Praveen and committed by
Uwe Kleine-König 75e7ed52 dcce06fb

+2 -4
+2 -4
drivers/pwm/pwm-tiehrpwm.c
··· 237 237 if (period_cycles < 1) 238 238 period_cycles = 1; 239 239 240 - pm_runtime_get_sync(pwmchip_parent(chip)); 241 - 242 240 /* Update clock prescaler values */ 243 241 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval); 244 242 ··· 287 289 288 290 if (!(duty_cycles > period_cycles)) 289 291 ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles); 290 - 291 - pm_runtime_put_sync(pwmchip_parent(chip)); 292 292 293 293 return 0; 294 294 } ··· 373 377 { 374 378 int err; 375 379 bool enabled = pwm->state.enabled; 380 + 381 + guard(pm_runtime_active)(pwmchip_parent(chip)); 376 382 377 383 if (state->polarity != pwm->state.polarity) { 378 384 if (enabled) {