drm/amd/powerplay: code clean up in vega10_hwmgr.c

+38 -6

1 changed file

expand all

drivers

gpu

drm

amd

powerplay

hwmgr

vega10_hwmgr.c

+38 -6

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

··· 1182 1182 else 1183 1183 pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( 1184 1184 bios_pcie_table->entries[i].lane_width); 1185 - printk("pcie_table->pcie_lane[%d] is %d %d\n", i, pcie_table->pcie_lane[i], bios_pcie_table->entries[i].lane_width); 1186 1185 if (data->registry_data.pcieClockOverride) 1187 1186 pcie_table->lclk[i] = 1188 1187 data->registry_data.pcieClockOverride; ··· 3023 3024 3024 3025 /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/ 3025 3026 minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock; 3026 - /* minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; */ 3027 + minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; 3027 3028 3028 3029 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 3029 3030 PHM_PlatformCaps_StablePState)) { ··· 3875 3876 { 3876 3877 int result = 0; 3877 3878 enum amd_pp_clock_type clk_type = clock_req->clock_type; 3878 - uint32_t clk_freq = clock_req->clock_freq_in_khz / 100; 3879 + uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 3879 3880 DSPCLK_e clk_select = 0; 3880 3881 uint32_t clk_request = 0; 3881 3882 ··· 3908 3909 return result; 3909 3910 } 3910 3911 3912 + static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr, 3913 + struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table, 3914 + uint32_t frequency) 3915 + { 3916 + uint8_t count; 3917 + uint8_t i; 3918 + 3919 + if (mclk_table == NULL || mclk_table->count == 0) 3920 + return 0; 3921 + 3922 + count = (uint8_t)(mclk_table->count); 3923 + 3924 + for(i = 0; i < count; i++) { 3925 + if(mclk_table->entries[i].clk >= frequency) 3926 + return i; 3927 + } 3928 + 3929 + return i-1; 3930 + } 3931 + 3911 3932 static int vega10_notify_smc_display_config_after_ps_adjustment( 3912 3933 struct pp_hwmgr *hwmgr) 3913 3934 { ··· 3935 3916 (struct vega10_hwmgr *)(hwmgr->backend); 3936 3917 struct vega10_single_dpm_table *dpm_table = 3937 3918 &data->dpm_table.dcef_table; 3919 + struct phm_ppt_v2_information *table_info = 3920 + (struct phm_ppt_v2_information *)hwmgr->pptable; 3921 + struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk; 3922 + uint32_t idx; 3938 3923 uint32_t num_active_disps = 0; 3939 3924 struct cgs_display_info info = {0}; 3940 3925 struct PP_Clocks min_clocks = {0}; ··· 3958 3935 3959 3936 min_clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk; 3960 3937 min_clocks.dcefClockInSR = hwmgr->display_config.min_dcef_deep_sleep_set_clk; 3938 + min_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; 3961 3939 3962 3940 for (i = 0; i < dpm_table->count; i++) { 3963 3941 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock) ··· 3971 3947 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) { 3972 3948 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( 3973 3949 hwmgr->smumgr, PPSMC_MSG_SetMinDeepSleepDcefclk, 3974 - min_clocks.dcefClockInSR), 3950 + min_clocks.dcefClockInSR /100), 3975 3951 "Attempt to set divider for DCEFCLK Failed!",); 3976 - } else 3952 + } else { 3977 3953 pr_info("Attempt to set Hard Min for DCEFCLK Failed!"); 3978 - } else 3954 + } 3955 + } else { 3979 3956 pr_info("Cannot find requested DCEFCLK!"); 3957 + } 3958 + 3959 + if (min_clocks.memoryClock != 0) { 3960 + idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock); 3961 + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx); 3962 + data->dpm_table.mem_table.dpm_state.soft_min_level= idx; 3963 + } 3980 3964 3981 3965 return 0; 3982 3966 }

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