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drm/mediatek: mtk_dsi: enable hs clock during pre-enable

Some bridges, such as the TI SN65DSI83, require the HS clock to be
running in order to lock its PLL during its own pre-enable function.

Without this change, the bridge gives the following error:
sn65dsi83 14-002c: failed to lock PLL, ret=-110
sn65dsi83 14-002c: Unexpected link status 0x01
sn65dsi83 14-002c: reset the pipe

Move the necessary functions from enable to pre-enable.

Signed-off-by: Gary Bisson <bisson.gary@gmail.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org> # Chromebooks
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20260120-mtkdsi-v1-1-b0f4094f3ac3@gmail.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>

authored by

Gary Bisson and committed by
Chun-Kuang Hu 76255024 6de23f81

+17 -18
+17 -18
drivers/gpu/drm/mediatek/mtk_dsi.c
··· 673 673 } 674 674 } 675 675 676 + static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) 677 + { 678 + if (!dsi->lanes_ready) { 679 + dsi->lanes_ready = true; 680 + mtk_dsi_rxtx_control(dsi); 681 + usleep_range(30, 100); 682 + mtk_dsi_reset_dphy(dsi); 683 + mtk_dsi_clk_ulp_mode_leave(dsi); 684 + mtk_dsi_lane0_ulp_mode_leave(dsi); 685 + mtk_dsi_clk_hs_mode(dsi, 0); 686 + usleep_range(1000, 3000); 687 + /* The reaction time after pulling up the mipi signal for dsi_rx */ 688 + } 689 + } 690 + 676 691 static int mtk_dsi_poweron(struct mtk_dsi *dsi) 677 692 { 678 693 struct device *dev = dsi->host.dev; ··· 740 725 mtk_dsi_set_vm_cmd(dsi); 741 726 mtk_dsi_config_vdo_timing(dsi); 742 727 mtk_dsi_set_interrupt_enable(dsi); 728 + mtk_dsi_lane_ready(dsi); 729 + mtk_dsi_clk_hs_mode(dsi, 1); 743 730 744 731 return 0; 745 732 err_disable_engine_clk: ··· 787 770 dsi->lanes_ready = false; 788 771 } 789 772 790 - static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) 791 - { 792 - if (!dsi->lanes_ready) { 793 - dsi->lanes_ready = true; 794 - mtk_dsi_rxtx_control(dsi); 795 - usleep_range(30, 100); 796 - mtk_dsi_reset_dphy(dsi); 797 - mtk_dsi_clk_ulp_mode_leave(dsi); 798 - mtk_dsi_lane0_ulp_mode_leave(dsi); 799 - mtk_dsi_clk_hs_mode(dsi, 0); 800 - usleep_range(1000, 3000); 801 - /* The reaction time after pulling up the mipi signal for dsi_rx */ 802 - } 803 - } 804 - 805 773 static void mtk_output_dsi_enable(struct mtk_dsi *dsi) 806 774 { 807 775 if (dsi->enabled) 808 776 return; 809 777 810 - mtk_dsi_lane_ready(dsi); 811 778 mtk_dsi_set_mode(dsi); 812 - mtk_dsi_clk_hs_mode(dsi, 1); 813 - 814 779 mtk_dsi_start(dsi); 815 780 816 781 dsi->enabled = true;