tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2021-07-30' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"Regular drm fixes pull, seems about the right size, lots of small
fixes across the board, mostly amdgpu, but msm and i915 are in there
along with panel and ttm.

amdgpu:
- Fix resource leak in an error path
- Avoid stack contents exposure in error path
- pmops check fix for S0ix vs S3
- DCN 2.1 display fixes
- DCN 2.0 display fix
- Backlight control fix for laptops with HDR panels
- Maintainers updates

i915:
- Fix vbt port mask
- Fix around reading the right DSC disable fuse in display_ver 10
- Split display version 9 and 10 in intel_setup_outputs

msm:
- iommu fault display fix
- misc dp compliance fixes
- dpu reg sizing fix

panel:
- Fix bpc for ytc700tlag_05_201c

ttm:
- debugfs init fixes"

* tag 'drm-fixes-2021-07-30' of git://anongit.freedesktop.org/drm/drm:
maintainers: add bugs and chat URLs for amdgpu
drm/amdgpu/display: only enable aux backlight control for OLED panels
drm/amd/display: ensure dentist display clock update finished in DCN20
drm/amd/display: Add missing DCN21 IP parameter
drm/amd/display: Guard DST_Y_PREFETCH register overflow in DCN21
drm/amdgpu: Check pmops for desired suspend state
drm/msm/dp: Initialize dp->aux->drm_dev before registration
drm/msm/dp: signal audio plugged change at dp_pm_resume
drm/msm/dp: Initialize the INTF_CONFIG register
drm/msm/dp: use dp_ctrl_off_link_stream during PHY compliance test run
drm/msm: Fix display fault handling
drm/msm/dpu: Fix sm8250_mdp register length
drm/amdgpu: Avoid printing of stack contents on firmware load error
drm/amdgpu: Fix resource leak on probe error path
drm/i915/display: split DISPLAY_VER 9 and 10 in intel_setup_outputs()
drm/i915: fix not reading DSC disable fuse in GLK
drm/i915/bios: Fix ports mask
drm/panel: panel-simple: Fix proper bpc for ytc700tlag_05_201c
drm/ttm: Initialize debugfs from ttm_global_init()

Linus Torvalds 764a5bc8 c71a2f65

+61 -40
+2
MAINTAINERS
··· 15468 15468 L: amd-gfx@lists.freedesktop.org 15469 15469 S: Supported 15470 15470 T: git https://gitlab.freedesktop.org/agd5f/linux.git 15471 + B: https://gitlab.freedesktop.org/drm/amd/-/issues 15472 + C: irc://irc.oftc.net/radeon 15471 15473 F: drivers/gpu/drm/amd/ 15472 15474 F: drivers/gpu/drm/radeon/ 15473 15475 F: include/uapi/drm/amdgpu_drm.h
+2 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
··· 26 26 #include <linux/slab.h> 27 27 #include <linux/power_supply.h> 28 28 #include <linux/pm_runtime.h> 29 + #include <linux/suspend.h> 29 30 #include <acpi/video.h> 30 31 #include <acpi/actbl.h> 31 32 ··· 1043 1042 #if defined(CONFIG_AMD_PMC) || defined(CONFIG_AMD_PMC_MODULE) 1044 1043 if (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0) { 1045 1044 if (adev->flags & AMD_IS_APU) 1046 - return true; 1045 + return pm_suspend_target_state == PM_SUSPEND_TO_IDLE; 1047 1046 } 1048 1047 #endif 1049 1048 return false;
+2 -6
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 3504 3504 r = amdgpu_device_get_job_timeout_settings(adev); 3505 3505 if (r) { 3506 3506 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n"); 3507 - goto failed_unmap; 3507 + return r; 3508 3508 } 3509 3509 3510 3510 /* early init functions */ 3511 3511 r = amdgpu_device_ip_early_init(adev); 3512 3512 if (r) 3513 - goto failed_unmap; 3513 + return r; 3514 3514 3515 3515 /* doorbell bar mapping and doorbell index init*/ 3516 3516 amdgpu_device_doorbell_init(adev); ··· 3735 3735 3736 3736 failed: 3737 3737 amdgpu_vf_error_trans_all(adev); 3738 - 3739 - failed_unmap: 3740 - iounmap(adev->rmmio); 3741 - adev->rmmio = NULL; 3742 3738 3743 3739 return r; 3744 3740 }
+3 -4
drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
··· 67 67 68 68 err = psp_init_asd_microcode(psp, chip_name); 69 69 if (err) 70 - goto out; 70 + return err; 71 71 72 72 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 73 73 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); ··· 80 80 } else { 81 81 err = amdgpu_ucode_validate(adev->psp.ta_fw); 82 82 if (err) 83 - goto out2; 83 + goto out; 84 84 85 85 ta_hdr = (const struct ta_firmware_header_v1_0 *) 86 86 adev->psp.ta_fw->data; ··· 105 105 106 106 return 0; 107 107 108 - out2: 108 + out: 109 109 release_firmware(adev->psp.ta_fw); 110 110 adev->psp.ta_fw = NULL; 111 - out: 112 111 if (err) { 113 112 dev_err(adev->dev, 114 113 "psp v12.0: Failed to load firmware \"%s\"\n",
+2 -2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 2429 2429 max_cll = conn_base->hdr_sink_metadata.hdmi_type1.max_cll; 2430 2430 min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll; 2431 2431 2432 - if (caps->ext_caps->bits.oled == 1 || 2432 + if (caps->ext_caps->bits.oled == 1 /*|| 2433 2433 caps->ext_caps->bits.sdr_aux_backlight_control == 1 || 2434 - caps->ext_caps->bits.hdr_aux_backlight_control == 1) 2434 + caps->ext_caps->bits.hdr_aux_backlight_control == 1*/) 2435 2435 caps->aux_support = true; 2436 2436 2437 2437 if (amdgpu_backlight == 0)
+1 -1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
··· 197 197 198 198 REG_UPDATE(DENTIST_DISPCLK_CNTL, 199 199 DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider); 200 - // REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100); 200 + REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 1000); 201 201 REG_UPDATE(DENTIST_DISPCLK_CNTL, 202 202 DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider); 203 203 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);
+1
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
··· 109 109 .max_page_table_levels = 4, 110 110 .pte_chunk_size_kbytes = 2, 111 111 .meta_chunk_size_kbytes = 2, 112 + .min_meta_chunk_size_bytes = 256, 112 113 .writeback_chunk_size_kbytes = 2, 113 114 .line_buffer_size_bits = 789504, 114 115 .is_line_buffer_bpp_fixed = 0,
+3
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
··· 841 841 else 842 842 *DestinationLinesForPrefetch = dst_y_prefetch_equ; 843 843 844 + // Limit to prevent overflow in DST_Y_PREFETCH register 845 + *DestinationLinesForPrefetch = dml_min(*DestinationLinesForPrefetch, 63.75); 846 + 844 847 dml_print("DML: VStartup: %d\n", VStartup); 845 848 dml_print("DML: TCalc: %f\n", TCalc); 846 849 dml_print("DML: TWait: %f\n", TWait);
+2 -1
drivers/gpu/drm/i915/display/intel_bios.c
··· 2166 2166 init_vbt_missing_defaults(struct drm_i915_private *i915) 2167 2167 { 2168 2168 enum port port; 2169 - int ports = PORT_A | PORT_B | PORT_C | PORT_D | PORT_E | PORT_F; 2169 + int ports = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | 2170 + BIT(PORT_D) | BIT(PORT_E) | BIT(PORT_F); 2170 2171 2171 2172 if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915)) 2172 2173 return;
+7 -1
drivers/gpu/drm/i915/display/intel_display.c
··· 11361 11361 intel_ddi_init(dev_priv, PORT_B); 11362 11362 intel_ddi_init(dev_priv, PORT_C); 11363 11363 vlv_dsi_init(dev_priv); 11364 - } else if (DISPLAY_VER(dev_priv) >= 9) { 11364 + } else if (DISPLAY_VER(dev_priv) == 10) { 11365 11365 intel_ddi_init(dev_priv, PORT_A); 11366 11366 intel_ddi_init(dev_priv, PORT_B); 11367 11367 intel_ddi_init(dev_priv, PORT_C); 11368 11368 intel_ddi_init(dev_priv, PORT_D); 11369 11369 intel_ddi_init(dev_priv, PORT_E); 11370 11370 intel_ddi_init(dev_priv, PORT_F); 11371 + } else if (DISPLAY_VER(dev_priv) >= 9) { 11372 + intel_ddi_init(dev_priv, PORT_A); 11373 + intel_ddi_init(dev_priv, PORT_B); 11374 + intel_ddi_init(dev_priv, PORT_C); 11375 + intel_ddi_init(dev_priv, PORT_D); 11376 + intel_ddi_init(dev_priv, PORT_E); 11371 11377 } else if (HAS_DDI(dev_priv)) { 11372 11378 u32 found; 11373 11379
+5 -4
drivers/gpu/drm/i915/intel_device_info.c
··· 325 325 info->pipe_mask &= ~BIT(PIPE_C); 326 326 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 327 327 } 328 - } else if (HAS_DISPLAY(dev_priv) && GRAPHICS_VER(dev_priv) >= 9) { 328 + } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) { 329 329 u32 dfsm = intel_de_read(dev_priv, SKL_DFSM); 330 330 331 331 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { ··· 340 340 info->pipe_mask &= ~BIT(PIPE_C); 341 341 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 342 342 } 343 - if (GRAPHICS_VER(dev_priv) >= 12 && 343 + 344 + if (DISPLAY_VER(dev_priv) >= 12 && 344 345 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { 345 346 info->pipe_mask &= ~BIT(PIPE_D); 346 347 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); ··· 353 352 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) 354 353 info->display.has_fbc = 0; 355 354 356 - if (GRAPHICS_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 355 + if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 357 356 info->display.has_dmc = 0; 358 357 359 - if (GRAPHICS_VER(dev_priv) >= 10 && 358 + if (DISPLAY_VER(dev_priv) >= 10 && 360 359 (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE)) 361 360 info->display.has_dsc = 0; 362 361 }
+1 -1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
··· 296 296 static const struct dpu_mdp_cfg sm8250_mdp[] = { 297 297 { 298 298 .name = "top_0", .id = MDP_TOP, 299 - .base = 0x0, .len = 0x45C, 299 + .base = 0x0, .len = 0x494, 300 300 .features = 0, 301 301 .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ 302 302 .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+1
drivers/gpu/drm/msm/dp/dp_catalog.c
··· 771 771 dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, 772 772 dp_catalog->width_blanking); 773 773 dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, dp_catalog->dp_active); 774 + dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, 0); 774 775 return 0; 775 776 } 776 777
+1 -1
drivers/gpu/drm/msm/dp/dp_ctrl.c
··· 1526 1526 * running. Add the global reset just before disabling the 1527 1527 * link clocks and core clocks. 1528 1528 */ 1529 - ret = dp_ctrl_off(&ctrl->dp_ctrl); 1529 + ret = dp_ctrl_off_link_stream(&ctrl->dp_ctrl); 1530 1530 if (ret) { 1531 1531 DRM_ERROR("failed to disable DP controller\n"); 1532 1532 return ret;
+5
drivers/gpu/drm/msm/dp/dp_display.c
··· 219 219 goto end; 220 220 } 221 221 222 + dp->aux->drm_dev = drm; 222 223 rc = dp_aux_register(dp->aux); 223 224 if (rc) { 224 225 DRM_ERROR("DRM DP AUX register failed\n"); ··· 1311 1310 dp->dp_display.is_connected = true; 1312 1311 else 1313 1312 dp->dp_display.is_connected = false; 1313 + 1314 + dp_display_handle_plugged_change(g_dp_display, 1315 + dp->dp_display.is_connected); 1316 + 1314 1317 1315 1318 mutex_unlock(&dp->event_mutex); 1316 1319
+10 -1
drivers/gpu/drm/msm/msm_iommu.c
··· 142 142 .tlb_add_page = msm_iommu_tlb_add_page, 143 143 }; 144 144 145 + static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, 146 + unsigned long iova, int flags, void *arg); 147 + 145 148 struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) 146 149 { 147 150 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(parent->dev); ··· 159 156 ttbr1_cfg = adreno_smmu->get_ttbr1_cfg(adreno_smmu->cookie); 160 157 if (!ttbr1_cfg) 161 158 return ERR_PTR(-ENODEV); 159 + 160 + /* 161 + * Defer setting the fault handler until we have a valid adreno_smmu 162 + * to avoid accidentially installing a GPU specific fault handler for 163 + * the display's iommu 164 + */ 165 + iommu_set_fault_handler(iommu->domain, msm_fault_handler, iommu); 162 166 163 167 pagetable = kzalloc(sizeof(*pagetable), GFP_KERNEL); 164 168 if (!pagetable) ··· 310 300 311 301 iommu->domain = domain; 312 302 msm_mmu_init(&iommu->base, dev, &funcs, MSM_MMU_IOMMU); 313 - iommu_set_fault_handler(domain, msm_fault_handler, iommu); 314 303 315 304 atomic_set(&iommu->pagetables, 0); 316 305
+1 -1
drivers/gpu/drm/panel/panel-simple.c
··· 4166 4166 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4167 4167 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4168 4168 .num_modes = 1, 4169 - .bpc = 6, 4169 + .bpc = 8, 4170 4170 .size = { 4171 4171 .width = 154, 4172 4172 .height = 90,
+12
drivers/gpu/drm/ttm/ttm_device.c
··· 44 44 struct ttm_global ttm_glob; 45 45 EXPORT_SYMBOL(ttm_glob); 46 46 47 + struct dentry *ttm_debugfs_root; 48 + 47 49 static void ttm_global_release(void) 48 50 { 49 51 struct ttm_global *glob = &ttm_glob; ··· 55 53 goto out; 56 54 57 55 ttm_pool_mgr_fini(); 56 + debugfs_remove(ttm_debugfs_root); 58 57 59 58 __free_page(glob->dummy_read_page); 60 59 memset(glob, 0, sizeof(*glob)); ··· 75 72 goto out; 76 73 77 74 si_meminfo(&si); 75 + 76 + ttm_debugfs_root = debugfs_create_dir("ttm", NULL); 77 + if (IS_ERR(ttm_debugfs_root)) { 78 + ret = PTR_ERR(ttm_debugfs_root); 79 + ttm_debugfs_root = NULL; 80 + goto out; 81 + } 78 82 79 83 /* Limit the number of pages in the pool to about 50% of the total 80 84 * system memory. ··· 110 100 debugfs_create_atomic_t("buffer_objects", 0444, ttm_debugfs_root, 111 101 &glob->bo_count); 112 102 out: 103 + if (ret && ttm_debugfs_root) 104 + debugfs_remove(ttm_debugfs_root); 113 105 if (ret) 114 106 --ttm_glob_use_count; 115 107 mutex_unlock(&ttm_global_mutex);
-16
drivers/gpu/drm/ttm/ttm_module.c
··· 72 72 return tmp; 73 73 } 74 74 75 - struct dentry *ttm_debugfs_root; 76 - 77 - static int __init ttm_init(void) 78 - { 79 - ttm_debugfs_root = debugfs_create_dir("ttm", NULL); 80 - return 0; 81 - } 82 - 83 - static void __exit ttm_exit(void) 84 - { 85 - debugfs_remove(ttm_debugfs_root); 86 - } 87 - 88 - module_init(ttm_init); 89 - module_exit(ttm_exit); 90 - 91 75 MODULE_AUTHOR("Thomas Hellstrom, Jerome Glisse"); 92 76 MODULE_DESCRIPTION("TTM memory manager subsystem (for DRM device)"); 93 77 MODULE_LICENSE("GPL and additional rights");