Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2025-02-28' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie:
"This week's fixes pull, amdgpu mostly, with some xe and a few misc
others, the fb defio fix is bit of a change, but it avoids some nasty
NULL pointer crashes due to defio assuming page backing in places it
didn't have pages.
amdgpu:
- Legacy dpm suspend/resume fix
- Runtime PM fix for DELL G5 SE
- MAINTAINERS updates
- Enforce Isolation fixes
- mailmap update
- EDID reading i2c fix
- PSR fix
- eDP fix
- HPD interrupt handling fix
- Clear memory fix
amdkfd:
- MQD handling fix
vkms:
- fix rounding error
imagination:
- header fix
nouveau:
- connector status fix
fb/defio:
- NULL ptr fix for defio drivers
i915:
- Fix encoder HW state readout for DP UHBR MST
xe:
- OA uapi fix (Umesh)
- Userptr related fixes
- Remove a duplicated register entry
- Scheduler related fix to prevent exec races when freeing it"
* tag 'drm-fixes-2025-02-28' of https://gitlab.freedesktop.org/drm/kernel: (25 commits)
drm/fbdev-dma: Add shadow buffering for deferred I/O
drm/nouveau: Do not override forced connector status
drm/i915/dp_mst: Fix encoder HW state readout for UHBR MST
drm/xe: cancel pending job timer before freeing scheduler
drm/xe/regs: remove a duplicate definition for RING_CTL_SIZE(size)
drm/imagination: remove unnecessary header include path
drm/amdgpu: init return value in amdgpu_ttm_clear_buffer
drm/amd/display: Fix HPD after gpu reset
drm/amd/display: add a quirk to enable eDP0 on DP1
drm/amd/display: Disable PSR-SU on eDP panels
MAINTAINERS: Update AMDGPU DML maintainers info
drm/amd/display: restore edid reading from a given i2c adapter
mailmap: Add entry for Rodrigo Siqueira
MAINTAINERS: Change my role from Maintainer to Reviewer
drm/amdgpu/mes: keep enforce isolation up to date
drm/amdgpu/gfx: only call mes for enforce isolation if supported
MAINTAINERS: update amdgpu maintainers list
drm/amdgpu: disable BAR resize on Dell G5 SE
drm/amdkfd: Preserve cp_hqd_pq_control on update_mqd
amdgpu/pm/legacy: fix suspend/resume issues
...
+407
-124
+3
.mailmap
+3
.mailmap
···
522
522
Nadia Yvette Chambers <nyc@holomorphy.com> William Lee Irwin III <wli@holomorphy.com>
523
523
Naoya Horiguchi <nao.horiguchi@gmail.com> <n-horiguchi@ah.jp.nec.com>
524
524
Naoya Horiguchi <nao.horiguchi@gmail.com> <naoya.horiguchi@nec.com>
525
+
Natalie Vock <natalie.vock@gmx.de> <friedrich.vock@gmx.de>
525
526
Nathan Chancellor <nathan@kernel.org> <natechancellor@gmail.com>
526
527
Naveen N Rao <naveen@kernel.org> <naveen.n.rao@linux.ibm.com>
527
528
Naveen N Rao <naveen@kernel.org> <naveen.n.rao@linux.vnet.ibm.com>
···
614
613
Richard Leitner <richard.leitner@linux.dev> <richard.leitner@skidata.com>
615
614
Robert Foss <rfoss@kernel.org> <robert.foss@linaro.org>
616
615
Rocky Liao <quic_rjliao@quicinc.com> <rjliao@codeaurora.org>
616
+
Rodrigo Siqueira <siqueira@igalia.com> <rodrigosiqueiramelo@gmail.com>
617
+
Rodrigo Siqueira <siqueira@igalia.com> <Rodrigo.Siqueira@amd.com>
617
618
Roman Gushchin <roman.gushchin@linux.dev> <guro@fb.com>
618
619
Roman Gushchin <roman.gushchin@linux.dev> <guroan@gmail.com>
619
620
Roman Gushchin <roman.gushchin@linux.dev> <klamm@yandex-team.ru>
+13
-3
MAINTAINERS
+13
-3
MAINTAINERS
···
1046
1046
AMD DISPLAY CORE
1047
1047
M: Harry Wentland <harry.wentland@amd.com>
1048
1048
M: Leo Li <sunpeng.li@amd.com>
1049
-
M: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
1049
+
R: Rodrigo Siqueira <siqueira@igalia.com>
1050
1050
L: amd-gfx@lists.freedesktop.org
1051
1051
S: Supported
1052
1052
T: git https://gitlab.freedesktop.org/agd5f/linux.git
1053
1053
F: drivers/gpu/drm/amd/display/
1054
1054
1055
1055
AMD DISPLAY CORE - DML
1056
-
M: Chaitanya Dhere <chaitanya.dhere@amd.com>
1056
+
M: Austin Zheng <austin.zheng@amd.com>
1057
1057
M: Jun Lei <jun.lei@amd.com>
1058
1058
S: Supported
1059
1059
F: drivers/gpu/drm/amd/display/dc/dml/
···
5925
5925
F: tools/testing/selftests/cgroup/test_cpuset.c
5926
5926
F: tools/testing/selftests/cgroup/test_cpuset_prs.sh
5927
5927
F: tools/testing/selftests/cgroup/test_cpuset_v1_base.sh
5928
+
5929
+
CONTROL GROUP - DEVICE MEMORY CONTROLLER (DMEM)
5930
+
M: Maarten Lankhorst <dev@lankhorst.se>
5931
+
M: Maxime Ripard <mripard@kernel.org>
5932
+
M: Natalie Vock <natalie.vock@gmx.de>
5933
+
L: cgroups@vger.kernel.org
5934
+
L: dri-devel@lists.freedesktop.org
5935
+
S: Maintained
5936
+
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
5937
+
F: include/linux/cgroup_dmem.h
5938
+
F: kernel/cgroup/dmem.c
5928
5939
5929
5940
CONTROL GROUP - MEMORY RESOURCE CONTROLLER (MEMCG)
5930
5941
M: Johannes Weiner <hannes@cmpxchg.org>
···
19666
19655
RADEON and AMDGPU DRM DRIVERS
19667
19656
M: Alex Deucher <alexander.deucher@amd.com>
19668
19657
M: Christian König <christian.koenig@amd.com>
19669
-
M: Xinhui Pan <Xinhui.Pan@amd.com>
19670
19658
L: amd-gfx@lists.freedesktop.org
19671
19659
S: Supported
19672
19660
B: https://gitlab.freedesktop.org/drm/amd/-/issues
+7
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+7
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
···
1638
1638
if (amdgpu_sriov_vf(adev))
1639
1639
return 0;
1640
1640
1641
+
/* resizing on Dell G5 SE platforms causes problems with runtime pm */
1642
+
if ((amdgpu_runtime_pm != 0) &&
1643
+
adev->pdev->vendor == PCI_VENDOR_ID_ATI &&
1644
+
adev->pdev->device == 0x731f &&
1645
+
adev->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
1646
+
return 0;
1647
+
1641
1648
/* PCI_EXT_CAP_ID_VNDR extended capability is located at 0x100 */
1642
1649
if (!pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_VNDR))
1643
1650
DRM_WARN("System can't access extended configuration space, please check!!\n");
+4
-7
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+4
-7
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
···
1638
1638
}
1639
1639
1640
1640
mutex_lock(&adev->enforce_isolation_mutex);
1641
-
1642
1641
for (i = 0; i < num_partitions; i++) {
1643
-
if (adev->enforce_isolation[i] && !partition_values[i]) {
1642
+
if (adev->enforce_isolation[i] && !partition_values[i])
1644
1643
/* Going from enabled to disabled */
1645
1644
amdgpu_vmid_free_reserved(adev, AMDGPU_GFXHUB(i));
1646
-
amdgpu_mes_set_enforce_isolation(adev, i, false);
1647
-
} else if (!adev->enforce_isolation[i] && partition_values[i]) {
1645
+
else if (!adev->enforce_isolation[i] && partition_values[i])
1648
1646
/* Going from disabled to enabled */
1649
1647
amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(i));
1650
-
amdgpu_mes_set_enforce_isolation(adev, i, true);
1651
-
}
1652
1648
adev->enforce_isolation[i] = partition_values[i];
1653
1649
}
1654
-
1655
1650
mutex_unlock(&adev->enforce_isolation_mutex);
1651
+
1652
+
amdgpu_mes_update_enforce_isolation(adev);
1656
1653
1657
1654
return count;
1658
1655
}
+19
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+19
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
···
1681
1681
}
1682
1682
1683
1683
/* Fix me -- node_id is used to identify the correct MES instances in the future */
1684
-
int amdgpu_mes_set_enforce_isolation(struct amdgpu_device *adev, uint32_t node_id, bool enable)
1684
+
static int amdgpu_mes_set_enforce_isolation(struct amdgpu_device *adev,
1685
+
uint32_t node_id, bool enable)
1685
1686
{
1686
1687
struct mes_misc_op_input op_input = {0};
1687
1688
int r;
···
1701
1700
dev_err(adev->dev, "failed to change_config.\n");
1702
1701
1703
1702
error:
1703
+
return r;
1704
+
}
1705
+
1706
+
int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev)
1707
+
{
1708
+
int i, r = 0;
1709
+
1710
+
if (adev->enable_mes && adev->gfx.enable_cleaner_shader) {
1711
+
mutex_lock(&adev->enforce_isolation_mutex);
1712
+
for (i = 0; i < (adev->xcp_mgr ? adev->xcp_mgr->num_xcps : 1); i++) {
1713
+
if (adev->enforce_isolation[i])
1714
+
r |= amdgpu_mes_set_enforce_isolation(adev, i, true);
1715
+
else
1716
+
r |= amdgpu_mes_set_enforce_isolation(adev, i, false);
1717
+
}
1718
+
mutex_unlock(&adev->enforce_isolation_mutex);
1719
+
}
1704
1720
return r;
1705
1721
}
1706
1722
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
···
534
534
535
535
bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev);
536
536
537
-
int amdgpu_mes_set_enforce_isolation(struct amdgpu_device *adev, uint32_t node_id, bool enable);
537
+
int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev);
538
538
539
539
#endif /* __AMDGPU_MES_H__ */
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+4
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+4
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+4
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+4
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+4
-2
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+4
-2
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
···
107
107
m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
108
108
0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
109
109
110
+
m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
111
+
m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;
110
112
m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;
111
113
112
114
m->cp_mqd_base_addr_lo = lower_32_bits(addr);
···
169
167
170
168
m = get_mqd(mqd);
171
169
172
-
m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
170
+
m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK;
173
171
m->cp_hqd_pq_control |=
174
172
ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
175
-
m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;
173
+
176
174
pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
177
175
178
176
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
+3
-2
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
+3
-2
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
···
154
154
m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
155
155
0x55 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
156
156
157
+
m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
158
+
m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;
157
159
m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;
158
160
159
161
m->cp_mqd_base_addr_lo = lower_32_bits(addr);
···
223
221
224
222
m = get_mqd(mqd);
225
223
226
-
m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
224
+
m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK;
227
225
m->cp_hqd_pq_control |=
228
226
ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
229
-
m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;
230
227
pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
231
228
232
229
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
+3
-2
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
+3
-2
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
···
121
121
m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
122
122
0x55 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
123
123
124
+
m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
125
+
m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;
124
126
m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;
125
127
126
128
m->cp_mqd_base_addr_lo = lower_32_bits(addr);
···
186
184
187
185
m = get_mqd(mqd);
188
186
189
-
m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
187
+
m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK;
190
188
m->cp_hqd_pq_control |=
191
189
ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
192
-
m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;
193
190
pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
194
191
195
192
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
+4
-1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+4
-1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
···
183
183
m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
184
184
0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
185
185
186
+
m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
187
+
m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;
188
+
186
189
m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;
187
190
188
191
m->cp_mqd_base_addr_lo = lower_32_bits(addr);
···
248
245
249
246
m = get_mqd(mqd);
250
247
251
-
m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
248
+
m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK;
252
249
m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
253
250
pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
254
251
+77
-9
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+77
-9
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
1618
1618
return false;
1619
1619
}
1620
1620
1621
-
static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1621
+
struct amdgpu_dm_quirks {
1622
+
bool aux_hpd_discon;
1623
+
bool support_edp0_on_dp1;
1624
+
};
1625
+
1626
+
static struct amdgpu_dm_quirks quirk_entries = {
1627
+
.aux_hpd_discon = false,
1628
+
.support_edp0_on_dp1 = false
1629
+
};
1630
+
1631
+
static int edp0_on_dp1_callback(const struct dmi_system_id *id)
1632
+
{
1633
+
quirk_entries.support_edp0_on_dp1 = true;
1634
+
return 0;
1635
+
}
1636
+
1637
+
static int aux_hpd_discon_callback(const struct dmi_system_id *id)
1638
+
{
1639
+
quirk_entries.aux_hpd_discon = true;
1640
+
return 0;
1641
+
}
1642
+
1643
+
static const struct dmi_system_id dmi_quirk_table[] = {
1622
1644
{
1645
+
.callback = aux_hpd_discon_callback,
1623
1646
.matches = {
1624
1647
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1625
1648
DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1626
1649
},
1627
1650
},
1628
1651
{
1652
+
.callback = aux_hpd_discon_callback,
1629
1653
.matches = {
1630
1654
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1631
1655
DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1632
1656
},
1633
1657
},
1634
1658
{
1659
+
.callback = aux_hpd_discon_callback,
1635
1660
.matches = {
1636
1661
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1637
1662
DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1638
1663
},
1639
1664
},
1640
1665
{
1666
+
.callback = aux_hpd_discon_callback,
1641
1667
.matches = {
1642
1668
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1643
1669
DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1644
1670
},
1645
1671
},
1646
1672
{
1673
+
.callback = aux_hpd_discon_callback,
1647
1674
.matches = {
1648
1675
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1649
1676
DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1650
1677
},
1651
1678
},
1652
1679
{
1680
+
.callback = aux_hpd_discon_callback,
1653
1681
.matches = {
1654
1682
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1655
1683
DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1656
1684
},
1657
1685
},
1658
1686
{
1687
+
.callback = aux_hpd_discon_callback,
1659
1688
.matches = {
1660
1689
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1661
1690
DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1662
1691
},
1663
1692
},
1664
1693
{
1694
+
.callback = aux_hpd_discon_callback,
1665
1695
.matches = {
1666
1696
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1667
1697
DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1668
1698
},
1669
1699
},
1670
1700
{
1701
+
.callback = aux_hpd_discon_callback,
1671
1702
.matches = {
1672
1703
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1673
1704
DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1705
+
},
1706
+
},
1707
+
{
1708
+
.callback = edp0_on_dp1_callback,
1709
+
.matches = {
1710
+
DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1711
+
DMI_MATCH(DMI_PRODUCT_NAME, "HP Elite mt645 G8 Mobile Thin Client"),
1712
+
},
1713
+
},
1714
+
{
1715
+
.callback = edp0_on_dp1_callback,
1716
+
.matches = {
1717
+
DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1718
+
DMI_MATCH(DMI_PRODUCT_NAME, "HP EliteBook 665 16 inch G11 Notebook PC"),
1674
1719
},
1675
1720
},
1676
1721
{}
1677
1722
/* TODO: refactor this from a fixed table to a dynamic option */
1678
1723
};
1679
1724
1680
-
static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1725
+
static void retrieve_dmi_info(struct amdgpu_display_manager *dm, struct dc_init_data *init_data)
1681
1726
{
1682
-
const struct dmi_system_id *dmi_id;
1727
+
int dmi_id;
1728
+
struct drm_device *dev = dm->ddev;
1683
1729
1684
1730
dm->aux_hpd_discon_quirk = false;
1731
+
init_data->flags.support_edp0_on_dp1 = false;
1685
1732
1686
-
dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1687
-
if (dmi_id) {
1733
+
dmi_id = dmi_check_system(dmi_quirk_table);
1734
+
1735
+
if (!dmi_id)
1736
+
return;
1737
+
1738
+
if (quirk_entries.aux_hpd_discon) {
1688
1739
dm->aux_hpd_discon_quirk = true;
1689
-
DRM_INFO("aux_hpd_discon_quirk attached\n");
1740
+
drm_info(dev, "aux_hpd_discon_quirk attached\n");
1741
+
}
1742
+
if (quirk_entries.support_edp0_on_dp1) {
1743
+
init_data->flags.support_edp0_on_dp1 = true;
1744
+
drm_info(dev, "aux_hpd_discon_quirk attached\n");
1690
1745
}
1691
1746
}
1692
1747
···
2049
1994
if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0))
2050
1995
init_data.num_virtual_links = 1;
2051
1996
2052
-
retrieve_dmi_info(&adev->dm);
1997
+
retrieve_dmi_info(&adev->dm, &init_data);
2053
1998
2054
1999
if (adev->dm.bb_from_dmub)
2055
2000
init_data.bb_from_dmub = adev->dm.bb_from_dmub;
···
7295
7240
struct dc_link *dc_link = aconnector->dc_link;
7296
7241
struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
7297
7242
const struct drm_edid *drm_edid;
7243
+
struct i2c_adapter *ddc;
7298
7244
7299
-
drm_edid = drm_edid_read(connector);
7245
+
if (dc_link && dc_link->aux_mode)
7246
+
ddc = &aconnector->dm_dp_aux.aux.ddc;
7247
+
else
7248
+
ddc = &aconnector->i2c->base;
7249
+
7250
+
drm_edid = drm_edid_read_ddc(connector, ddc);
7300
7251
drm_edid_connector_update(connector, drm_edid);
7301
7252
if (!drm_edid) {
7302
7253
DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
···
7347
7286
static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
7348
7287
{
7349
7288
struct drm_connector *connector = &aconnector->base;
7289
+
struct dc_link *dc_link = aconnector->dc_link;
7350
7290
struct dc_sink_init_data init_params = {
7351
7291
.link = aconnector->dc_link,
7352
7292
.sink_signal = SIGNAL_TYPE_VIRTUAL
7353
7293
};
7354
7294
const struct drm_edid *drm_edid;
7355
7295
const struct edid *edid;
7296
+
struct i2c_adapter *ddc;
7356
7297
7357
-
drm_edid = drm_edid_read(connector);
7298
+
if (dc_link && dc_link->aux_mode)
7299
+
ddc = &aconnector->dm_dp_aux.aux.ddc;
7300
+
else
7301
+
ddc = &aconnector->i2c->base;
7302
+
7303
+
drm_edid = drm_edid_read_ddc(connector, ddc);
7358
7304
drm_edid_connector_update(connector, drm_edid);
7359
7305
if (!drm_edid) {
7360
7306
DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
+14
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+14
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
···
894
894
struct drm_device *dev = adev_to_drm(adev);
895
895
struct drm_connector *connector;
896
896
struct drm_connector_list_iter iter;
897
+
int i;
897
898
898
899
drm_connector_list_iter_begin(dev, &iter);
899
900
drm_for_each_connector_iter(connector, &iter) {
···
921
920
}
922
921
}
923
922
drm_connector_list_iter_end(&iter);
923
+
924
+
/* Update reference counts for HPDs */
925
+
for (i = DC_IRQ_SOURCE_HPD1; i <= adev->mode_info.num_hpd; i++) {
926
+
if (amdgpu_irq_get(adev, &adev->hpd_irq, i - DC_IRQ_SOURCE_HPD1))
927
+
drm_err(dev, "DM_IRQ: Failed get HPD for source=%d)!\n", i);
928
+
}
924
929
}
925
930
926
931
/**
···
942
935
struct drm_device *dev = adev_to_drm(adev);
943
936
struct drm_connector *connector;
944
937
struct drm_connector_list_iter iter;
938
+
int i;
945
939
946
940
drm_connector_list_iter_begin(dev, &iter);
947
941
drm_for_each_connector_iter(connector, &iter) {
···
968
960
}
969
961
}
970
962
drm_connector_list_iter_end(&iter);
963
+
964
+
/* Update reference counts for HPDs */
965
+
for (i = DC_IRQ_SOURCE_HPD1; i <= adev->mode_info.num_hpd; i++) {
966
+
if (amdgpu_irq_put(adev, &adev->hpd_irq, i - DC_IRQ_SOURCE_HPD1))
967
+
drm_err(dev, "DM_IRQ: Failed put HPD for source=%d!\n", i);
968
+
}
971
969
}
+2
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+2
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+19
-6
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
+19
-6
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
···
3042
3042
if (!amdgpu_dpm)
3043
3043
return 0;
3044
3044
3045
+
mutex_lock(&adev->pm.mutex);
3045
3046
kv_dpm_setup_asic(adev);
3046
3047
ret = kv_dpm_enable(adev);
3047
3048
if (ret)
···
3050
3049
else
3051
3050
adev->pm.dpm_enabled = true;
3052
3051
amdgpu_legacy_dpm_compute_clocks(adev);
3052
+
mutex_unlock(&adev->pm.mutex);
3053
+
3053
3054
return ret;
3054
3055
}
3055
3056
···
3069
3066
{
3070
3067
struct amdgpu_device *adev = ip_block->adev;
3071
3068
3069
+
cancel_work_sync(&adev->pm.dpm.thermal.work);
3070
+
3072
3071
if (adev->pm.dpm_enabled) {
3072
+
mutex_lock(&adev->pm.mutex);
3073
+
adev->pm.dpm_enabled = false;
3073
3074
/* disable dpm */
3074
3075
kv_dpm_disable(adev);
3075
3076
/* reset the power state */
3076
3077
adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
3078
+
mutex_unlock(&adev->pm.mutex);
3077
3079
}
3078
3080
return 0;
3079
3081
}
3080
3082
3081
3083
static int kv_dpm_resume(struct amdgpu_ip_block *ip_block)
3082
3084
{
3083
-
int ret;
3085
+
int ret = 0;
3084
3086
struct amdgpu_device *adev = ip_block->adev;
3085
3087
3086
-
if (adev->pm.dpm_enabled) {
3088
+
if (!amdgpu_dpm)
3089
+
return 0;
3090
+
3091
+
if (!adev->pm.dpm_enabled) {
3092
+
mutex_lock(&adev->pm.mutex);
3087
3093
/* asic init will reset to the boot state */
3088
3094
kv_dpm_setup_asic(adev);
3089
3095
ret = kv_dpm_enable(adev);
3090
-
if (ret)
3096
+
if (ret) {
3091
3097
adev->pm.dpm_enabled = false;
3092
-
else
3098
+
} else {
3093
3099
adev->pm.dpm_enabled = true;
3094
-
if (adev->pm.dpm_enabled)
3095
3100
amdgpu_legacy_dpm_compute_clocks(adev);
3101
+
}
3102
+
mutex_unlock(&adev->pm.mutex);
3096
3103
}
3097
-
return 0;
3104
+
return ret;
3098
3105
}
3099
3106
3100
3107
static bool kv_dpm_is_idle(void *handle)
+6
-2
drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
+6
-2
drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
···
1009
1009
enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
1010
1010
int temp, size = sizeof(temp);
1011
1011
1012
-
if (!adev->pm.dpm_enabled)
1013
-
return;
1012
+
mutex_lock(&adev->pm.mutex);
1014
1013
1014
+
if (!adev->pm.dpm_enabled) {
1015
+
mutex_unlock(&adev->pm.mutex);
1016
+
return;
1017
+
}
1015
1018
if (!pp_funcs->read_sensor(adev->powerplay.pp_handle,
1016
1019
AMDGPU_PP_SENSOR_GPU_TEMP,
1017
1020
(void *)&temp,
···
1036
1033
adev->pm.dpm.state = dpm_state;
1037
1034
1038
1035
amdgpu_legacy_dpm_compute_clocks(adev->powerplay.pp_handle);
1036
+
mutex_unlock(&adev->pm.mutex);
1039
1037
}
+20
-6
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+20
-6
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
···
7786
7786
if (!amdgpu_dpm)
7787
7787
return 0;
7788
7788
7789
+
mutex_lock(&adev->pm.mutex);
7789
7790
si_dpm_setup_asic(adev);
7790
7791
ret = si_dpm_enable(adev);
7791
7792
if (ret)
···
7794
7793
else
7795
7794
adev->pm.dpm_enabled = true;
7796
7795
amdgpu_legacy_dpm_compute_clocks(adev);
7796
+
mutex_unlock(&adev->pm.mutex);
7797
7797
return ret;
7798
7798
}
7799
7799
···
7812
7810
{
7813
7811
struct amdgpu_device *adev = ip_block->adev;
7814
7812
7813
+
cancel_work_sync(&adev->pm.dpm.thermal.work);
7814
+
7815
7815
if (adev->pm.dpm_enabled) {
7816
+
mutex_lock(&adev->pm.mutex);
7817
+
adev->pm.dpm_enabled = false;
7816
7818
/* disable dpm */
7817
7819
si_dpm_disable(adev);
7818
7820
/* reset the power state */
7819
7821
adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7822
+
mutex_unlock(&adev->pm.mutex);
7820
7823
}
7824
+
7821
7825
return 0;
7822
7826
}
7823
7827
7824
7828
static int si_dpm_resume(struct amdgpu_ip_block *ip_block)
7825
7829
{
7826
-
int ret;
7830
+
int ret = 0;
7827
7831
struct amdgpu_device *adev = ip_block->adev;
7828
7832
7829
-
if (adev->pm.dpm_enabled) {
7833
+
if (!amdgpu_dpm)
7834
+
return 0;
7835
+
7836
+
if (!adev->pm.dpm_enabled) {
7830
7837
/* asic init will reset to the boot state */
7838
+
mutex_lock(&adev->pm.mutex);
7831
7839
si_dpm_setup_asic(adev);
7832
7840
ret = si_dpm_enable(adev);
7833
-
if (ret)
7841
+
if (ret) {
7834
7842
adev->pm.dpm_enabled = false;
7835
-
else
7843
+
} else {
7836
7844
adev->pm.dpm_enabled = true;
7837
-
if (adev->pm.dpm_enabled)
7838
7845
amdgpu_legacy_dpm_compute_clocks(adev);
7846
+
}
7847
+
mutex_unlock(&adev->pm.mutex);
7839
7848
}
7840
-
return 0;
7849
+
7850
+
return ret;
7841
7851
}
7842
7852
7843
7853
static bool si_dpm_is_idle(void *handle)
+155
-62
drivers/gpu/drm/drm_fbdev_dma.c
+155
-62
drivers/gpu/drm/drm_fbdev_dma.c
···
1
1
// SPDX-License-Identifier: MIT
2
2
3
3
#include <linux/fb.h>
4
+
#include <linux/vmalloc.h>
4
5
5
6
#include <drm/drm_drv.h>
6
7
#include <drm/drm_fbdev_dma.h>
···
71
70
.fb_destroy = drm_fbdev_dma_fb_destroy,
72
71
};
73
72
74
-
FB_GEN_DEFAULT_DEFERRED_DMAMEM_OPS(drm_fbdev_dma,
73
+
FB_GEN_DEFAULT_DEFERRED_DMAMEM_OPS(drm_fbdev_dma_shadowed,
75
74
drm_fb_helper_damage_range,
76
75
drm_fb_helper_damage_area);
77
76
78
-
static int drm_fbdev_dma_deferred_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
77
+
static void drm_fbdev_dma_shadowed_fb_destroy(struct fb_info *info)
79
78
{
80
79
struct drm_fb_helper *fb_helper = info->par;
81
-
struct drm_framebuffer *fb = fb_helper->fb;
82
-
struct drm_gem_dma_object *dma = drm_fb_dma_get_gem_obj(fb, 0);
80
+
void *shadow = info->screen_buffer;
83
81
84
-
if (!dma->map_noncoherent)
85
-
vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
82
+
if (!fb_helper->dev)
83
+
return;
86
84
87
-
return fb_deferred_io_mmap(info, vma);
85
+
if (info->fbdefio)
86
+
fb_deferred_io_cleanup(info);
87
+
drm_fb_helper_fini(fb_helper);
88
+
vfree(shadow);
89
+
90
+
drm_client_buffer_vunmap(fb_helper->buffer);
91
+
drm_client_framebuffer_delete(fb_helper->buffer);
92
+
drm_client_release(&fb_helper->client);
93
+
drm_fb_helper_unprepare(fb_helper);
94
+
kfree(fb_helper);
88
95
}
89
96
90
-
static const struct fb_ops drm_fbdev_dma_deferred_fb_ops = {
97
+
static const struct fb_ops drm_fbdev_dma_shadowed_fb_ops = {
91
98
.owner = THIS_MODULE,
92
99
.fb_open = drm_fbdev_dma_fb_open,
93
100
.fb_release = drm_fbdev_dma_fb_release,
94
-
__FB_DEFAULT_DEFERRED_OPS_RDWR(drm_fbdev_dma),
101
+
FB_DEFAULT_DEFERRED_OPS(drm_fbdev_dma_shadowed),
95
102
DRM_FB_HELPER_DEFAULT_OPS,
96
-
__FB_DEFAULT_DEFERRED_OPS_DRAW(drm_fbdev_dma),
97
-
.fb_mmap = drm_fbdev_dma_deferred_fb_mmap,
98
-
.fb_destroy = drm_fbdev_dma_fb_destroy,
103
+
.fb_destroy = drm_fbdev_dma_shadowed_fb_destroy,
99
104
};
100
105
101
106
/*
102
107
* struct drm_fb_helper
103
108
*/
104
109
110
+
static void drm_fbdev_dma_damage_blit_real(struct drm_fb_helper *fb_helper,
111
+
struct drm_clip_rect *clip,
112
+
struct iosys_map *dst)
113
+
{
114
+
struct drm_framebuffer *fb = fb_helper->fb;
115
+
size_t offset = clip->y1 * fb->pitches[0];
116
+
size_t len = clip->x2 - clip->x1;
117
+
unsigned int y;
118
+
void *src;
119
+
120
+
switch (drm_format_info_bpp(fb->format, 0)) {
121
+
case 1:
122
+
offset += clip->x1 / 8;
123
+
len = DIV_ROUND_UP(len + clip->x1 % 8, 8);
124
+
break;
125
+
case 2:
126
+
offset += clip->x1 / 4;
127
+
len = DIV_ROUND_UP(len + clip->x1 % 4, 4);
128
+
break;
129
+
case 4:
130
+
offset += clip->x1 / 2;
131
+
len = DIV_ROUND_UP(len + clip->x1 % 2, 2);
132
+
break;
133
+
default:
134
+
offset += clip->x1 * fb->format->cpp[0];
135
+
len *= fb->format->cpp[0];
136
+
break;
137
+
}
138
+
139
+
src = fb_helper->info->screen_buffer + offset;
140
+
iosys_map_incr(dst, offset); /* go to first pixel within clip rect */
141
+
142
+
for (y = clip->y1; y < clip->y2; y++) {
143
+
iosys_map_memcpy_to(dst, 0, src, len);
144
+
iosys_map_incr(dst, fb->pitches[0]);
145
+
src += fb->pitches[0];
146
+
}
147
+
}
148
+
149
+
static int drm_fbdev_dma_damage_blit(struct drm_fb_helper *fb_helper,
150
+
struct drm_clip_rect *clip)
151
+
{
152
+
struct drm_client_buffer *buffer = fb_helper->buffer;
153
+
struct iosys_map dst;
154
+
155
+
/*
156
+
* For fbdev emulation, we only have to protect against fbdev modeset
157
+
* operations. Nothing else will involve the client buffer's BO. So it
158
+
* is sufficient to acquire struct drm_fb_helper.lock here.
159
+
*/
160
+
mutex_lock(&fb_helper->lock);
161
+
162
+
dst = buffer->map;
163
+
drm_fbdev_dma_damage_blit_real(fb_helper, clip, &dst);
164
+
165
+
mutex_unlock(&fb_helper->lock);
166
+
167
+
return 0;
168
+
}
105
169
static int drm_fbdev_dma_helper_fb_dirty(struct drm_fb_helper *helper,
106
170
struct drm_clip_rect *clip)
107
171
{
···
178
112
return 0;
179
113
180
114
if (helper->fb->funcs->dirty) {
115
+
ret = drm_fbdev_dma_damage_blit(helper, clip);
116
+
if (drm_WARN_ONCE(dev, ret, "Damage blitter failed: ret=%d\n", ret))
117
+
return ret;
118
+
181
119
ret = helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, clip, 1);
182
120
if (drm_WARN_ONCE(dev, ret, "Dirty helper failed: ret=%d\n", ret))
183
121
return ret;
···
198
128
* struct drm_fb_helper
199
129
*/
200
130
131
+
static int drm_fbdev_dma_driver_fbdev_probe_tail(struct drm_fb_helper *fb_helper,
132
+
struct drm_fb_helper_surface_size *sizes)
133
+
{
134
+
struct drm_device *dev = fb_helper->dev;
135
+
struct drm_client_buffer *buffer = fb_helper->buffer;
136
+
struct drm_gem_dma_object *dma_obj = to_drm_gem_dma_obj(buffer->gem);
137
+
struct drm_framebuffer *fb = fb_helper->fb;
138
+
struct fb_info *info = fb_helper->info;
139
+
struct iosys_map map = buffer->map;
140
+
141
+
info->fbops = &drm_fbdev_dma_fb_ops;
142
+
143
+
/* screen */
144
+
info->flags |= FBINFO_VIRTFB; /* system memory */
145
+
if (dma_obj->map_noncoherent)
146
+
info->flags |= FBINFO_READS_FAST; /* signal caching */
147
+
info->screen_size = sizes->surface_height * fb->pitches[0];
148
+
info->screen_buffer = map.vaddr;
149
+
if (!(info->flags & FBINFO_HIDE_SMEM_START)) {
150
+
if (!drm_WARN_ON(dev, is_vmalloc_addr(info->screen_buffer)))
151
+
info->fix.smem_start = page_to_phys(virt_to_page(info->screen_buffer));
152
+
}
153
+
info->fix.smem_len = info->screen_size;
154
+
155
+
return 0;
156
+
}
157
+
158
+
static int drm_fbdev_dma_driver_fbdev_probe_tail_shadowed(struct drm_fb_helper *fb_helper,
159
+
struct drm_fb_helper_surface_size *sizes)
160
+
{
161
+
struct drm_client_buffer *buffer = fb_helper->buffer;
162
+
struct fb_info *info = fb_helper->info;
163
+
size_t screen_size = buffer->gem->size;
164
+
void *screen_buffer;
165
+
int ret;
166
+
167
+
/*
168
+
* Deferred I/O requires struct page for framebuffer memory,
169
+
* which is not guaranteed for all DMA ranges. We thus create
170
+
* a shadow buffer in system memory.
171
+
*/
172
+
screen_buffer = vzalloc(screen_size);
173
+
if (!screen_buffer)
174
+
return -ENOMEM;
175
+
176
+
info->fbops = &drm_fbdev_dma_shadowed_fb_ops;
177
+
178
+
/* screen */
179
+
info->flags |= FBINFO_VIRTFB; /* system memory */
180
+
info->flags |= FBINFO_READS_FAST; /* signal caching */
181
+
info->screen_buffer = screen_buffer;
182
+
info->fix.smem_len = screen_size;
183
+
184
+
fb_helper->fbdefio.delay = HZ / 20;
185
+
fb_helper->fbdefio.deferred_io = drm_fb_helper_deferred_io;
186
+
187
+
info->fbdefio = &fb_helper->fbdefio;
188
+
ret = fb_deferred_io_init(info);
189
+
if (ret)
190
+
goto err_vfree;
191
+
192
+
return 0;
193
+
194
+
err_vfree:
195
+
vfree(screen_buffer);
196
+
return ret;
197
+
}
198
+
201
199
int drm_fbdev_dma_driver_fbdev_probe(struct drm_fb_helper *fb_helper,
202
200
struct drm_fb_helper_surface_size *sizes)
203
201
{
204
202
struct drm_client_dev *client = &fb_helper->client;
205
203
struct drm_device *dev = fb_helper->dev;
206
-
bool use_deferred_io = false;
207
204
struct drm_client_buffer *buffer;
208
-
struct drm_gem_dma_object *dma_obj;
209
205
struct drm_framebuffer *fb;
210
206
struct fb_info *info;
211
207
u32 format;
···
288
152
sizes->surface_height, format);
289
153
if (IS_ERR(buffer))
290
154
return PTR_ERR(buffer);
291
-
dma_obj = to_drm_gem_dma_obj(buffer->gem);
292
155
293
156
fb = buffer->fb;
294
-
295
-
/*
296
-
* Deferred I/O requires struct page for framebuffer memory,
297
-
* which is not guaranteed for all DMA ranges. We thus only
298
-
* install deferred I/O if we have a framebuffer that requires
299
-
* it.
300
-
*/
301
-
if (fb->funcs->dirty)
302
-
use_deferred_io = true;
303
157
304
158
ret = drm_client_buffer_vmap(buffer, &map);
305
159
if (ret) {
···
311
185
312
186
drm_fb_helper_fill_info(info, fb_helper, sizes);
313
187
314
-
if (use_deferred_io)
315
-
info->fbops = &drm_fbdev_dma_deferred_fb_ops;
188
+
if (fb->funcs->dirty)
189
+
ret = drm_fbdev_dma_driver_fbdev_probe_tail_shadowed(fb_helper, sizes);
316
190
else
317
-
info->fbops = &drm_fbdev_dma_fb_ops;
318
-
319
-
/* screen */
320
-
info->flags |= FBINFO_VIRTFB; /* system memory */
321
-
if (dma_obj->map_noncoherent)
322
-
info->flags |= FBINFO_READS_FAST; /* signal caching */
323
-
info->screen_size = sizes->surface_height * fb->pitches[0];
324
-
info->screen_buffer = map.vaddr;
325
-
if (!(info->flags & FBINFO_HIDE_SMEM_START)) {
326
-
if (!drm_WARN_ON(dev, is_vmalloc_addr(info->screen_buffer)))
327
-
info->fix.smem_start = page_to_phys(virt_to_page(info->screen_buffer));
328
-
}
329
-
info->fix.smem_len = info->screen_size;
330
-
331
-
/*
332
-
* Only set up deferred I/O if the screen buffer supports
333
-
* it. If this disagrees with the previous test for ->dirty,
334
-
* mmap on the /dev/fb file might not work correctly.
335
-
*/
336
-
if (!is_vmalloc_addr(info->screen_buffer) && info->fix.smem_start) {
337
-
unsigned long pfn = info->fix.smem_start >> PAGE_SHIFT;
338
-
339
-
if (drm_WARN_ON(dev, !pfn_to_page(pfn)))
340
-
use_deferred_io = false;
341
-
}
342
-
343
-
/* deferred I/O */
344
-
if (use_deferred_io) {
345
-
fb_helper->fbdefio.delay = HZ / 20;
346
-
fb_helper->fbdefio.deferred_io = drm_fb_helper_deferred_io;
347
-
348
-
info->fbdefio = &fb_helper->fbdefio;
349
-
ret = fb_deferred_io_init(info);
350
-
if (ret)
351
-
goto err_drm_fb_helper_release_info;
352
-
}
191
+
ret = drm_fbdev_dma_driver_fbdev_probe_tail(fb_helper, sizes);
192
+
if (ret)
193
+
goto err_drm_fb_helper_release_info;
353
194
354
195
return 0;
355
196
+5
-4
drivers/gpu/drm/i915/display/intel_ddi.c
+5
-4
drivers/gpu/drm/i915/display/intel_ddi.c
···
866
866
encoder->base.base.id, encoder->base.name);
867
867
868
868
if (!mst_pipe_mask && dp128b132b_pipe_mask) {
869
-
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
869
+
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
870
870
871
871
/*
872
872
* If we don't have 8b/10b MST, but have more than one
···
878
878
* we don't expect MST to have been enabled at that point, and
879
879
* can assume it's SST.
880
880
*/
881
-
if (hweight8(dp128b132b_pipe_mask) > 1 || intel_dp->is_mst)
881
+
if (hweight8(dp128b132b_pipe_mask) > 1 ||
882
+
intel_dp_mst_encoder_active_links(dig_port))
882
883
mst_pipe_mask = dp128b132b_pipe_mask;
883
884
}
884
885
···
4152
4151
} else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) {
4153
4152
intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl);
4154
4153
} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) {
4155
-
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4154
+
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4156
4155
4157
4156
/*
4158
4157
* If this is true, we know we're being called from mst stream
4159
4158
* encoder's ->get_config().
4160
4159
*/
4161
-
if (intel_dp->is_mst)
4160
+
if (intel_dp_mst_encoder_active_links(dig_port))
4162
4161
intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl);
4163
4162
else
4164
4163
intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl);
-2
drivers/gpu/drm/imagination/Makefile
-2
drivers/gpu/drm/imagination/Makefile
-1
drivers/gpu/drm/nouveau/nouveau_connector.c
-1
drivers/gpu/drm/nouveau/nouveau_connector.c
+1
-1
drivers/gpu/drm/vkms/vkms_composer.c
+1
-1
drivers/gpu/drm/vkms/vkms_composer.c
-1
drivers/gpu/drm/xe/regs/xe_engine_regs.h
-1
drivers/gpu/drm/xe/regs/xe_engine_regs.h
+2
drivers/gpu/drm/xe/xe_guc_submit.c
+2
drivers/gpu/drm/xe/xe_guc_submit.c
···
1248
1248
1249
1249
if (xe_exec_queue_is_lr(q))
1250
1250
cancel_work_sync(&ge->lr_tdr);
1251
+
/* Confirm no work left behind accessing device structures */
1252
+
cancel_delayed_work_sync(&ge->sched.base.work_tdr);
1251
1253
release_guc_id(guc, q);
1252
1254
xe_sched_entity_fini(&ge->entity);
1253
1255
xe_sched_fini(&ge->sched);
+3
-2
drivers/gpu/drm/xe/xe_oa.c
+3
-2
drivers/gpu/drm/xe/xe_oa.c
···
1689
1689
stream->oa_buffer.format = &stream->oa->oa_formats[param->oa_format];
1690
1690
1691
1691
stream->sample = param->sample;
1692
-
stream->periodic = param->period_exponent > 0;
1692
+
stream->periodic = param->period_exponent >= 0;
1693
1693
stream->period_exponent = param->period_exponent;
1694
1694
stream->no_preempt = param->no_preempt;
1695
1695
stream->wait_num_reports = param->wait_num_reports;
···
1970
1970
}
1971
1971
1972
1972
param.xef = xef;
1973
+
param.period_exponent = -1;
1973
1974
ret = xe_oa_user_extensions(oa, XE_OA_USER_EXTN_FROM_OPEN, data, 0, ¶m);
1974
1975
if (ret)
1975
1976
return ret;
···
2025
2024
goto err_exec_q;
2026
2025
}
2027
2026
2028
-
if (param.period_exponent > 0) {
2027
+
if (param.period_exponent >= 0) {
2029
2028
u64 oa_period, oa_freq_hz;
2030
2029
2031
2030
/* Requesting samples from OAG buffer is a privileged operation */
+33
-7
drivers/gpu/drm/xe/xe_vm.c
+33
-7
drivers/gpu/drm/xe/xe_vm.c
···
666
666
667
667
/* Collect invalidated userptrs */
668
668
spin_lock(&vm->userptr.invalidated_lock);
669
+
xe_assert(vm->xe, list_empty(&vm->userptr.repin_list));
669
670
list_for_each_entry_safe(uvma, next, &vm->userptr.invalidated,
670
671
userptr.invalidate_link) {
671
672
list_del_init(&uvma->userptr.invalidate_link);
672
-
list_move_tail(&uvma->userptr.repin_link,
673
-
&vm->userptr.repin_list);
673
+
list_add_tail(&uvma->userptr.repin_link,
674
+
&vm->userptr.repin_list);
674
675
}
675
676
spin_unlock(&vm->userptr.invalidated_lock);
676
677
677
-
/* Pin and move to temporary list */
678
+
/* Pin and move to bind list */
678
679
list_for_each_entry_safe(uvma, next, &vm->userptr.repin_list,
679
680
userptr.repin_link) {
680
681
err = xe_vma_userptr_pin_pages(uvma);
681
682
if (err == -EFAULT) {
682
683
list_del_init(&uvma->userptr.repin_link);
684
+
/*
685
+
* We might have already done the pin once already, but
686
+
* then had to retry before the re-bind happened, due
687
+
* some other condition in the caller, but in the
688
+
* meantime the userptr got dinged by the notifier such
689
+
* that we need to revalidate here, but this time we hit
690
+
* the EFAULT. In such a case make sure we remove
691
+
* ourselves from the rebind list to avoid going down in
692
+
* flames.
693
+
*/
694
+
if (!list_empty(&uvma->vma.combined_links.rebind))
695
+
list_del_init(&uvma->vma.combined_links.rebind);
683
696
684
697
/* Wait for pending binds */
685
698
xe_vm_lock(vm, false);
···
703
690
err = xe_vm_invalidate_vma(&uvma->vma);
704
691
xe_vm_unlock(vm);
705
692
if (err)
706
-
return err;
693
+
break;
707
694
} else {
708
-
if (err < 0)
709
-
return err;
695
+
if (err)
696
+
break;
710
697
711
698
list_del_init(&uvma->userptr.repin_link);
712
699
list_move_tail(&uvma->vma.combined_links.rebind,
···
714
701
}
715
702
}
716
703
717
-
return 0;
704
+
if (err) {
705
+
down_write(&vm->userptr.notifier_lock);
706
+
spin_lock(&vm->userptr.invalidated_lock);
707
+
list_for_each_entry_safe(uvma, next, &vm->userptr.repin_list,
708
+
userptr.repin_link) {
709
+
list_del_init(&uvma->userptr.repin_link);
710
+
list_move_tail(&uvma->userptr.invalidate_link,
711
+
&vm->userptr.invalidated);
712
+
}
713
+
spin_unlock(&vm->userptr.invalidated_lock);
714
+
up_write(&vm->userptr.notifier_lock);
715
+
}
716
+
return err;
718
717
}
719
718
720
719
/**
···
1091
1066
xe_assert(vm->xe, vma->gpuva.flags & XE_VMA_DESTROYED);
1092
1067
1093
1068
spin_lock(&vm->userptr.invalidated_lock);
1069
+
xe_assert(vm->xe, list_empty(&to_userptr_vma(vma)->userptr.repin_link));
1094
1070
list_del(&to_userptr_vma(vma)->userptr.invalidate_link);
1095
1071
spin_unlock(&vm->userptr.invalidated_lock);
1096
1072
} else if (!xe_vma_is_null(vma)) {