Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'i2c/for-5.0' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c updates from Wolfram Sang:
"I2C has only driver updates for you this time.
Mostly new IDs/DT compatibles, also SPDX conversions, small cleanups.
STM32F7 got FastMode+ and PM support, Axxia some reliabilty
improvements"
* 'i2c/for-5.0' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (26 commits)
i2c: Add Actions Semiconductor Owl family S700 I2C support
dt-bindings: i2c: Add S700 support for Actions Semi Soc's
i2c: ismt: Add support for Intel Cedar Fork
i2c: tegra: Switch to SPDX identifier
i2c: tegra: Add missing kerneldoc for some fields
i2c: tegra: Cleanup kerneldoc comments
i2c: axxia: support sequence command mode
dt-bindings: i2c: rcar: Add r8a774c0 support
dt-bindings: i2c: sh_mobile: Add r8a774c0 support
i2c: sh_mobile: Add support for r8a774c0 (RZ/G2E)
i2c: i2c-cros-ec-tunnel: Switch to SPDX identifier.
i2c: powermac: Use of_node_name_eq for node name comparisons
i2c-axxia: check for error conditions first
i2c-axxia: dedicated function to set client addr
dt-bindings: i2c: Use correct vendor prefix for Atmel
i2c: tegra: replace spin_lock_irqsave with spin_lock in ISR
eeprom: at24: add support for 24c2048
dt-bindings: eeprom: at24: add "atmel,24c2048" compatible string
i2c: i2c-stm32f7: add PM Runtime support
i2c: sh_mobile: add support for r8a77990 (R-Car E3)
...
+346
-137
+1
Documentation/devicetree/bindings/eeprom/at24.txt
+1
Documentation/devicetree/bindings/eeprom/at24.txt
+1
-1
Documentation/devicetree/bindings/i2c/i2c-at91.txt
+1
-1
Documentation/devicetree/bindings/i2c/i2c-at91.txt
+2
-2
Documentation/devicetree/bindings/i2c/i2c-mux-ltc4306.txt
+2
-2
Documentation/devicetree/bindings/i2c/i2c-mux-ltc4306.txt
+1
-1
Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt
+1
-1
Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt
+3
-1
Documentation/devicetree/bindings/i2c/i2c-owl.txt
+3
-1
Documentation/devicetree/bindings/i2c/i2c-owl.txt
···
2
2
3
3
Required properties:
4
4
5
-
- compatible : Should be "actions,s900-i2c".
5
+
- compatible : Should be one of the following:
6
+
- "actions,s700-i2c" for S700 SoC
7
+
- "actions,s900-i2c" for S900 SoC
6
8
- reg : Offset and length of the register set for the device.
7
9
- #address-cells : Should be 1.
8
10
- #size-cells : Should be 0.
+1
Documentation/devicetree/bindings/i2c/i2c-rcar.txt
+1
Documentation/devicetree/bindings/i2c/i2c-rcar.txt
···
7
7
"renesas,i2c-r8a7745" if the device is a part of a R8A7745 SoC.
8
8
"renesas,i2c-r8a77470" if the device is a part of a R8A77470 SoC.
9
9
"renesas,i2c-r8a774a1" if the device is a part of a R8A774A1 SoC.
10
+
"renesas,i2c-r8a774c0" if the device is a part of a R8A774C0 SoC.
10
11
"renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC.
11
12
"renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC.
12
13
"renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC.
+9
-1
Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
+9
-1
Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
···
8
8
- "renesas,iic-r8a7744" (RZ/G1N)
9
9
- "renesas,iic-r8a7745" (RZ/G1E)
10
10
- "renesas,iic-r8a774a1" (RZ/G2M)
11
+
- "renesas,iic-r8a774c0" (RZ/G2E)
11
12
- "renesas,iic-r8a7790" (R-Car H2)
12
13
- "renesas,iic-r8a7791" (R-Car M2-W)
13
14
- "renesas,iic-r8a7792" (R-Car V2H)
···
17
16
- "renesas,iic-r8a7795" (R-Car H3)
18
17
- "renesas,iic-r8a7796" (R-Car M3-W)
19
18
- "renesas,iic-r8a77965" (R-Car M3-N)
19
+
- "renesas,iic-r8a77990" (R-Car E3)
20
20
- "renesas,iic-sh73a0" (SH-Mobile AG5)
21
21
- "renesas,rcar-gen2-iic" (generic R-Car Gen2 or RZ/G1
22
22
compatible device)
···
30
28
the platform first followed by the generic R-Car
31
29
version.
32
30
33
-
renesas,rmobile-iic must always follow.
31
+
When compatible with "renesas,rmobile-iic" it should
32
+
be the last compatibility string listed.
33
+
34
+
The r8a77990 (R-Car E3) and r8a774c0 (RZ/G2E)
35
+
controllers are not considered compatible with
36
+
"renesas,rcar-gen3-iic" or "renesas,rmobile-iic"
37
+
due to the absence of automatic transmission registers.
34
38
35
39
- reg : address start and address range size of device
36
40
- interrupts : interrupt of device
+6
Documentation/devicetree/bindings/i2c/i2c-stm32.txt
+6
Documentation/devicetree/bindings/i2c/i2c-stm32.txt
···
26
26
- i2c-scl-falling-time-ns : Only for STM32F7, I2C SCL Falling time for the board
27
27
(default: 10)
28
28
I2C Timings are derived from these 2 values
29
+
- st,syscfg-fmp: Only for STM32F7, use to set Fast Mode Plus bit within SYSCFG
30
+
whether Fast Mode Plus speed is selected by slave.
31
+
1st cell : phandle to syscfg
32
+
2nd cell : register offset within SYSCFG
33
+
3rd cell : register bitmask for FMP bit
29
34
30
35
Example :
31
36
···
58
53
clocks = <&rcc 1 CLK_I2C1>;
59
54
pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
60
55
pinctrl-names = "default";
56
+
st,syscfg-fmp = <&syscfg 0x4 0x1>;
61
57
};
+1
-1
Documentation/devicetree/bindings/i2c/nxp,pca9541.txt
+1
-1
Documentation/devicetree/bindings/i2c/nxp,pca9541.txt
+135
-33
drivers/i2c/busses/i2c-axxia.c
+135
-33
drivers/i2c/busses/i2c-axxia.c
···
12
12
*/
13
13
#include <linux/clk.h>
14
14
#include <linux/clkdev.h>
15
+
#include <linux/delay.h>
15
16
#include <linux/err.h>
16
17
#include <linux/i2c.h>
17
18
#include <linux/init.h>
···
26
25
#define I2C_XFER_TIMEOUT (msecs_to_jiffies(250))
27
26
#define I2C_STOP_TIMEOUT (msecs_to_jiffies(100))
28
27
#define FIFO_SIZE 8
28
+
#define SEQ_LEN 2
29
29
30
30
#define GLOBAL_CONTROL 0x00
31
31
#define GLOBAL_MST_EN BIT(0)
···
53
51
#define CMD_BUSY (1<<3)
54
52
#define CMD_MANUAL (0x00 | CMD_BUSY)
55
53
#define CMD_AUTO (0x01 | CMD_BUSY)
54
+
#define CMD_SEQUENCE (0x02 | CMD_BUSY)
56
55
#define MST_RX_XFER 0x2c
57
56
#define MST_TX_XFER 0x30
58
57
#define MST_ADDR_1 0x34
···
90
87
* axxia_i2c_dev - I2C device context
91
88
* @base: pointer to register struct
92
89
* @msg: pointer to current message
93
-
* @msg_xfrd: number of bytes transferred in msg
90
+
* @msg_r: pointer to current read message (sequence transfer)
91
+
* @msg_xfrd: number of bytes transferred in tx_fifo
92
+
* @msg_xfrd_r: number of bytes transferred in rx_fifo
94
93
* @msg_err: error code for completed message
95
94
* @msg_complete: xfer completion object
96
95
* @dev: device reference
···
103
98
struct axxia_i2c_dev {
104
99
void __iomem *base;
105
100
struct i2c_msg *msg;
101
+
struct i2c_msg *msg_r;
106
102
size_t msg_xfrd;
103
+
size_t msg_xfrd_r;
107
104
int msg_err;
108
105
struct completion msg_complete;
109
106
struct device *dev;
···
234
227
*/
235
228
static int axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev *idev)
236
229
{
237
-
struct i2c_msg *msg = idev->msg;
230
+
struct i2c_msg *msg = idev->msg_r;
238
231
size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO);
239
-
int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd);
232
+
int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd_r);
240
233
241
234
while (bytes_to_transfer-- > 0) {
242
235
int c = readl(idev->base + MST_DATA);
243
236
244
-
if (idev->msg_xfrd == 0 && i2c_m_recv_len(msg)) {
237
+
if (idev->msg_xfrd_r == 0 && i2c_m_recv_len(msg)) {
245
238
/*
246
239
* Check length byte for SMBus block read
247
240
*/
···
254
247
msg->len = 1 + c;
255
248
writel(msg->len, idev->base + MST_RX_XFER);
256
249
}
257
-
msg->buf[idev->msg_xfrd++] = c;
250
+
msg->buf[idev->msg_xfrd_r++] = c;
258
251
}
259
252
260
253
return 0;
···
294
287
}
295
288
296
289
/* RX FIFO needs service? */
297
-
if (i2c_m_rd(idev->msg) && (status & MST_STATUS_RFL))
290
+
if (i2c_m_rd(idev->msg_r) && (status & MST_STATUS_RFL))
298
291
axxia_i2c_empty_rx_fifo(idev);
299
292
300
293
/* TX FIFO needs service? */
···
303
296
i2c_int_disable(idev, MST_STATUS_TFL);
304
297
}
305
298
306
-
if (status & MST_STATUS_SCC) {
307
-
/* Stop completed */
308
-
i2c_int_disable(idev, ~MST_STATUS_TSS);
309
-
complete(&idev->msg_complete);
310
-
} else if (status & MST_STATUS_SNS) {
311
-
/* Transfer done */
312
-
i2c_int_disable(idev, ~MST_STATUS_TSS);
313
-
if (i2c_m_rd(idev->msg) && idev->msg_xfrd < idev->msg->len)
314
-
axxia_i2c_empty_rx_fifo(idev);
315
-
complete(&idev->msg_complete);
316
-
} else if (status & MST_STATUS_TSS) {
317
-
/* Transfer timeout */
318
-
idev->msg_err = -ETIMEDOUT;
319
-
i2c_int_disable(idev, ~MST_STATUS_TSS);
320
-
complete(&idev->msg_complete);
321
-
} else if (unlikely(status & MST_STATUS_ERR)) {
299
+
if (unlikely(status & MST_STATUS_ERR)) {
322
300
/* Transfer error */
323
301
i2c_int_disable(idev, ~0);
324
302
if (status & MST_STATUS_AL)
···
320
328
readl(idev->base + MST_TX_BYTES_XFRD),
321
329
readl(idev->base + MST_TX_XFER));
322
330
complete(&idev->msg_complete);
331
+
} else if (status & MST_STATUS_SCC) {
332
+
/* Stop completed */
333
+
i2c_int_disable(idev, ~MST_STATUS_TSS);
334
+
complete(&idev->msg_complete);
335
+
} else if (status & MST_STATUS_SNS) {
336
+
/* Transfer done */
337
+
i2c_int_disable(idev, ~MST_STATUS_TSS);
338
+
if (i2c_m_rd(idev->msg_r) && idev->msg_xfrd_r < idev->msg_r->len)
339
+
axxia_i2c_empty_rx_fifo(idev);
340
+
complete(&idev->msg_complete);
341
+
} else if (status & MST_STATUS_SS) {
342
+
/* Auto/Sequence transfer done */
343
+
complete(&idev->msg_complete);
344
+
} else if (status & MST_STATUS_TSS) {
345
+
/* Transfer timeout */
346
+
idev->msg_err = -ETIMEDOUT;
347
+
i2c_int_disable(idev, ~MST_STATUS_TSS);
348
+
complete(&idev->msg_complete);
323
349
}
324
350
325
351
out:
···
347
337
return IRQ_HANDLED;
348
338
}
349
339
350
-
static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
340
+
static void axxia_i2c_set_addr(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
351
341
{
352
-
u32 int_mask = MST_STATUS_ERR | MST_STATUS_SNS;
353
-
u32 rx_xfer, tx_xfer;
354
342
u32 addr_1, addr_2;
355
-
unsigned long time_left;
356
-
unsigned int wt_value;
357
-
358
-
idev->msg = msg;
359
-
idev->msg_xfrd = 0;
360
-
reinit_completion(&idev->msg_complete);
361
343
362
344
if (i2c_m_ten(msg)) {
363
345
/* 10-bit address
···
369
367
addr_2 = 0;
370
368
}
371
369
370
+
writel(addr_1, idev->base + MST_ADDR_1);
371
+
writel(addr_2, idev->base + MST_ADDR_2);
372
+
}
373
+
374
+
/* The NAK interrupt will be sent _before_ issuing STOP command
375
+
* so the controller might still be busy processing it. No
376
+
* interrupt will be sent at the end so we have to poll for it
377
+
*/
378
+
static int axxia_i2c_handle_seq_nak(struct axxia_i2c_dev *idev)
379
+
{
380
+
unsigned long timeout = jiffies + I2C_XFER_TIMEOUT;
381
+
382
+
do {
383
+
if ((readl(idev->base + MST_COMMAND) & CMD_BUSY) == 0)
384
+
return 0;
385
+
usleep_range(1, 100);
386
+
} while (time_before(jiffies, timeout));
387
+
388
+
return -ETIMEDOUT;
389
+
}
390
+
391
+
static int axxia_i2c_xfer_seq(struct axxia_i2c_dev *idev, struct i2c_msg msgs[])
392
+
{
393
+
u32 int_mask = MST_STATUS_ERR | MST_STATUS_SS | MST_STATUS_RFL;
394
+
u32 rlen = i2c_m_recv_len(&msgs[1]) ? I2C_SMBUS_BLOCK_MAX : msgs[1].len;
395
+
unsigned long time_left;
396
+
397
+
axxia_i2c_set_addr(idev, &msgs[0]);
398
+
399
+
writel(msgs[0].len, idev->base + MST_TX_XFER);
400
+
writel(rlen, idev->base + MST_RX_XFER);
401
+
402
+
idev->msg = &msgs[0];
403
+
idev->msg_r = &msgs[1];
404
+
idev->msg_xfrd = 0;
405
+
idev->msg_xfrd_r = 0;
406
+
axxia_i2c_fill_tx_fifo(idev);
407
+
408
+
writel(CMD_SEQUENCE, idev->base + MST_COMMAND);
409
+
410
+
reinit_completion(&idev->msg_complete);
411
+
i2c_int_enable(idev, int_mask);
412
+
413
+
time_left = wait_for_completion_timeout(&idev->msg_complete,
414
+
I2C_XFER_TIMEOUT);
415
+
416
+
i2c_int_disable(idev, int_mask);
417
+
418
+
axxia_i2c_empty_rx_fifo(idev);
419
+
420
+
if (idev->msg_err == -ENXIO) {
421
+
if (axxia_i2c_handle_seq_nak(idev))
422
+
axxia_i2c_init(idev);
423
+
} else if (readl(idev->base + MST_COMMAND) & CMD_BUSY) {
424
+
dev_warn(idev->dev, "busy after xfer\n");
425
+
}
426
+
427
+
if (time_left == 0) {
428
+
idev->msg_err = -ETIMEDOUT;
429
+
i2c_recover_bus(&idev->adapter);
430
+
axxia_i2c_init(idev);
431
+
}
432
+
433
+
if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO)
434
+
axxia_i2c_init(idev);
435
+
436
+
return idev->msg_err;
437
+
}
438
+
439
+
static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
440
+
{
441
+
u32 int_mask = MST_STATUS_ERR | MST_STATUS_SNS;
442
+
u32 rx_xfer, tx_xfer;
443
+
unsigned long time_left;
444
+
unsigned int wt_value;
445
+
446
+
idev->msg = msg;
447
+
idev->msg_r = msg;
448
+
idev->msg_xfrd = 0;
449
+
idev->msg_xfrd_r = 0;
450
+
reinit_completion(&idev->msg_complete);
451
+
452
+
axxia_i2c_set_addr(idev, msg);
453
+
372
454
if (i2c_m_rd(msg)) {
373
455
/* I2C read transfer */
374
456
rx_xfer = i2c_m_recv_len(msg) ? I2C_SMBUS_BLOCK_MAX : msg->len;
···
465
379
466
380
writel(rx_xfer, idev->base + MST_RX_XFER);
467
381
writel(tx_xfer, idev->base + MST_TX_XFER);
468
-
writel(addr_1, idev->base + MST_ADDR_1);
469
-
writel(addr_2, idev->base + MST_ADDR_2);
470
382
471
383
if (i2c_m_rd(msg))
472
384
int_mask |= MST_STATUS_RFL;
···
529
445
return 0;
530
446
}
531
447
448
+
/* This function checks if the msgs[] array contains messages compatible with
449
+
* Sequence mode of operation. This mode assumes there will be exactly one
450
+
* write of non-zero length followed by exactly one read of non-zero length,
451
+
* both targeted at the same client device.
452
+
*/
453
+
static bool axxia_i2c_sequence_ok(struct i2c_msg msgs[], int num)
454
+
{
455
+
return num == SEQ_LEN && !i2c_m_rd(&msgs[0]) && i2c_m_rd(&msgs[1]) &&
456
+
msgs[0].len > 0 && msgs[0].len <= FIFO_SIZE &&
457
+
msgs[1].len > 0 && msgs[0].addr == msgs[1].addr;
458
+
}
459
+
532
460
static int
533
461
axxia_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
534
462
{
···
549
453
int ret = 0;
550
454
551
455
idev->msg_err = 0;
456
+
457
+
if (axxia_i2c_sequence_ok(msgs, num)) {
458
+
ret = axxia_i2c_xfer_seq(idev, msgs);
459
+
return ret ? : SEQ_LEN;
460
+
}
461
+
552
462
i2c_int_enable(idev, MST_STATUS_TSS);
553
463
554
464
for (i = 0; ret == 0 && i < num; ++i)
+1
-9
drivers/i2c/busses/i2c-bcm2835.c
+1
-9
drivers/i2c/busses/i2c-bcm2835.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
1
2
/*
2
3
* BCM2835 master mode driver
3
-
*
4
-
* This software is licensed under the terms of the GNU General Public
5
-
* License version 2, as published by the Free Software Foundation, and
6
-
* may be copied, distributed, and modified under those terms.
7
-
*
8
-
* This program is distributed in the hope that it will be useful,
9
-
* but WITHOUT ANY WARRANTY; without even the implied warranty of
10
-
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11
-
* GNU General Public License for more details.
12
4
*/
13
5
14
6
#include <linux/clk.h>
+4
-10
drivers/i2c/busses/i2c-cros-ec-tunnel.c
+4
-10
drivers/i2c/busses/i2c-cros-ec-tunnel.c
···
1
-
/*
2
-
* Copyright (C) 2013 Google, Inc
3
-
*
4
-
* This program is free software; you can redistribute it and/or modify
5
-
* it under the terms of the GNU General Public License as published by
6
-
* the Free Software Foundation; either version 2 of the License, or
7
-
* (at your option) any later version.
8
-
*
9
-
* Expose an I2C passthrough to the ChromeOS EC.
10
-
*/
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
// Expose an I2C passthrough to the ChromeOS EC.
3
+
//
4
+
// Copyright (C) 2013 Google, Inc.
11
5
12
6
#include <linux/module.h>
13
7
#include <linux/i2c.h>
+1
-1
drivers/i2c/busses/i2c-ibm_iic.c
+1
-1
drivers/i2c/busses/i2c-ibm_iic.c
+2
-1
drivers/i2c/busses/i2c-imx.c
+2
-1
drivers/i2c/busses/i2c-imx.c
···
1090
1090
/* Get I2C clock */
1091
1091
i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
1092
1092
if (IS_ERR(i2c_imx->clk)) {
1093
-
dev_err(&pdev->dev, "can't get I2C clock\n");
1093
+
if (PTR_ERR(i2c_imx->clk) != -EPROBE_DEFER)
1094
+
dev_err(&pdev->dev, "can't get I2C clock\n");
1094
1095
return PTR_ERR(i2c_imx->clk);
1095
1096
}
1096
1097
+2
drivers/i2c/busses/i2c-ismt.c
+2
drivers/i2c/busses/i2c-ismt.c
···
75
75
/* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
76
76
#define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59
77
77
#define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a
78
+
#define PCI_DEVICE_ID_INTEL_CDF_SMT 0x18ac
78
79
#define PCI_DEVICE_ID_INTEL_DNV_SMT 0x19ac
79
80
#define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15
80
81
···
182
181
static const struct pci_device_id ismt_ids[] = {
183
182
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) },
184
183
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) },
184
+
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMT) },
185
185
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMT) },
186
186
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) },
187
187
{ 0, }
+1
drivers/i2c/busses/i2c-owl.c
+1
drivers/i2c/busses/i2c-owl.c
+4
-4
drivers/i2c/busses/i2c-powermac.c
+4
-4
drivers/i2c/busses/i2c-powermac.c
···
229
229
return (be32_to_cpup(prop) & 0xff) >> 1;
230
230
231
231
/* Now handle some devices with missing "reg" properties */
232
-
if (!strcmp(node->name, "cereal"))
232
+
if (of_node_name_eq(node, "cereal"))
233
233
return 0x60;
234
-
else if (!strcmp(node->name, "deq"))
234
+
else if (of_node_name_eq(node, "deq"))
235
235
return 0x34;
236
236
237
237
dev_warn(&adap->dev, "No i2c address for %pOF\n", node);
···
304
304
}
305
305
306
306
/* Now look for known workarounds */
307
-
if (!strcmp(node->name, "deq")) {
307
+
if (of_node_name_eq(node, "deq")) {
308
308
/* Apple uses address 0x34 for TAS3001 and 0x35 for TAS3004 */
309
309
if (addr == 0x34) {
310
310
snprintf(type, type_size, "MAC,tas3001");
···
331
331
* case we skip this function completely as the device-tree will
332
332
* not contain anything useful.
333
333
*/
334
-
if (!strcmp(adap->dev.of_node->name, "via-pmu"))
334
+
if (of_node_name_eq(adap->dev.of_node, "via-pmu"))
335
335
return;
336
336
337
337
for_each_child_of_node(adap->dev.of_node, node) {
+2
drivers/i2c/busses/i2c-sh_mobile.c
+2
drivers/i2c/busses/i2c-sh_mobile.c
···
800
800
static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
801
801
{ .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
802
802
{ .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config },
803
+
{ .compatible = "renesas,iic-r8a774c0", .data = &fast_clock_dt_config },
803
804
{ .compatible = "renesas,iic-r8a7790", .data = &v2_freq_calc_dt_config },
804
805
{ .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config },
805
806
{ .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config },
···
809
808
{ .compatible = "renesas,rcar-gen2-iic", .data = &fast_clock_dt_config },
810
809
{ .compatible = "renesas,iic-r8a7795", .data = &fast_clock_dt_config },
811
810
{ .compatible = "renesas,rcar-gen3-iic", .data = &fast_clock_dt_config },
811
+
{ .compatible = "renesas,iic-r8a77990", .data = &fast_clock_dt_config },
812
812
{ .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
813
813
{ .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
814
814
{},
+136
-46
drivers/i2c/busses/i2c-stm32f7.c
+136
-46
drivers/i2c/busses/i2c-stm32f7.c
···
21
21
#include <linux/interrupt.h>
22
22
#include <linux/io.h>
23
23
#include <linux/iopoll.h>
24
+
#include <linux/mfd/syscon.h>
24
25
#include <linux/module.h>
25
26
#include <linux/of.h>
26
27
#include <linux/of_address.h>
27
28
#include <linux/of_irq.h>
28
29
#include <linux/of_platform.h>
29
30
#include <linux/platform_device.h>
31
+
#include <linux/pinctrl/consumer.h>
32
+
#include <linux/pm_runtime.h>
33
+
#include <linux/regmap.h>
30
34
#include <linux/reset.h>
31
35
#include <linux/slab.h>
32
36
···
167
163
#define STM32F7_SCLH_MAX BIT(8)
168
164
#define STM32F7_SCLL_MAX BIT(8)
169
165
166
+
#define STM32F7_AUTOSUSPEND_DELAY (HZ / 100)
167
+
170
168
/**
171
169
* struct stm32f7_i2c_spec - private i2c specification timing
172
170
* @rate: I2C bus speed (Hz)
···
282
276
* slave)
283
277
* @dma: dma data
284
278
* @use_dma: boolean to know if dma is used in the current transfer
279
+
* @regmap: holds SYSCFG phandle for Fast Mode Plus bits
285
280
*/
286
281
struct stm32f7_i2c_dev {
287
282
struct i2c_adapter adap;
···
303
296
bool master_mode;
304
297
struct stm32_i2c_dma *dma;
305
298
bool use_dma;
299
+
struct regmap *regmap;
306
300
};
307
301
308
302
/**
···
1553
1545
i2c_dev->msg_id = 0;
1554
1546
f7_msg->smbus = false;
1555
1547
1556
-
ret = clk_enable(i2c_dev->clk);
1557
-
if (ret) {
1558
-
dev_err(i2c_dev->dev, "Failed to enable clock\n");
1548
+
ret = pm_runtime_get_sync(i2c_dev->dev);
1549
+
if (ret < 0)
1559
1550
return ret;
1560
-
}
1561
1551
1562
1552
ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1563
1553
if (ret)
1564
-
goto clk_free;
1554
+
goto pm_free;
1565
1555
1566
1556
stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1567
1557
···
1575
1569
ret = -ETIMEDOUT;
1576
1570
}
1577
1571
1578
-
clk_free:
1579
-
clk_disable(i2c_dev->clk);
1572
+
pm_free:
1573
+
pm_runtime_mark_last_busy(i2c_dev->dev);
1574
+
pm_runtime_put_autosuspend(i2c_dev->dev);
1580
1575
1581
1576
return (ret < 0) ? ret : num;
1582
1577
}
···
1599
1592
f7_msg->read_write = read_write;
1600
1593
f7_msg->smbus = true;
1601
1594
1602
-
ret = clk_enable(i2c_dev->clk);
1603
-
if (ret) {
1604
-
dev_err(i2c_dev->dev, "Failed to enable clock\n");
1595
+
ret = pm_runtime_get_sync(dev);
1596
+
if (ret < 0)
1605
1597
return ret;
1606
-
}
1607
1598
1608
1599
ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1609
1600
if (ret)
1610
-
goto clk_free;
1601
+
goto pm_free;
1611
1602
1612
1603
ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1613
1604
if (ret)
1614
-
goto clk_free;
1605
+
goto pm_free;
1615
1606
1616
1607
timeout = wait_for_completion_timeout(&i2c_dev->complete,
1617
1608
i2c_dev->adap.timeout);
1618
1609
ret = f7_msg->result;
1619
1610
if (ret)
1620
-
goto clk_free;
1611
+
goto pm_free;
1621
1612
1622
1613
if (!timeout) {
1623
1614
dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1624
1615
if (i2c_dev->use_dma)
1625
1616
dmaengine_terminate_all(dma->chan_using);
1626
1617
ret = -ETIMEDOUT;
1627
-
goto clk_free;
1618
+
goto pm_free;
1628
1619
}
1629
1620
1630
1621
/* Check PEC */
1631
1622
if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1632
1623
ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1633
1624
if (ret)
1634
-
goto clk_free;
1625
+
goto pm_free;
1635
1626
}
1636
1627
1637
1628
if (read_write && size != I2C_SMBUS_QUICK) {
···
1654
1649
}
1655
1650
}
1656
1651
1657
-
clk_free:
1658
-
clk_disable(i2c_dev->clk);
1652
+
pm_free:
1653
+
pm_runtime_mark_last_busy(dev);
1654
+
pm_runtime_put_autosuspend(dev);
1659
1655
return ret;
1660
1656
}
1661
1657
···
1682
1676
if (ret)
1683
1677
return ret;
1684
1678
1685
-
if (!(stm32f7_i2c_is_slave_registered(i2c_dev))) {
1686
-
ret = clk_enable(i2c_dev->clk);
1687
-
if (ret) {
1688
-
dev_err(dev, "Failed to enable clock\n");
1689
-
return ret;
1690
-
}
1691
-
}
1679
+
ret = pm_runtime_get_sync(dev);
1680
+
if (ret < 0)
1681
+
return ret;
1692
1682
1693
1683
if (id == 0) {
1694
1684
/* Configure Own Address 1 */
···
1705
1703
oar2 &= ~STM32F7_I2C_OAR2_MASK;
1706
1704
if (slave->flags & I2C_CLIENT_TEN) {
1707
1705
ret = -EOPNOTSUPP;
1708
-
goto exit;
1706
+
goto pm_free;
1709
1707
}
1710
1708
1711
1709
oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
···
1714
1712
writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1715
1713
} else {
1716
1714
ret = -ENODEV;
1717
-
goto exit;
1715
+
goto pm_free;
1718
1716
}
1719
1717
1720
1718
/* Enable ACK */
···
1725
1723
STM32F7_I2C_CR1_PE;
1726
1724
stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1727
1725
1728
-
return 0;
1729
-
1730
-
exit:
1731
-
if (!(stm32f7_i2c_is_slave_registered(i2c_dev)))
1732
-
clk_disable(i2c_dev->clk);
1726
+
ret = 0;
1727
+
pm_free:
1728
+
pm_runtime_mark_last_busy(dev);
1729
+
pm_runtime_put_autosuspend(dev);
1733
1730
1734
1731
return ret;
1735
1732
}
···
1746
1745
1747
1746
WARN_ON(!i2c_dev->slave[id]);
1748
1747
1748
+
ret = pm_runtime_get_sync(i2c_dev->dev);
1749
+
if (ret < 0)
1750
+
return ret;
1751
+
1749
1752
if (id == 0) {
1750
1753
mask = STM32F7_I2C_OAR1_OA1EN;
1751
1754
stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
···
1760
1755
1761
1756
i2c_dev->slave[id] = NULL;
1762
1757
1763
-
if (!(stm32f7_i2c_is_slave_registered(i2c_dev))) {
1758
+
if (!(stm32f7_i2c_is_slave_registered(i2c_dev)))
1764
1759
stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1765
-
clk_disable(i2c_dev->clk);
1766
-
}
1760
+
1761
+
pm_runtime_mark_last_busy(i2c_dev->dev);
1762
+
pm_runtime_put_autosuspend(i2c_dev->dev);
1767
1763
1768
1764
return 0;
1765
+
}
1766
+
1767
+
static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
1768
+
struct stm32f7_i2c_dev *i2c_dev)
1769
+
{
1770
+
struct device_node *np = pdev->dev.of_node;
1771
+
int ret;
1772
+
u32 reg, mask;
1773
+
1774
+
i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
1775
+
if (IS_ERR(i2c_dev->regmap)) {
1776
+
/* Optional */
1777
+
return 0;
1778
+
}
1779
+
1780
+
ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1, ®);
1781
+
if (ret)
1782
+
return ret;
1783
+
1784
+
ret = of_property_read_u32_index(np, "st,syscfg-fmp", 2, &mask);
1785
+
if (ret)
1786
+
return ret;
1787
+
1788
+
return regmap_update_bits(i2c_dev->regmap, reg, mask, mask);
1769
1789
}
1770
1790
1771
1791
static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
···
1849
1819
dev_err(&pdev->dev, "Error: Missing controller clock\n");
1850
1820
return PTR_ERR(i2c_dev->clk);
1851
1821
}
1822
+
1852
1823
ret = clk_prepare_enable(i2c_dev->clk);
1853
1824
if (ret) {
1854
1825
dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
···
1859
1828
i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
1860
1829
ret = device_property_read_u32(&pdev->dev, "clock-frequency",
1861
1830
&clk_rate);
1862
-
if (!ret && clk_rate >= 1000000)
1831
+
if (!ret && clk_rate >= 1000000) {
1863
1832
i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS;
1864
-
else if (!ret && clk_rate >= 400000)
1833
+
ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
1834
+
if (ret)
1835
+
goto clk_free;
1836
+
} else if (!ret && clk_rate >= 400000) {
1865
1837
i2c_dev->speed = STM32_I2C_SPEED_FAST;
1866
-
else if (!ret && clk_rate >= 100000)
1838
+
} else if (!ret && clk_rate >= 100000) {
1867
1839
i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
1840
+
}
1868
1841
1869
1842
rst = devm_reset_control_get(&pdev->dev, NULL);
1870
1843
if (IS_ERR(rst)) {
···
1923
1888
if (ret)
1924
1889
goto clk_free;
1925
1890
1926
-
stm32f7_i2c_hw_config(i2c_dev);
1927
-
1928
1891
adap = &i2c_dev->adap;
1929
1892
i2c_set_adapdata(adap, i2c_dev);
1930
1893
snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
···
1941
1908
STM32F7_I2C_TXDR,
1942
1909
STM32F7_I2C_RXDR);
1943
1910
1944
-
ret = i2c_add_adapter(adap);
1945
-
if (ret)
1946
-
goto clk_free;
1947
-
1948
1911
platform_set_drvdata(pdev, i2c_dev);
1949
1912
1950
-
clk_disable(i2c_dev->clk);
1913
+
pm_runtime_set_autosuspend_delay(i2c_dev->dev,
1914
+
STM32F7_AUTOSUSPEND_DELAY);
1915
+
pm_runtime_use_autosuspend(i2c_dev->dev);
1916
+
pm_runtime_set_active(i2c_dev->dev);
1917
+
pm_runtime_enable(i2c_dev->dev);
1918
+
1919
+
pm_runtime_get_noresume(&pdev->dev);
1920
+
1921
+
stm32f7_i2c_hw_config(i2c_dev);
1922
+
1923
+
ret = i2c_add_adapter(adap);
1924
+
if (ret)
1925
+
goto pm_disable;
1951
1926
1952
1927
dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
1953
1928
1929
+
pm_runtime_mark_last_busy(i2c_dev->dev);
1930
+
pm_runtime_put_autosuspend(i2c_dev->dev);
1931
+
1954
1932
return 0;
1933
+
1934
+
pm_disable:
1935
+
pm_runtime_put_noidle(i2c_dev->dev);
1936
+
pm_runtime_disable(i2c_dev->dev);
1937
+
pm_runtime_set_suspended(i2c_dev->dev);
1938
+
pm_runtime_dont_use_autosuspend(i2c_dev->dev);
1955
1939
1956
1940
clk_free:
1957
1941
clk_disable_unprepare(i2c_dev->clk);
···
1986
1936
}
1987
1937
1988
1938
i2c_del_adapter(&i2c_dev->adap);
1939
+
pm_runtime_get_sync(i2c_dev->dev);
1989
1940
1990
-
clk_unprepare(i2c_dev->clk);
1941
+
clk_disable_unprepare(i2c_dev->clk);
1942
+
1943
+
pm_runtime_put_noidle(i2c_dev->dev);
1944
+
pm_runtime_disable(i2c_dev->dev);
1945
+
pm_runtime_set_suspended(i2c_dev->dev);
1946
+
pm_runtime_dont_use_autosuspend(i2c_dev->dev);
1991
1947
1992
1948
return 0;
1993
1949
}
1950
+
1951
+
#ifdef CONFIG_PM
1952
+
static int stm32f7_i2c_runtime_suspend(struct device *dev)
1953
+
{
1954
+
struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1955
+
1956
+
if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1957
+
clk_disable_unprepare(i2c_dev->clk);
1958
+
1959
+
return 0;
1960
+
}
1961
+
1962
+
static int stm32f7_i2c_runtime_resume(struct device *dev)
1963
+
{
1964
+
struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1965
+
int ret;
1966
+
1967
+
if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
1968
+
ret = clk_prepare_enable(i2c_dev->clk);
1969
+
if (ret) {
1970
+
dev_err(dev, "failed to prepare_enable clock\n");
1971
+
return ret;
1972
+
}
1973
+
}
1974
+
1975
+
return 0;
1976
+
}
1977
+
#endif
1978
+
1979
+
static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
1980
+
SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
1981
+
stm32f7_i2c_runtime_resume, NULL)
1982
+
};
1994
1983
1995
1984
static const struct of_device_id stm32f7_i2c_match[] = {
1996
1985
{ .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
···
2041
1952
.driver = {
2042
1953
.name = "stm32f7-i2c",
2043
1954
.of_match_table = stm32f7_i2c_match,
1955
+
.pm = &stm32f7_i2c_pm_ops,
2044
1956
},
2045
1957
.probe = stm32f7_i2c_probe,
2046
1958
.remove = stm32f7_i2c_remove,
+29
-25
drivers/i2c/busses/i2c-tegra.c
+29
-25
drivers/i2c/busses/i2c-tegra.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
1
2
/*
2
3
* drivers/i2c/busses/i2c-tegra.c
3
4
*
4
5
* Copyright (C) 2010 Google, Inc.
5
6
* Author: Colin Cross <ccross@android.com>
6
-
*
7
-
* This software is licensed under the terms of the GNU General Public
8
-
* License version 2, as published by the Free Software Foundation, and
9
-
* may be copied, distributed, and modified under those terms.
10
-
*
11
-
* This program is distributed in the hope that it will be useful,
12
-
* but WITHOUT ANY WARRANTY; without even the implied warranty of
13
-
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
-
* GNU General Public License for more details.
15
-
*
16
7
*/
17
8
18
9
#include <linux/kernel.h>
···
136
145
* @has_continue_xfer_support: Continue transfer supports.
137
146
* @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
138
147
* complete interrupt per packet basis.
139
-
* @has_single_clk_source: The i2c controller has single clock source. Tegra30
140
-
* and earlier Socs has two clock sources i.e. div-clk and
148
+
* @has_single_clk_source: The I2C controller has single clock source. Tegra30
149
+
* and earlier SoCs have two clock sources i.e. div-clk and
141
150
* fast-clk.
142
151
* @has_config_load_reg: Has the config load register to load the new
143
152
* configuration.
···
145
154
* @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
146
155
* applicable if there is no fast clock source i.e. single clock
147
156
* source.
157
+
* @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
158
+
* applicable if there is no fast clock source (i.e. single
159
+
* clock source).
160
+
* @has_multi_master_mode: The I2C controller supports running in single-master
161
+
* or multi-master mode.
162
+
* @has_slcg_override_reg: The I2C controller supports a register that
163
+
* overrides the second level clock gating.
164
+
* @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
165
+
* provides additional features and allows for longer messages to
166
+
* be transferred in one go.
148
167
*/
149
-
150
168
struct tegra_i2c_hw_feature {
151
169
bool has_continue_xfer_support;
152
170
bool has_per_pkt_xfer_complete_irq;
···
170
170
};
171
171
172
172
/**
173
-
* struct tegra_i2c_dev - per device i2c context
173
+
* struct tegra_i2c_dev - per device I2C context
174
174
* @dev: device reference for power management
175
-
* @hw: Tegra i2c hw feature.
176
-
* @adapter: core i2c layer adapter information
177
-
* @div_clk: clock reference for div clock of i2c controller.
178
-
* @fast_clk: clock reference for fast clock of i2c controller.
175
+
* @hw: Tegra I2C HW feature
176
+
* @adapter: core I2C layer adapter information
177
+
* @div_clk: clock reference for div clock of I2C controller
178
+
* @fast_clk: clock reference for fast clock of I2C controller
179
+
* @rst: reset control for the I2C controller
179
180
* @base: ioremapped registers cookie
180
-
* @cont_id: i2c controller id, used for for packet header
181
-
* @irq: irq number of transfer complete interrupt
182
-
* @is_dvc: identifies the DVC i2c controller, has a different register layout
181
+
* @cont_id: I2C controller ID, used for packet header
182
+
* @irq: IRQ number of transfer complete interrupt
183
+
* @irq_disabled: used to track whether or not the interrupt is enabled
184
+
* @is_dvc: identifies the DVC I2C controller, has a different register layout
183
185
* @msg_complete: transfer completion notifier
184
186
* @msg_err: error code for completed message
185
187
* @msg_buf: pointer to current message data
186
188
* @msg_buf_remaining: size of unsent data in the message buffer
187
189
* @msg_read: identifies read transfers
188
-
* @bus_clk_rate: current i2c bus clock rate
190
+
* @bus_clk_rate: current I2C bus clock rate
191
+
* @clk_divisor_non_hs_mode: clock divider for non-high-speed modes
192
+
* @is_multimaster_mode: track if I2C controller is in multi-master mode
193
+
* @xfer_lock: lock to serialize transfer submission and processing
189
194
*/
190
195
struct tegra_i2c_dev {
191
196
struct device *dev;
···
613
608
u32 status;
614
609
const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
615
610
struct tegra_i2c_dev *i2c_dev = dev_id;
616
-
unsigned long flags;
617
611
618
612
status = i2c_readl(i2c_dev, I2C_INT_STATUS);
619
613
620
-
spin_lock_irqsave(&i2c_dev->xfer_lock, flags);
614
+
spin_lock(&i2c_dev->xfer_lock);
621
615
if (status == 0) {
622
616
dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
623
617
i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
···
674
670
675
671
complete(&i2c_dev->msg_complete);
676
672
done:
677
-
spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags);
673
+
spin_unlock(&i2c_dev->xfer_lock);
678
674
return IRQ_HANDLED;
679
675
}
680
676
+1
-1
drivers/misc/eeprom/Kconfig
+1
-1
drivers/misc/eeprom/Kconfig
···
13
13
ones like at24c64, 24lc02 or fm24c04:
14
14
15
15
24c00, 24c01, 24c02, spd (readonly 24c02), 24c04, 24c08,
16
-
24c16, 24c32, 24c64, 24c128, 24c256, 24c512, 24c1024
16
+
24c16, 24c32, 24c64, 24c128, 24c256, 24c512, 24c1024, 24c2048
17
17
18
18
Unless you like data loss puzzles, always be sure that any chip
19
19
you configure as a 24c32 (32 kbit) or larger is NOT really a
+3
drivers/misc/eeprom/at24.c
+3
drivers/misc/eeprom/at24.c
···
156
156
AT24_CHIP_DATA(at24_data_24c256, 262144 / 8, AT24_FLAG_ADDR16);
157
157
AT24_CHIP_DATA(at24_data_24c512, 524288 / 8, AT24_FLAG_ADDR16);
158
158
AT24_CHIP_DATA(at24_data_24c1024, 1048576 / 8, AT24_FLAG_ADDR16);
159
+
AT24_CHIP_DATA(at24_data_24c2048, 2097152 / 8, AT24_FLAG_ADDR16);
159
160
/* identical to 24c08 ? */
160
161
AT24_CHIP_DATA(at24_data_INT3499, 8192 / 8, 0);
161
162
···
183
182
{ "24c256", (kernel_ulong_t)&at24_data_24c256 },
184
183
{ "24c512", (kernel_ulong_t)&at24_data_24c512 },
185
184
{ "24c1024", (kernel_ulong_t)&at24_data_24c1024 },
185
+
{ "24c2048", (kernel_ulong_t)&at24_data_24c2048 },
186
186
{ "at24", 0 },
187
187
{ /* END OF LIST */ }
188
188
};
···
212
210
{ .compatible = "atmel,24c256", .data = &at24_data_24c256 },
213
211
{ .compatible = "atmel,24c512", .data = &at24_data_24c512 },
214
212
{ .compatible = "atmel,24c1024", .data = &at24_data_24c1024 },
213
+
{ .compatible = "atmel,24c2048", .data = &at24_data_24c2048 },
215
214
{ /* END OF LIST */ },
216
215
};
217
216
MODULE_DEVICE_TABLE(of, at24_of_match);