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dt-bindings: iio: dac: ad3552r: add iio backend support

There is a version of AXI DAC IP block (for FPGAs) that provides
a physical QSPI bus for AD3552R and similar chips, so supporting
spi-controller functionalities.

For this case, the binding is modified to include some additional
properties.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Reviewed-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20241028-wip-bl-ad3552r-axi-v0-iio-testing-v9-1-f6960b4f9719@kernel-space.org
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

authored by

Angelo Dureghello and committed by
Jonathan Cameron 76830926 f928099e

+7
+7
Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml
··· 60 60 $ref: /schemas/types.yaml#/definitions/uint32 61 61 enum: [0, 1, 2, 3] 62 62 63 + io-backends: 64 + description: The iio backend reference. 65 + Device can be optionally connected to the "axi-ad3552r IP" fpga-based 66 + QSPI + DDR (Double Data Rate) controller to reach high speed transfers. 67 + maxItems: 1 68 + 63 69 '#address-cells': 64 70 const: 1 65 71 ··· 134 128 - custom-output-range-config 135 129 136 130 allOf: 131 + - $ref: /schemas/spi/spi-peripheral-props.yaml# 137 132 - if: 138 133 properties: 139 134 compatible: