Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'riscv/for-v5.5-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Paul Walmsley:
"Several fixes for RISC-V:
- Fix function graph trace support
- Prefix the CSR IRQ_* macro names with "RV_", to avoid collisions
with macros elsewhere in the Linux kernel tree named "IRQ_TIMER"
- Use __pa_symbol() when computing the physical address of a kernel
symbol, rather than __pa()
- Mark the RISC-V port as supporting GCOV
One DT addition:
- Describe the L2 cache controller in the FU540 DT file
One documentation update:
- Add patch acceptance guideline documentation"
* tag 'riscv/for-v5.5-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
Documentation: riscv: add patch acceptance guidelines
riscv: prefix IRQ_ macro names with an RV_ namespace
clocksource: riscv: add notrace to riscv_sched_clock
riscv: ftrace: correct the condition logic in function graph tracer
riscv: dts: Add DT support for SiFive L2 cache controller
riscv: gcov: enable gcov for RISC-V
riscv: mm: use __pa_symbol for kernel symbols
+76
-22
+1
-1
Documentation/features/debug/gcov-profile-all/arch-support.txt
+1
-1
Documentation/features/debug/gcov-profile-all/arch-support.txt
+1
Documentation/process/index.rst
+1
Documentation/process/index.rst
+1
Documentation/riscv/index.rst
+1
Documentation/riscv/index.rst
+35
Documentation/riscv/patch-acceptance.rst
+35
Documentation/riscv/patch-acceptance.rst
···
1
+
.. SPDX-License-Identifier: GPL-2.0
2
+
3
+
arch/riscv maintenance guidelines for developers
4
+
================================================
5
+
6
+
Overview
7
+
--------
8
+
The RISC-V instruction set architecture is developed in the open:
9
+
in-progress drafts are available for all to review and to experiment
10
+
with implementations. New module or extension drafts can change
11
+
during the development process - sometimes in ways that are
12
+
incompatible with previous drafts. This flexibility can present a
13
+
challenge for RISC-V Linux maintenance. Linux maintainers disapprove
14
+
of churn, and the Linux development process prefers well-reviewed and
15
+
tested code over experimental code. We wish to extend these same
16
+
principles to the RISC-V-related code that will be accepted for
17
+
inclusion in the kernel.
18
+
19
+
Submit Checklist Addendum
20
+
-------------------------
21
+
We'll only accept patches for new modules or extensions if the
22
+
specifications for those modules or extensions are listed as being
23
+
"Frozen" or "Ratified" by the RISC-V Foundation. (Developers may, of
24
+
course, maintain their own Linux kernel trees that contain code for
25
+
any draft extensions that they wish.)
26
+
27
+
Additionally, the RISC-V specification allows implementors to create
28
+
their own custom extensions. These custom extensions aren't required
29
+
to go through any review or ratification process by the RISC-V
30
+
Foundation. To avoid the maintenance complexity and potential
31
+
performance impact of adding kernel code for implementor-specific
32
+
RISC-V extensions, we'll only to accept patches for extensions that
33
+
have been officially frozen or ratified by the RISC-V Foundation.
34
+
(Implementors, may, of course, maintain their own Linux kernel trees
35
+
containing code for any custom extensions that they wish.)
+1
MAINTAINERS
+1
MAINTAINERS
···
14121
14121
M: Palmer Dabbelt <palmer@dabbelt.com>
14122
14122
M: Albert Ou <aou@eecs.berkeley.edu>
14123
14123
L: linux-riscv@lists.infradead.org
14124
+
P: Documentation/riscv/patch-acceptance.rst
14124
14125
T: git git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
14125
14126
S: Supported
14126
14127
F: arch/riscv/
+1
arch/riscv/Kconfig
+1
arch/riscv/Kconfig
+15
arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+15
arch/riscv/boot/dts/sifive/fu540-c000.dtsi
···
54
54
reg = <1>;
55
55
riscv,isa = "rv64imafdc";
56
56
tlb-split;
57
+
next-level-cache = <&l2cache>;
57
58
cpu1_intc: interrupt-controller {
58
59
#interrupt-cells = <1>;
59
60
compatible = "riscv,cpu-intc";
···
78
77
reg = <2>;
79
78
riscv,isa = "rv64imafdc";
80
79
tlb-split;
80
+
next-level-cache = <&l2cache>;
81
81
cpu2_intc: interrupt-controller {
82
82
#interrupt-cells = <1>;
83
83
compatible = "riscv,cpu-intc";
···
102
100
reg = <3>;
103
101
riscv,isa = "rv64imafdc";
104
102
tlb-split;
103
+
next-level-cache = <&l2cache>;
105
104
cpu3_intc: interrupt-controller {
106
105
#interrupt-cells = <1>;
107
106
compatible = "riscv,cpu-intc";
···
126
123
reg = <4>;
127
124
riscv,isa = "rv64imafdc";
128
125
tlb-split;
126
+
next-level-cache = <&l2cache>;
129
127
cpu4_intc: interrupt-controller {
130
128
#interrupt-cells = <1>;
131
129
compatible = "riscv,cpu-intc";
···
256
252
clocks = <&prci PRCI_CLK_TLCLK>;
257
253
#pwm-cells = <3>;
258
254
status = "disabled";
255
+
};
256
+
l2cache: cache-controller@2010000 {
257
+
compatible = "sifive,fu540-c000-ccache", "cache";
258
+
cache-block-size = <64>;
259
+
cache-level = <2>;
260
+
cache-sets = <1024>;
261
+
cache-size = <2097152>;
262
+
cache-unified;
263
+
interrupt-parent = <&plic0>;
264
+
interrupts = <1 2 3>;
265
+
reg = <0x0 0x2010000 0x0 0x1000>;
259
266
};
260
267
261
268
};
+9
-9
arch/riscv/include/asm/csr.h
+9
-9
arch/riscv/include/asm/csr.h
···
116
116
# define SR_PIE SR_MPIE
117
117
# define SR_PP SR_MPP
118
118
119
-
# define IRQ_SOFT IRQ_M_SOFT
120
-
# define IRQ_TIMER IRQ_M_TIMER
121
-
# define IRQ_EXT IRQ_M_EXT
119
+
# define RV_IRQ_SOFT IRQ_M_SOFT
120
+
# define RV_IRQ_TIMER IRQ_M_TIMER
121
+
# define RV_IRQ_EXT IRQ_M_EXT
122
122
#else /* CONFIG_RISCV_M_MODE */
123
123
# define CSR_STATUS CSR_SSTATUS
124
124
# define CSR_IE CSR_SIE
···
133
133
# define SR_PIE SR_SPIE
134
134
# define SR_PP SR_SPP
135
135
136
-
# define IRQ_SOFT IRQ_S_SOFT
137
-
# define IRQ_TIMER IRQ_S_TIMER
138
-
# define IRQ_EXT IRQ_S_EXT
136
+
# define RV_IRQ_SOFT IRQ_S_SOFT
137
+
# define RV_IRQ_TIMER IRQ_S_TIMER
138
+
# define RV_IRQ_EXT IRQ_S_EXT
139
139
#endif /* CONFIG_RISCV_M_MODE */
140
140
141
141
/* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
142
-
#define IE_SIE (_AC(0x1, UL) << IRQ_SOFT)
143
-
#define IE_TIE (_AC(0x1, UL) << IRQ_TIMER)
144
-
#define IE_EIE (_AC(0x1, UL) << IRQ_EXT)
142
+
#define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT)
143
+
#define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER)
144
+
#define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)
145
145
146
146
#ifndef __ASSEMBLY__
147
147
+1
-1
arch/riscv/kernel/ftrace.c
+1
-1
arch/riscv/kernel/ftrace.c
+3
-3
arch/riscv/kernel/irq.c
+3
-3
arch/riscv/kernel/irq.c
···
23
23
24
24
irq_enter();
25
25
switch (regs->cause & ~CAUSE_IRQ_FLAG) {
26
-
case IRQ_TIMER:
26
+
case RV_IRQ_TIMER:
27
27
riscv_timer_interrupt();
28
28
break;
29
29
#ifdef CONFIG_SMP
30
-
case IRQ_SOFT:
30
+
case RV_IRQ_SOFT:
31
31
/*
32
32
* We only use software interrupts to pass IPIs, so if a non-SMP
33
33
* system gets one, then we don't know what to do.
···
35
35
riscv_software_interrupt();
36
36
break;
37
37
#endif
38
-
case IRQ_EXT:
38
+
case RV_IRQ_EXT:
39
39
handle_arch_irq(regs);
40
40
break;
41
41
default:
+6
-6
arch/riscv/mm/init.c
+6
-6
arch/riscv/mm/init.c
···
99
99
pr_info("initrd not found or empty");
100
100
goto disable;
101
101
}
102
-
if (__pa(initrd_end) > PFN_PHYS(max_low_pfn)) {
102
+
if (__pa_symbol(initrd_end) > PFN_PHYS(max_low_pfn)) {
103
103
pr_err("initrd extends beyond end of memory");
104
104
goto disable;
105
105
}
106
106
107
107
size = initrd_end - initrd_start;
108
-
memblock_reserve(__pa(initrd_start), size);
108
+
memblock_reserve(__pa_symbol(initrd_start), size);
109
109
initrd_below_start_ok = 1;
110
110
111
111
pr_info("Initial ramdisk at: 0x%p (%lu bytes)\n",
···
124
124
{
125
125
struct memblock_region *reg;
126
126
phys_addr_t mem_size = 0;
127
-
phys_addr_t vmlinux_end = __pa(&_end);
128
-
phys_addr_t vmlinux_start = __pa(&_start);
127
+
phys_addr_t vmlinux_end = __pa_symbol(&_end);
128
+
phys_addr_t vmlinux_start = __pa_symbol(&_start);
129
129
130
130
/* Find the memory region containing the kernel */
131
131
for_each_memblock(memory, reg) {
···
445
445
446
446
/* Setup swapper PGD for fixmap */
447
447
create_pgd_mapping(swapper_pg_dir, FIXADDR_START,
448
-
__pa(fixmap_pgd_next),
448
+
__pa_symbol(fixmap_pgd_next),
449
449
PGDIR_SIZE, PAGE_TABLE);
450
450
451
451
/* Map all memory banks */
···
474
474
clear_fixmap(FIX_PMD);
475
475
476
476
/* Move to swapper page table */
477
-
csr_write(CSR_SATP, PFN_DOWN(__pa(swapper_pg_dir)) | SATP_MODE);
477
+
csr_write(CSR_SATP, PFN_DOWN(__pa_symbol(swapper_pg_dir)) | SATP_MODE);
478
478
local_flush_tlb_all();
479
479
}
480
480
#else
+1
-1
drivers/clocksource/timer-riscv.c
+1
-1
drivers/clocksource/timer-riscv.c