Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
iio: adc: ad7173: add AD7173 driver
The AD7173 family offer a complete integrated Sigma-Delta ADC solution
which can be used in high precision, low noise single channel
applications or higher speed multiplexed applications. The Sigma-Delta
ADC is intended primarily for measurement of signals close to DC but also
delivers outstanding performance with input bandwidths out to ~10kHz.
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Reviewed-by: Michael Walle <michael@walle.cc> # for gpio-regmap
Signed-off-by: Dumitru Ceclan <mitrutzceclan@gmail.com>
Reviewed-by: Nuno Sa <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20240228110622.25114-3-mitrutzceclan@gmail.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
authored by
Dumitru Ceclan
and committed by
Jonathan Cameron
76a1e6a4
7b0c9f8f
+1134
+17
drivers/iio/adc/Kconfig
+17
drivers/iio/adc/Kconfig
···
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To compile this driver as a module, choose M here: the module will be
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called ad7124.
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config AD7173
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tristate "Analog Devices AD7173 driver"
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depends on SPI_MASTER
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select AD_SIGMA_DELTA
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select GPIO_REGMAP if GPIOLIB
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select REGMAP_SPI if GPIOLIB
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help
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Say yes here to build support for Analog Devices AD7173 and similar ADC
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Currently supported models:
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- AD7172-2
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- AD7173-8
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- AD7175-2
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- AD7176-2
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To compile this driver as a module, choose M here: the module will be
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called ad7173.
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config AD7192
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tristate "Analog Devices AD7190 AD7192 AD7193 AD7195 ADC driver"
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depends on SPI
+1
drivers/iio/adc/Makefile
+1
drivers/iio/adc/Makefile
+1116
drivers/iio/adc/ad7173.c
+1116
drivers/iio/adc/ad7173.c
···
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* AD7172-2/AD7173-8/AD7175-2/AD7176-2 SPI ADC driver
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* Copyright (C) 2015, 2024 Analog Devices, Inc.
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*/
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+
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#include <linux/array_size.h>
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#include <linux/bitfield.h>
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#include <linux/bitmap.h>
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#include <linux/container_of.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/gpio/driver.h>
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#include <linux/gpio/regmap.h>
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#include <linux/idr.h>
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#include <linux/interrupt.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <linux/types.h>
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#include <linux/units.h>
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+
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#include <linux/iio/buffer.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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+
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#include <linux/iio/adc/ad_sigma_delta.h>
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+
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#define AD7173_REG_COMMS 0x00
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#define AD7173_REG_ADC_MODE 0x01
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#define AD7173_REG_INTERFACE_MODE 0x02
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#define AD7173_REG_CRC 0x03
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#define AD7173_REG_DATA 0x04
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#define AD7173_REG_GPIO 0x06
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#define AD7173_REG_ID 0x07
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#define AD7173_REG_CH(x) (0x10 + (x))
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#define AD7173_REG_SETUP(x) (0x20 + (x))
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#define AD7173_REG_FILTER(x) (0x28 + (x))
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#define AD7173_REG_OFFSET(x) (0x30 + (x))
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#define AD7173_REG_GAIN(x) (0x38 + (x))
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+
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#define AD7173_RESET_LENGTH BITS_TO_BYTES(64)
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+
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#define AD7173_CH_ENABLE BIT(15)
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#define AD7173_CH_SETUP_SEL_MASK GENMASK(14, 12)
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#define AD7173_CH_SETUP_AINPOS_MASK GENMASK(9, 5)
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#define AD7173_CH_SETUP_AINNEG_MASK GENMASK(4, 0)
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#define AD7173_CH_ADDRESS(pos, neg) \
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(FIELD_PREP(AD7173_CH_SETUP_AINPOS_MASK, pos) | \
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FIELD_PREP(AD7173_CH_SETUP_AINNEG_MASK, neg))
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#define AD7173_AIN_TEMP_POS 17
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#define AD7173_AIN_TEMP_NEG 18
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+
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#define AD7172_ID 0x00d0
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#define AD7173_ID 0x30d0
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#define AD7175_ID 0x0cd0
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#define AD7176_ID 0x0c90
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#define AD7173_ID_MASK GENMASK(15, 4)
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#define AD7173_ADC_MODE_REF_EN BIT(15)
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#define AD7173_ADC_MODE_SING_CYC BIT(13)
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#define AD7173_ADC_MODE_MODE_MASK GENMASK(6, 4)
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#define AD7173_ADC_MODE_CLOCKSEL_MASK GENMASK(3, 2)
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#define AD7173_ADC_MODE_CLOCKSEL_INT 0x0
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#define AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT 0x1
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#define AD7173_ADC_MODE_CLOCKSEL_EXT 0x2
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#define AD7173_ADC_MODE_CLOCKSEL_XTAL 0x3
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#define AD7173_GPIO_PDSW BIT(14)
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#define AD7173_GPIO_OP_EN2_3 BIT(13)
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#define AD7173_GPIO_MUX_IO BIT(12)
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#define AD7173_GPIO_SYNC_EN BIT(11)
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#define AD7173_GPIO_ERR_EN BIT(10)
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#define AD7173_GPIO_ERR_DAT BIT(9)
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#define AD7173_GPIO_GP_DATA3 BIT(7)
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#define AD7173_GPIO_GP_DATA2 BIT(6)
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#define AD7173_GPIO_IP_EN1 BIT(5)
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#define AD7173_GPIO_IP_EN0 BIT(4)
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#define AD7173_GPIO_OP_EN1 BIT(3)
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#define AD7173_GPIO_OP_EN0 BIT(2)
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#define AD7173_GPIO_GP_DATA1 BIT(1)
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#define AD7173_GPIO_GP_DATA0 BIT(0)
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#define AD7173_GPO12_DATA(x) BIT((x) + 0)
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#define AD7173_GPO23_DATA(x) BIT((x) + 4)
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#define AD7173_GPO_DATA(x) ((x) < 2 ? AD7173_GPO12_DATA(x) : AD7173_GPO23_DATA(x))
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+
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#define AD7173_INTERFACE_DATA_STAT BIT(6)
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#define AD7173_INTERFACE_DATA_STAT_EN(x) \
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FIELD_PREP(AD7173_INTERFACE_DATA_STAT, x)
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#define AD7173_SETUP_BIPOLAR BIT(12)
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#define AD7173_SETUP_AREF_BUF_MASK GENMASK(11, 10)
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#define AD7173_SETUP_AIN_BUF_MASK GENMASK(9, 8)
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#define AD7173_SETUP_REF_SEL_MASK GENMASK(5, 4)
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#define AD7173_SETUP_REF_SEL_AVDD1_AVSS 0x3
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#define AD7173_SETUP_REF_SEL_INT_REF 0x2
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#define AD7173_SETUP_REF_SEL_EXT_REF2 0x1
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#define AD7173_SETUP_REF_SEL_EXT_REF 0x0
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#define AD7173_VOLTAGE_INT_REF_uV 2500000
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#define AD7173_TEMP_SENSIIVITY_uV_per_C 477
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#define AD7173_FILTER_ODR0_MASK GENMASK(5, 0)
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#define AD7173_MAX_CONFIGS 8
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enum ad7173_ids {
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ID_AD7172_2,
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ID_AD7173_8,
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ID_AD7175_2,
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ID_AD7176_2,
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};
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struct ad7173_device_info {
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const unsigned int *sinc5_data_rates;
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unsigned int num_sinc5_data_rates;
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unsigned int num_channels;
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unsigned int num_configs;
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unsigned int num_inputs;
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unsigned int clock;
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unsigned int id;
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char *name;
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bool has_temp;
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u8 num_gpios;
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};
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struct ad7173_channel_config {
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u8 cfg_slot;
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bool live;
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+
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/* Following fields are used to compare equality. */
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struct_group(config_props,
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bool bipolar;
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bool input_buf;
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u8 odr;
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u8 ref_sel;
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);
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};
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struct ad7173_channel {
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unsigned int chan_reg;
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unsigned int ain;
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struct ad7173_channel_config cfg;
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};
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struct ad7173_state {
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struct ad_sigma_delta sd;
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const struct ad7173_device_info *info;
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struct ad7173_channel *channels;
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struct regulator_bulk_data regulators[3];
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unsigned int adc_mode;
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unsigned int interface_mode;
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unsigned int num_channels;
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struct ida cfg_slots_status;
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unsigned long long config_usage_counter;
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unsigned long long *config_cnts;
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struct clk *ext_clk;
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struct clk_hw int_clk_hw;
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#if IS_ENABLED(CONFIG_GPIOLIB)
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struct regmap *reg_gpiocon_regmap;
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struct gpio_regmap *gpio_regmap;
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#endif
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};
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static const unsigned int ad7173_sinc5_data_rates[] = {
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6211000, 6211000, 6211000, 6211000, 6211000, 6211000, 5181000, 4444000, /* 0-7 */
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3115000, 2597000, 1007000, 503800, 381000, 200300, 100500, 59520, /* 8-15 */
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49680, 20010, 16333, 10000, 5000, 2500, 1250, /* 16-22 */
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};
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static const unsigned int ad7175_sinc5_data_rates[] = {
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50000000, 41667000, 31250000, 27778000, /* 0-3 */
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20833000, 17857000, 12500000, 10000000, /* 4-7 */
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5000000, 2500000, 1000000, 500000, /* 8-11 */
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397500, 200000, 100000, 59920, /* 12-15 */
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49960, 20000, 16666, 10000, /* 16-19 */
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5000, /* 20 */
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};
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static const struct ad7173_device_info ad7173_device_info[] = {
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[ID_AD7172_2] = {
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.name = "ad7172-2",
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.id = AD7172_ID,
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.num_inputs = 5,
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.num_channels = 4,
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.num_configs = 4,
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.num_gpios = 2,
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.has_temp = true,
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.clock = 2 * HZ_PER_MHZ,
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.sinc5_data_rates = ad7173_sinc5_data_rates,
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.num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
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},
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[ID_AD7173_8] = {
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.name = "ad7173-8",
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.id = AD7173_ID,
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.num_inputs = 17,
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.num_channels = 16,
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.num_configs = 8,
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.num_gpios = 4,
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.has_temp = true,
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.clock = 2 * HZ_PER_MHZ,
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.sinc5_data_rates = ad7173_sinc5_data_rates,
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.num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
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},
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[ID_AD7175_2] = {
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.name = "ad7175-2",
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.id = AD7175_ID,
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.num_inputs = 5,
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.num_channels = 4,
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.num_configs = 4,
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.num_gpios = 2,
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.has_temp = true,
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.clock = 16 * HZ_PER_MHZ,
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.sinc5_data_rates = ad7175_sinc5_data_rates,
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.num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
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},
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[ID_AD7176_2] = {
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.name = "ad7176-2",
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.id = AD7176_ID,
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.num_inputs = 5,
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.num_channels = 4,
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.num_configs = 4,
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.num_gpios = 2,
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.has_temp = false,
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.clock = 16 * HZ_PER_MHZ,
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.sinc5_data_rates = ad7175_sinc5_data_rates,
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.num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
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},
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};
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static const char *const ad7173_ref_sel_str[] = {
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[AD7173_SETUP_REF_SEL_EXT_REF] = "vref",
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[AD7173_SETUP_REF_SEL_EXT_REF2] = "vref2",
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[AD7173_SETUP_REF_SEL_INT_REF] = "refout-avss",
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[AD7173_SETUP_REF_SEL_AVDD1_AVSS] = "avdd",
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};
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static const char *const ad7173_clk_sel[] = {
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"ext-clk", "xtal"
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};
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+
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#if IS_ENABLED(CONFIG_GPIOLIB)
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+
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static const struct regmap_range ad7173_range_gpio[] = {
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regmap_reg_range(AD7173_REG_GPIO, AD7173_REG_GPIO),
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};
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static const struct regmap_access_table ad7173_access_table = {
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.yes_ranges = ad7173_range_gpio,
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.n_yes_ranges = ARRAY_SIZE(ad7173_range_gpio),
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};
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static const struct regmap_config ad7173_regmap_config = {
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.reg_bits = 8,
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.val_bits = 16,
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.rd_table = &ad7173_access_table,
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.wr_table = &ad7173_access_table,
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.read_flag_mask = BIT(6),
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};
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+
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static int ad7173_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
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unsigned int offset, unsigned int *reg,
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unsigned int *mask)
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{
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*mask = AD7173_GPO_DATA(offset);
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*reg = base;
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return 0;
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}
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+
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static void ad7173_gpio_disable(void *data)
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{
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struct ad7173_state *st = data;
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unsigned int mask;
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+
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mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3;
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regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, ~mask);
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}
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+
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static int ad7173_gpio_init(struct ad7173_state *st)
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{
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struct gpio_regmap_config gpio_regmap = {};
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struct device *dev = &st->sd.spi->dev;
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unsigned int mask;
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int ret;
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+
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st->reg_gpiocon_regmap = devm_regmap_init_spi(st->sd.spi, &ad7173_regmap_config);
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ret = PTR_ERR_OR_ZERO(st->reg_gpiocon_regmap);
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if (ret)
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return dev_err_probe(dev, ret, "Unable to init regmap\n");
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+
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mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3;
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regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, mask);
303
+
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ret = devm_add_action_or_reset(dev, ad7173_gpio_disable, st);
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if (ret)
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return ret;
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+
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gpio_regmap.parent = dev;
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gpio_regmap.regmap = st->reg_gpiocon_regmap;
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gpio_regmap.ngpio = st->info->num_gpios;
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gpio_regmap.reg_set_base = AD7173_REG_GPIO;
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gpio_regmap.reg_mask_xlate = ad7173_mask_xlate;
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+
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st->gpio_regmap = devm_gpio_regmap_register(dev, &gpio_regmap);
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ret = PTR_ERR_OR_ZERO(st->gpio_regmap);
316
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if (ret)
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return dev_err_probe(dev, ret, "Unable to init gpio-regmap\n");
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+
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return 0;
320
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}
321
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#else
322
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static int ad7173_gpio_init(struct ad7173_state *st)
323
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{
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return 0;
325
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}
326
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#endif /* CONFIG_GPIOLIB */
327
+
328
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static struct ad7173_state *ad_sigma_delta_to_ad7173(struct ad_sigma_delta *sd)
329
+
{
330
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return container_of(sd, struct ad7173_state, sd);
331
+
}
332
+
333
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static struct ad7173_state *clk_hw_to_ad7173(struct clk_hw *hw)
334
+
{
335
+
return container_of(hw, struct ad7173_state, int_clk_hw);
336
+
}
337
+
338
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static void ad7173_ida_destroy(void *data)
339
+
{
340
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struct ad7173_state *st = data;
341
+
342
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ida_destroy(&st->cfg_slots_status);
343
+
}
344
+
345
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static void ad7173_reset_usage_cnts(struct ad7173_state *st)
346
+
{
347
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memset64(st->config_cnts, 0, st->info->num_configs);
348
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st->config_usage_counter = 0;
349
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}
350
+
351
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static struct ad7173_channel_config *
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ad7173_find_live_config(struct ad7173_state *st, struct ad7173_channel_config *cfg)
353
+
{
354
+
struct ad7173_channel_config *cfg_aux;
355
+
ptrdiff_t cmp_size;
356
+
int i;
357
+
358
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cmp_size = sizeof_field(struct ad7173_channel_config, config_props);
359
+
for (i = 0; i < st->num_channels; i++) {
360
+
cfg_aux = &st->channels[i].cfg;
361
+
362
+
if (cfg_aux->live &&
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!memcmp(&cfg->config_props, &cfg_aux->config_props, cmp_size))
364
+
return cfg_aux;
365
+
}
366
+
return NULL;
367
+
}
368
+
369
+
/* Could be replaced with a generic LRU implementation */
370
+
static int ad7173_free_config_slot_lru(struct ad7173_state *st)
371
+
{
372
+
int i, lru_position = 0;
373
+
374
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for (i = 1; i < st->info->num_configs; i++)
375
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if (st->config_cnts[i] < st->config_cnts[lru_position])
376
+
lru_position = i;
377
+
378
+
for (i = 0; i < st->num_channels; i++)
379
+
if (st->channels[i].cfg.cfg_slot == lru_position)
380
+
st->channels[i].cfg.live = false;
381
+
382
+
ida_free(&st->cfg_slots_status, lru_position);
383
+
return ida_alloc(&st->cfg_slots_status, GFP_KERNEL);
384
+
}
385
+
386
+
/* Could be replaced with a generic LRU implementation */
387
+
static int ad7173_load_config(struct ad7173_state *st,
388
+
struct ad7173_channel_config *cfg)
389
+
{
390
+
unsigned int config;
391
+
int free_cfg_slot, ret;
392
+
393
+
free_cfg_slot = ida_alloc_range(&st->cfg_slots_status, 0,
394
+
st->info->num_configs - 1, GFP_KERNEL);
395
+
if (free_cfg_slot < 0)
396
+
free_cfg_slot = ad7173_free_config_slot_lru(st);
397
+
398
+
cfg->cfg_slot = free_cfg_slot;
399
+
config = FIELD_PREP(AD7173_SETUP_REF_SEL_MASK, cfg->ref_sel);
400
+
401
+
if (cfg->bipolar)
402
+
config |= AD7173_SETUP_BIPOLAR;
403
+
404
+
if (cfg->input_buf)
405
+
config |= AD7173_SETUP_AIN_BUF_MASK;
406
+
407
+
ret = ad_sd_write_reg(&st->sd, AD7173_REG_SETUP(free_cfg_slot), 2, config);
408
+
if (ret)
409
+
return ret;
410
+
411
+
return ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(free_cfg_slot), 2,
412
+
AD7173_FILTER_ODR0_MASK & cfg->odr);
413
+
}
414
+
415
+
static int ad7173_config_channel(struct ad7173_state *st, int addr)
416
+
{
417
+
struct ad7173_channel_config *cfg = &st->channels[addr].cfg;
418
+
struct ad7173_channel_config *live_cfg;
419
+
int ret;
420
+
421
+
if (!cfg->live) {
422
+
live_cfg = ad7173_find_live_config(st, cfg);
423
+
if (live_cfg) {
424
+
cfg->cfg_slot = live_cfg->cfg_slot;
425
+
} else {
426
+
ret = ad7173_load_config(st, cfg);
427
+
if (ret)
428
+
return ret;
429
+
cfg->live = true;
430
+
}
431
+
}
432
+
433
+
if (st->config_usage_counter == U64_MAX)
434
+
ad7173_reset_usage_cnts(st);
435
+
436
+
st->config_usage_counter++;
437
+
st->config_cnts[cfg->cfg_slot] = st->config_usage_counter;
438
+
439
+
return 0;
440
+
}
441
+
442
+
static int ad7173_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
443
+
{
444
+
struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
445
+
unsigned int val;
446
+
int ret;
447
+
448
+
ret = ad7173_config_channel(st, channel);
449
+
if (ret)
450
+
return ret;
451
+
452
+
val = AD7173_CH_ENABLE |
453
+
FIELD_PREP(AD7173_CH_SETUP_SEL_MASK, st->channels[channel].cfg.cfg_slot) |
454
+
st->channels[channel].ain;
455
+
456
+
return ad_sd_write_reg(&st->sd, AD7173_REG_CH(channel), 2, val);
457
+
}
458
+
459
+
static int ad7173_set_mode(struct ad_sigma_delta *sd,
460
+
enum ad_sigma_delta_mode mode)
461
+
{
462
+
struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
463
+
464
+
st->adc_mode &= ~AD7173_ADC_MODE_MODE_MASK;
465
+
st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_MODE_MASK, mode);
466
+
467
+
return ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 2, st->adc_mode);
468
+
}
469
+
470
+
static int ad7173_append_status(struct ad_sigma_delta *sd, bool append)
471
+
{
472
+
struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
473
+
unsigned int interface_mode = st->interface_mode;
474
+
int ret;
475
+
476
+
interface_mode |= AD7173_INTERFACE_DATA_STAT_EN(append);
477
+
ret = ad_sd_write_reg(&st->sd, AD7173_REG_INTERFACE_MODE, 2, interface_mode);
478
+
if (ret)
479
+
return ret;
480
+
481
+
st->interface_mode = interface_mode;
482
+
483
+
return 0;
484
+
}
485
+
486
+
static int ad7173_disable_all(struct ad_sigma_delta *sd)
487
+
{
488
+
struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
489
+
int ret;
490
+
int i;
491
+
492
+
for (i = 0; i < st->num_channels; i++) {
493
+
ret = ad_sd_write_reg(sd, AD7173_REG_CH(i), 2, 0);
494
+
if (ret < 0)
495
+
return ret;
496
+
}
497
+
498
+
return 0;
499
+
}
500
+
501
+
static struct ad_sigma_delta_info ad7173_sigma_delta_info = {
502
+
.set_channel = ad7173_set_channel,
503
+
.append_status = ad7173_append_status,
504
+
.disable_all = ad7173_disable_all,
505
+
.set_mode = ad7173_set_mode,
506
+
.has_registers = true,
507
+
.addr_shift = 0,
508
+
.read_mask = BIT(6),
509
+
.status_ch_mask = GENMASK(3, 0),
510
+
.data_reg = AD7173_REG_DATA,
511
+
};
512
+
513
+
static int ad7173_setup(struct iio_dev *indio_dev)
514
+
{
515
+
struct ad7173_state *st = iio_priv(indio_dev);
516
+
struct device *dev = &st->sd.spi->dev;
517
+
u8 buf[AD7173_RESET_LENGTH];
518
+
unsigned int id;
519
+
int ret;
520
+
521
+
/* reset the serial interface */
522
+
memset(buf, 0xff, AD7173_RESET_LENGTH);
523
+
ret = spi_write_then_read(st->sd.spi, buf, sizeof(buf), NULL, 0);
524
+
if (ret < 0)
525
+
return ret;
526
+
527
+
/* datasheet recommends a delay of at least 500us after reset */
528
+
fsleep(500);
529
+
530
+
ret = ad_sd_read_reg(&st->sd, AD7173_REG_ID, 2, &id);
531
+
if (ret)
532
+
return ret;
533
+
534
+
id &= AD7173_ID_MASK;
535
+
if (id != st->info->id)
536
+
dev_warn(dev, "Unexpected device id: 0x%04X, expected: 0x%04X\n",
537
+
id, st->info->id);
538
+
539
+
st->adc_mode |= AD7173_ADC_MODE_SING_CYC;
540
+
st->interface_mode = 0x0;
541
+
542
+
st->config_usage_counter = 0;
543
+
st->config_cnts = devm_kcalloc(dev, st->info->num_configs,
544
+
sizeof(*st->config_cnts), GFP_KERNEL);
545
+
if (!st->config_cnts)
546
+
return -ENOMEM;
547
+
548
+
/* All channels are enabled by default after a reset */
549
+
return ad7173_disable_all(&st->sd);
550
+
}
551
+
552
+
static unsigned int ad7173_get_ref_voltage_milli(struct ad7173_state *st,
553
+
u8 reference_select)
554
+
{
555
+
int vref;
556
+
557
+
switch (reference_select) {
558
+
case AD7173_SETUP_REF_SEL_EXT_REF:
559
+
vref = regulator_get_voltage(st->regulators[0].consumer);
560
+
break;
561
+
562
+
case AD7173_SETUP_REF_SEL_EXT_REF2:
563
+
vref = regulator_get_voltage(st->regulators[1].consumer);
564
+
break;
565
+
566
+
case AD7173_SETUP_REF_SEL_INT_REF:
567
+
vref = AD7173_VOLTAGE_INT_REF_uV;
568
+
break;
569
+
570
+
case AD7173_SETUP_REF_SEL_AVDD1_AVSS:
571
+
vref = regulator_get_voltage(st->regulators[2].consumer);
572
+
break;
573
+
574
+
default:
575
+
return -EINVAL;
576
+
}
577
+
578
+
if (vref < 0)
579
+
return vref;
580
+
581
+
return vref / (MICRO / MILLI);
582
+
}
583
+
584
+
static int ad7173_read_raw(struct iio_dev *indio_dev,
585
+
struct iio_chan_spec const *chan,
586
+
int *val, int *val2, long info)
587
+
{
588
+
struct ad7173_state *st = iio_priv(indio_dev);
589
+
struct ad7173_channel *ch = &st->channels[chan->address];
590
+
unsigned int reg;
591
+
u64 temp;
592
+
int ret;
593
+
594
+
switch (info) {
595
+
case IIO_CHAN_INFO_RAW:
596
+
ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
597
+
if (ret < 0)
598
+
return ret;
599
+
600
+
/* disable channel after single conversion */
601
+
ret = ad_sd_write_reg(&st->sd, AD7173_REG_CH(chan->address), 2, 0);
602
+
if (ret < 0)
603
+
return ret;
604
+
605
+
return IIO_VAL_INT;
606
+
case IIO_CHAN_INFO_SCALE:
607
+
if (chan->type == IIO_TEMP) {
608
+
temp = AD7173_VOLTAGE_INT_REF_uV * MILLI;
609
+
temp /= AD7173_TEMP_SENSIIVITY_uV_per_C;
610
+
*val = temp;
611
+
*val2 = chan->scan_type.realbits;
612
+
} else {
613
+
*val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel);
614
+
*val2 = chan->scan_type.realbits - !!(ch->cfg.bipolar);
615
+
}
616
+
return IIO_VAL_FRACTIONAL_LOG2;
617
+
case IIO_CHAN_INFO_OFFSET:
618
+
if (chan->type == IIO_TEMP) {
619
+
/* 0 Kelvin -> raw sample */
620
+
temp = -ABSOLUTE_ZERO_MILLICELSIUS;
621
+
temp *= AD7173_TEMP_SENSIIVITY_uV_per_C;
622
+
temp <<= chan->scan_type.realbits;
623
+
temp = DIV_U64_ROUND_CLOSEST(temp,
624
+
AD7173_VOLTAGE_INT_REF_uV *
625
+
MILLI);
626
+
*val = -temp;
627
+
} else {
628
+
*val = -BIT(chan->scan_type.realbits - 1);
629
+
}
630
+
return IIO_VAL_INT;
631
+
case IIO_CHAN_INFO_SAMP_FREQ:
632
+
reg = st->channels[chan->address].cfg.odr;
633
+
634
+
*val = st->info->sinc5_data_rates[reg] / MILLI;
635
+
*val2 = (st->info->sinc5_data_rates[reg] % MILLI) * (MICRO / MILLI);
636
+
637
+
return IIO_VAL_INT_PLUS_MICRO;
638
+
default:
639
+
return -EINVAL;
640
+
}
641
+
}
642
+
643
+
static int ad7173_write_raw(struct iio_dev *indio_dev,
644
+
struct iio_chan_spec const *chan,
645
+
int val, int val2, long info)
646
+
{
647
+
struct ad7173_state *st = iio_priv(indio_dev);
648
+
struct ad7173_channel_config *cfg;
649
+
unsigned int freq, i, reg;
650
+
int ret;
651
+
652
+
ret = iio_device_claim_direct_mode(indio_dev);
653
+
if (ret)
654
+
return ret;
655
+
656
+
switch (info) {
657
+
case IIO_CHAN_INFO_SAMP_FREQ:
658
+
freq = val * MILLI + val2 / MILLI;
659
+
for (i = 0; i < st->info->num_sinc5_data_rates - 1; i++)
660
+
if (freq >= st->info->sinc5_data_rates[i])
661
+
break;
662
+
663
+
cfg = &st->channels[chan->address].cfg;
664
+
cfg->odr = i;
665
+
666
+
if (!cfg->live)
667
+
break;
668
+
669
+
ret = ad_sd_read_reg(&st->sd, AD7173_REG_FILTER(cfg->cfg_slot), 2, ®);
670
+
if (ret)
671
+
break;
672
+
reg &= ~AD7173_FILTER_ODR0_MASK;
673
+
reg |= FIELD_PREP(AD7173_FILTER_ODR0_MASK, i);
674
+
ret = ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(cfg->cfg_slot), 2, reg);
675
+
break;
676
+
677
+
default:
678
+
ret = -EINVAL;
679
+
break;
680
+
}
681
+
682
+
iio_device_release_direct_mode(indio_dev);
683
+
return ret;
684
+
}
685
+
686
+
static int ad7173_update_scan_mode(struct iio_dev *indio_dev,
687
+
const unsigned long *scan_mask)
688
+
{
689
+
struct ad7173_state *st = iio_priv(indio_dev);
690
+
int i, ret;
691
+
692
+
for (i = 0; i < indio_dev->num_channels; i++) {
693
+
if (test_bit(i, scan_mask))
694
+
ret = ad7173_set_channel(&st->sd, i);
695
+
else
696
+
ret = ad_sd_write_reg(&st->sd, AD7173_REG_CH(i), 2, 0);
697
+
if (ret < 0)
698
+
return ret;
699
+
}
700
+
701
+
return 0;
702
+
}
703
+
704
+
static int ad7173_debug_reg_access(struct iio_dev *indio_dev, unsigned int reg,
705
+
unsigned int writeval, unsigned int *readval)
706
+
{
707
+
struct ad7173_state *st = iio_priv(indio_dev);
708
+
u8 reg_size;
709
+
710
+
if (reg == AD7173_REG_COMMS)
711
+
reg_size = 1;
712
+
else if (reg == AD7173_REG_CRC || reg == AD7173_REG_DATA ||
713
+
reg >= AD7173_REG_OFFSET(0))
714
+
reg_size = 3;
715
+
else
716
+
reg_size = 2;
717
+
718
+
if (readval)
719
+
return ad_sd_read_reg(&st->sd, reg, reg_size, readval);
720
+
721
+
return ad_sd_write_reg(&st->sd, reg, reg_size, writeval);
722
+
}
723
+
724
+
static const struct iio_info ad7173_info = {
725
+
.read_raw = &ad7173_read_raw,
726
+
.write_raw = &ad7173_write_raw,
727
+
.debugfs_reg_access = &ad7173_debug_reg_access,
728
+
.validate_trigger = ad_sd_validate_trigger,
729
+
.update_scan_mode = ad7173_update_scan_mode,
730
+
};
731
+
732
+
static const struct iio_chan_spec ad7173_channel_template = {
733
+
.type = IIO_VOLTAGE,
734
+
.indexed = 1,
735
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
736
+
BIT(IIO_CHAN_INFO_SCALE),
737
+
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
738
+
.scan_type = {
739
+
.sign = 'u',
740
+
.realbits = 24,
741
+
.storagebits = 32,
742
+
.endianness = IIO_BE,
743
+
},
744
+
};
745
+
746
+
static const struct iio_chan_spec ad7173_temp_iio_channel_template = {
747
+
.type = IIO_TEMP,
748
+
.indexed = 1,
749
+
.channel = AD7173_AIN_TEMP_POS,
750
+
.channel2 = AD7173_AIN_TEMP_NEG,
751
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
752
+
BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET),
753
+
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
754
+
.scan_type = {
755
+
.sign = 'u',
756
+
.realbits = 24,
757
+
.storagebits = 32,
758
+
.endianness = IIO_BE,
759
+
},
760
+
};
761
+
762
+
static void ad7173_disable_regulators(void *data)
763
+
{
764
+
struct ad7173_state *st = data;
765
+
766
+
regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators);
767
+
}
768
+
769
+
static void ad7173_clk_disable_unprepare(void *clk)
770
+
{
771
+
clk_disable_unprepare(clk);
772
+
}
773
+
774
+
static unsigned long ad7173_sel_clk(struct ad7173_state *st,
775
+
unsigned int clk_sel)
776
+
{
777
+
int ret;
778
+
779
+
st->adc_mode &= !AD7173_ADC_MODE_CLOCKSEL_MASK;
780
+
st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, clk_sel);
781
+
ret = ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 0x2, st->adc_mode);
782
+
783
+
return ret;
784
+
}
785
+
786
+
static unsigned long ad7173_clk_recalc_rate(struct clk_hw *hw,
787
+
unsigned long parent_rate)
788
+
{
789
+
struct ad7173_state *st = clk_hw_to_ad7173(hw);
790
+
791
+
return st->info->clock / HZ_PER_KHZ;
792
+
}
793
+
794
+
static int ad7173_clk_output_is_enabled(struct clk_hw *hw)
795
+
{
796
+
struct ad7173_state *st = clk_hw_to_ad7173(hw);
797
+
u32 clk_sel;
798
+
799
+
clk_sel = FIELD_GET(AD7173_ADC_MODE_CLOCKSEL_MASK, st->adc_mode);
800
+
return clk_sel == AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT;
801
+
}
802
+
803
+
static int ad7173_clk_output_prepare(struct clk_hw *hw)
804
+
{
805
+
struct ad7173_state *st = clk_hw_to_ad7173(hw);
806
+
807
+
return ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT);
808
+
}
809
+
810
+
static void ad7173_clk_output_unprepare(struct clk_hw *hw)
811
+
{
812
+
struct ad7173_state *st = clk_hw_to_ad7173(hw);
813
+
814
+
ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT);
815
+
}
816
+
817
+
static const struct clk_ops ad7173_int_clk_ops = {
818
+
.recalc_rate = ad7173_clk_recalc_rate,
819
+
.is_enabled = ad7173_clk_output_is_enabled,
820
+
.prepare = ad7173_clk_output_prepare,
821
+
.unprepare = ad7173_clk_output_unprepare,
822
+
};
823
+
824
+
static int ad7173_register_clk_provider(struct iio_dev *indio_dev)
825
+
{
826
+
struct ad7173_state *st = iio_priv(indio_dev);
827
+
struct device *dev = indio_dev->dev.parent;
828
+
struct fwnode_handle *fwnode = dev_fwnode(dev);
829
+
struct clk_init_data init = {};
830
+
int ret;
831
+
832
+
if (!IS_ENABLED(CONFIG_COMMON_CLK))
833
+
return 0;
834
+
835
+
init.name = fwnode_get_name(fwnode);
836
+
init.ops = &ad7173_int_clk_ops;
837
+
838
+
st->int_clk_hw.init = &init;
839
+
ret = devm_clk_hw_register(dev, &st->int_clk_hw);
840
+
if (ret)
841
+
return ret;
842
+
843
+
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
844
+
&st->int_clk_hw);
845
+
}
846
+
847
+
static int ad7173_fw_parse_channel_config(struct iio_dev *indio_dev)
848
+
{
849
+
struct ad7173_channel *chans_st_arr, *chan_st_priv;
850
+
struct ad7173_state *st = iio_priv(indio_dev);
851
+
struct device *dev = indio_dev->dev.parent;
852
+
struct iio_chan_spec *chan_arr, *chan;
853
+
unsigned int ain[2], chan_index = 0;
854
+
struct fwnode_handle *child;
855
+
int ref_sel, ret;
856
+
857
+
chan_arr = devm_kcalloc(dev, sizeof(*indio_dev->channels),
858
+
st->num_channels, GFP_KERNEL);
859
+
if (!chan_arr)
860
+
return -ENOMEM;
861
+
862
+
chans_st_arr = devm_kcalloc(dev, st->num_channels, sizeof(*st->channels),
863
+
GFP_KERNEL);
864
+
if (!chans_st_arr)
865
+
return -ENOMEM;
866
+
867
+
indio_dev->channels = chan_arr;
868
+
st->channels = chans_st_arr;
869
+
870
+
if (st->info->has_temp) {
871
+
chan_arr[chan_index] = ad7173_temp_iio_channel_template;
872
+
chan_st_priv = &chans_st_arr[chan_index];
873
+
chan_st_priv->ain =
874
+
AD7173_CH_ADDRESS(chan_arr[chan_index].channel,
875
+
chan_arr[chan_index].channel2);
876
+
chan_st_priv->cfg.bipolar = false;
877
+
chan_st_priv->cfg.input_buf = true;
878
+
chan_st_priv->cfg.ref_sel = AD7173_SETUP_REF_SEL_INT_REF;
879
+
st->adc_mode |= AD7173_ADC_MODE_REF_EN;
880
+
881
+
chan_index++;
882
+
}
883
+
884
+
device_for_each_child_node(dev, child) {
885
+
chan = &chan_arr[chan_index];
886
+
chan_st_priv = &chans_st_arr[chan_index];
887
+
ret = fwnode_property_read_u32_array(child, "diff-channels",
888
+
ain, ARRAY_SIZE(ain));
889
+
if (ret) {
890
+
fwnode_handle_put(child);
891
+
return ret;
892
+
}
893
+
894
+
if (ain[0] >= st->info->num_inputs ||
895
+
ain[1] >= st->info->num_inputs) {
896
+
fwnode_handle_put(child);
897
+
return dev_err_probe(dev, -EINVAL,
898
+
"Input pin number out of range for pair (%d %d).\n",
899
+
ain[0], ain[1]);
900
+
}
901
+
902
+
ret = fwnode_property_match_property_string(child,
903
+
"adi,reference-select",
904
+
ad7173_ref_sel_str,
905
+
ARRAY_SIZE(ad7173_ref_sel_str));
906
+
if (ret < 0)
907
+
ref_sel = AD7173_SETUP_REF_SEL_INT_REF;
908
+
else
909
+
ref_sel = ret;
910
+
911
+
if (ref_sel == AD7173_SETUP_REF_SEL_EXT_REF2 &&
912
+
st->info->id != AD7173_ID) {
913
+
fwnode_handle_put(child);
914
+
return dev_err_probe(dev, -EINVAL,
915
+
"External reference 2 is only available on ad7173-8\n");
916
+
}
917
+
918
+
ret = ad7173_get_ref_voltage_milli(st, ref_sel);
919
+
if (ret < 0) {
920
+
fwnode_handle_put(child);
921
+
return dev_err_probe(dev, ret,
922
+
"Cannot use reference %u\n", ref_sel);
923
+
}
924
+
if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF)
925
+
st->adc_mode |= AD7173_ADC_MODE_REF_EN;
926
+
chan_st_priv->cfg.ref_sel = ref_sel;
927
+
928
+
*chan = ad7173_channel_template;
929
+
chan->address = chan_index;
930
+
chan->scan_index = chan_index;
931
+
chan->channel = ain[0];
932
+
chan->channel2 = ain[1];
933
+
chan->differential = true;
934
+
935
+
chan_st_priv->ain = AD7173_CH_ADDRESS(ain[0], ain[1]);
936
+
chan_st_priv->chan_reg = chan_index;
937
+
chan_st_priv->cfg.input_buf = true;
938
+
chan_st_priv->cfg.odr = 0;
939
+
940
+
chan_st_priv->cfg.bipolar = fwnode_property_read_bool(child, "bipolar");
941
+
if (chan_st_priv->cfg.bipolar)
942
+
chan->info_mask_separate |= BIT(IIO_CHAN_INFO_OFFSET);
943
+
944
+
chan_index++;
945
+
}
946
+
return 0;
947
+
}
948
+
949
+
static int ad7173_fw_parse_device_config(struct iio_dev *indio_dev)
950
+
{
951
+
struct ad7173_state *st = iio_priv(indio_dev);
952
+
struct device *dev = indio_dev->dev.parent;
953
+
unsigned int num_channels;
954
+
int ret;
955
+
956
+
st->regulators[0].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF];
957
+
st->regulators[1].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF2];
958
+
st->regulators[2].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_AVDD1_AVSS];
959
+
960
+
/*
961
+
* If a regulator is not available, it will be set to a dummy regulator.
962
+
* Each channel reference is checked with regulator_get_voltage() before
963
+
* setting attributes so if any channel uses a dummy supply the driver
964
+
* probe will fail.
965
+
*/
966
+
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators),
967
+
st->regulators);
968
+
if (ret)
969
+
return dev_err_probe(dev, ret, "Failed to get regulators\n");
970
+
971
+
ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators);
972
+
if (ret)
973
+
return dev_err_probe(dev, ret, "Failed to enable regulators\n");
974
+
975
+
ret = devm_add_action_or_reset(dev, ad7173_disable_regulators, st);
976
+
if (ret)
977
+
return dev_err_probe(dev, ret,
978
+
"Failed to add regulators disable action\n");
979
+
980
+
ret = device_property_match_property_string(dev, "clock-names",
981
+
ad7173_clk_sel,
982
+
ARRAY_SIZE(ad7173_clk_sel));
983
+
if (ret < 0) {
984
+
st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK,
985
+
AD7173_ADC_MODE_CLOCKSEL_INT);
986
+
ad7173_register_clk_provider(indio_dev);
987
+
} else {
988
+
st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK,
989
+
AD7173_ADC_MODE_CLOCKSEL_EXT + ret);
990
+
st->ext_clk = devm_clk_get(dev, ad7173_clk_sel[ret]);
991
+
if (IS_ERR(st->ext_clk))
992
+
return dev_err_probe(dev, PTR_ERR(st->ext_clk),
993
+
"Failed to get external clock\n");
994
+
995
+
ret = clk_prepare_enable(st->ext_clk);
996
+
if (ret)
997
+
return dev_err_probe(dev, ret,
998
+
"Failed to enable external clock\n");
999
+
1000
+
ret = devm_add_action_or_reset(dev, ad7173_clk_disable_unprepare,
1001
+
st->ext_clk);
1002
+
if (ret)
1003
+
return ret;
1004
+
}
1005
+
1006
+
ret = fwnode_irq_get_byname(dev_fwnode(dev), "rdy");
1007
+
if (ret < 0)
1008
+
return dev_err_probe(dev, ret, "Interrupt 'rdy' is required\n");
1009
+
1010
+
ad7173_sigma_delta_info.irq_line = ret;
1011
+
1012
+
num_channels = device_get_child_node_count(dev);
1013
+
1014
+
if (st->info->has_temp)
1015
+
num_channels++;
1016
+
1017
+
if (num_channels == 0)
1018
+
return dev_err_probe(dev, -ENODATA, "No channels specified\n");
1019
+
indio_dev->num_channels = num_channels;
1020
+
st->num_channels = num_channels;
1021
+
1022
+
return ad7173_fw_parse_channel_config(indio_dev);
1023
+
}
1024
+
1025
+
static int ad7173_probe(struct spi_device *spi)
1026
+
{
1027
+
struct device *dev = &spi->dev;
1028
+
struct ad7173_state *st;
1029
+
struct iio_dev *indio_dev;
1030
+
int ret;
1031
+
1032
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1033
+
if (!indio_dev)
1034
+
return -ENOMEM;
1035
+
1036
+
st = iio_priv(indio_dev);
1037
+
st->info = spi_get_device_match_data(spi);
1038
+
if (!st->info)
1039
+
return -ENODEV;
1040
+
1041
+
ida_init(&st->cfg_slots_status);
1042
+
ret = devm_add_action_or_reset(dev, ad7173_ida_destroy, st);
1043
+
if (ret)
1044
+
return ret;
1045
+
1046
+
indio_dev->name = st->info->name;
1047
+
indio_dev->modes = INDIO_DIRECT_MODE;
1048
+
indio_dev->info = &ad7173_info;
1049
+
1050
+
spi->mode = SPI_MODE_3;
1051
+
spi_setup(spi);
1052
+
1053
+
ad7173_sigma_delta_info.num_slots = st->info->num_configs;
1054
+
ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7173_sigma_delta_info);
1055
+
if (ret)
1056
+
return ret;
1057
+
1058
+
ret = ad7173_fw_parse_device_config(indio_dev);
1059
+
if (ret)
1060
+
return ret;
1061
+
1062
+
ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev);
1063
+
if (ret)
1064
+
return ret;
1065
+
1066
+
ret = ad7173_setup(indio_dev);
1067
+
if (ret)
1068
+
return ret;
1069
+
1070
+
ret = devm_iio_device_register(dev, indio_dev);
1071
+
if (ret)
1072
+
return ret;
1073
+
1074
+
if (IS_ENABLED(CONFIG_GPIOLIB))
1075
+
return ad7173_gpio_init(st);
1076
+
1077
+
return 0;
1078
+
}
1079
+
1080
+
static const struct of_device_id ad7173_of_match[] = {
1081
+
{ .compatible = "adi,ad7172-2",
1082
+
.data = &ad7173_device_info[ID_AD7172_2]},
1083
+
{ .compatible = "adi,ad7173-8",
1084
+
.data = &ad7173_device_info[ID_AD7173_8]},
1085
+
{ .compatible = "adi,ad7175-2",
1086
+
.data = &ad7173_device_info[ID_AD7175_2]},
1087
+
{ .compatible = "adi,ad7176-2",
1088
+
.data = &ad7173_device_info[ID_AD7176_2]},
1089
+
{ }
1090
+
};
1091
+
MODULE_DEVICE_TABLE(of, ad7173_of_match);
1092
+
1093
+
static const struct spi_device_id ad7173_id_table[] = {
1094
+
{ "ad7172-2", (kernel_ulong_t)&ad7173_device_info[ID_AD7172_2]},
1095
+
{ "ad7173-8", (kernel_ulong_t)&ad7173_device_info[ID_AD7173_8]},
1096
+
{ "ad7175-2", (kernel_ulong_t)&ad7173_device_info[ID_AD7175_2]},
1097
+
{ "ad7176-2", (kernel_ulong_t)&ad7173_device_info[ID_AD7176_2]},
1098
+
{ }
1099
+
};
1100
+
MODULE_DEVICE_TABLE(spi, ad7173_id_table);
1101
+
1102
+
static struct spi_driver ad7173_driver = {
1103
+
.driver = {
1104
+
.name = "ad7173",
1105
+
.of_match_table = ad7173_of_match,
1106
+
},
1107
+
.probe = ad7173_probe,
1108
+
.id_table = ad7173_id_table,
1109
+
};
1110
+
module_spi_driver(ad7173_driver);
1111
+
1112
+
MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA);
1113
+
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafo.de>");
1114
+
MODULE_AUTHOR("Dumitru Ceclan <dumitru.ceclan@analog.com>");
1115
+
MODULE_DESCRIPTION("Analog Devices AD7172/AD7173/AD7175/AD7176 ADC driver");
1116
+
MODULE_LICENSE("GPL");