+50

Documentation/devicetree/bindings/hwmon/pmbus/adi,lt3074.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/hwmon/pmbus/adi,lt3074.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Analog Devices LT3074 voltage regulator 8 8 + 9 9 + maintainers: 10 10 + - Cedric Encarnacion <cedricjustine.encarnacion@analog.com> 11 11 + 12 12 + description: | 13 13 + The LT3074 is a low voltage, ultra-low noise and ultra-fast transient 14 14 + response linear regulator. It allows telemetry for input/output voltage, 15 15 + output current and temperature through the PMBus serial interface. 16 16 + 17 17 + Datasheet: 18 18 + https://www.analog.com/en/products/lt3074.html 19 19 + 20 20 + allOf: 21 21 + - $ref: /schemas/regulator/regulator.yaml# 22 22 + 23 23 + properties: 24 24 + compatible: 25 25 + enum: 26 26 + - adi,lt3074 27 27 + 28 28 + reg: 29 29 + maxItems: 1 30 30 + 31 31 + required: 32 32 + - compatible 33 33 + - reg 34 34 + 35 35 + unevaluatedProperties: false 36 36 + 37 37 + examples: 38 38 + - | 39 39 + i2c { 40 40 + #address-cells = <1>; 41 41 + #size-cells = <0>; 42 42 + 43 43 + regulator@6d { 44 44 + compatible = "adi,lt3074"; 45 45 + reg = <0x6d>; 46 46 + regulator-name = "vout"; 47 47 + regulator-max-microvolt = <1250000>; 48 48 + regulator-min-microvolt = <1150000>; 49 49 + }; 50 50 + };

+74

Documentation/devicetree/bindings/hwmon/pmbus/mps,mpq8785.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/hwmon/pmbus/mps,mpq8785.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Monolithic Power Systems Multiphase Voltage Regulators with PMBus 8 8 + 9 9 + maintainers: 10 10 + - Charles Hsu <ythsu0511@gmail.com> 11 11 + 12 12 + description: 13 13 + Monolithic Power Systems digital multiphase voltage regulators with PMBus. 14 14 + 15 15 + properties: 16 16 + compatible: 17 17 + enum: 18 18 + - mps,mpm3695 19 19 + - mps,mpm3695-25 20 20 + - mps,mpm82504 21 21 + - mps,mpq8785 22 22 + 23 23 + reg: 24 24 + maxItems: 1 25 25 + 26 26 + mps,vout-fb-divider-ratio-permille: 27 27 + description: 28 28 + The feedback resistor divider ratio, expressed in permille 29 29 + (Vfb / Vout * 1000). This value is written to the PMBUS_VOUT_SCALE_LOOP 30 30 + register and is required for correct output voltage presentation. 31 31 + $ref: /schemas/types.yaml#/definitions/uint32 32 32 + minimum: 1 33 33 + maximum: 4095 34 34 + default: 706 35 35 + 36 36 + required: 37 37 + - compatible 38 38 + - reg 39 39 + 40 40 + allOf: 41 41 + - if: 42 42 + properties: 43 43 + compatible: 44 44 + enum: 45 45 + - mps,mpm3695 46 46 + - mps,mpm82504 47 47 + then: 48 48 + properties: 49 49 + mps,vout-fb-divider-ratio-permille: 50 50 + maximum: 1023 51 51 + 52 52 + - if: 53 53 + properties: 54 54 + compatible: 55 55 + const: mps,mpq8785 56 56 + then: 57 57 + properties: 58 58 + mps,vout-fb-divider-ratio-permille: 59 59 + maximum: 2047 60 60 + 61 61 + additionalProperties: false 62 62 + 63 63 + examples: 64 64 + - | 65 65 + i2c { 66 66 + #address-cells = <1>; 67 67 + #size-cells = <0>; 68 68 + 69 69 + pmic@30 { 70 70 + compatible = "mps,mpm82504"; 71 71 + reg = <0x30>; 72 72 + mps,vout-fb-divider-ratio-permille = <600>; 73 73 + }; 74 74 + };

+5 -1

Documentation/devicetree/bindings/hwmon/sophgo,sg2042-hwmon-mcu.yaml

reviewed

··· 11 11 12 12 properties: 13 13 compatible: 14 14 - const: sophgo,sg2042-hwmon-mcu 14 14 + oneOf: 15 15 + - items: 16 16 + - const: sophgo,sg2044-hwmon-mcu 17 17 + - const: sophgo,sg2042-hwmon-mcu 18 18 + - const: sophgo,sg2042-hwmon-mcu 15 19 16 20 reg: 17 21 maxItems: 1

+17 -1

Documentation/devicetree/bindings/hwmon/ti,amc6821.yaml

reviewed

··· 28 28 i2c-mux: 29 29 type: object 30 30 31 31 + fan: 32 32 + $ref: fan-common.yaml# 33 33 + unevaluatedProperties: false 34 34 + 35 35 + "#pwm-cells": 36 36 + const: 2 37 37 + description: | 38 38 + Number of cells in a PWM specifier. 39 39 + - cell 0: PWM period in nanoseconds 40 40 + - cell 1: PWM polarity: 0 or PWM_POLARITY_INVERTED 41 41 + 31 42 required: 32 43 - compatible 33 44 - reg ··· 61 50 #address-cells = <1>; 62 51 #size-cells = <0>; 63 52 64 64 - fan@18 { 53 53 + fan_controller: fan@18 { 65 54 compatible = "ti,amc6821"; 66 55 reg = <0x18>; 56 56 + #pwm-cells = <2>; 57 57 + 58 58 + fan { 59 59 + pwms = <&fan_controller 40000 0>; 60 60 + }; 67 61 }; 68 62 }; 69 63

+5

Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml

reviewed

··· 19 19 properties: 20 20 compatible: 21 21 enum: 22 22 + - silergy,sq52206 22 23 - silergy,sy24655 23 24 - ti,ina209 24 25 - ti,ina219 ··· 58 57 value of 1 maps to ADCRANGE=1 where no gain divisor is applied to the 59 58 shunt voltage, and a value of 4 maps to ADCRANGE=0 such that a wider 60 59 voltage range is used. 60 60 + 61 61 + For SQ52206,the shunt-gain value 1 mapps to ADCRANGE=10/11, the value 2 62 62 + mapps to ADCRANGE=01, and the value 4 mapps to ADCRANGE=00. 61 63 62 64 The default value is device dependent, and is defined by the reset value 63 65 of PGA/ADCRANGE in the respective configuration registers. ··· 101 97 compatible: 102 98 contains: 103 99 enum: 100 100 + - silergy,sq52206 104 101 - silergy,sy24655 105 102 - ti,ina209 106 103 - ti,ina219

+4

Documentation/devicetree/bindings/hwmon/ti,tmp102.yaml

reviewed

··· 23 23 "#thermal-sensor-cells": 24 24 const: 1 25 25 26 26 + vcc-supply: 27 27 + description: Power supply for tmp102 28 28 + 26 29 required: 27 30 - compatible 28 31 - reg ··· 45 42 reg = <0x48>; 46 43 interrupt-parent = <&gpio7>; 47 44 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 45 45 + vcc-supply = <&supply>; 48 46 #thermal-sensor-cells = <1>; 49 47 }; 50 48 };

-2

Documentation/devicetree/bindings/trivial-devices.yaml

reviewed

··· 295 295 - mps,mp5990 296 296 # Monolithic Power Systems Inc. digital step-down converter mp9941 297 297 - mps,mp9941 298 298 - # Monolithic Power Systems Inc. synchronous step-down converter mpq8785 299 299 - - mps,mpq8785 300 298 # Temperature sensor with integrated fan control 301 299 - national,lm63 302 300 # Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor

+26 -3

Documentation/hwmon/acpi_power_meter.rst

reviewed

··· 37 37 contains symlinks to the devices that this meter measures. 38 38 39 39 Some computers have the ability to enforce a power cap in hardware. If this is 40 40 - the case, the `power[1-*]_cap` and related sysfs files will appear. When the 41 41 - average power consumption exceeds the cap, an ACPI event will be broadcast on 42 42 - the netlink event socket and a poll notification will be sent to the 40 40 + the case, the `power[1-*]_cap` and related sysfs files will appear. 41 41 + For information on enabling the power cap feature, refer to the description 42 42 + of the "force_on_cap" option in the "Module Parameters" chapter. 43 43 + To use the power cap feature properly, you need to set appropriate value 44 44 + (in microWatts) to the `power[1-*]_cap` sysfs files. 45 45 + The value must be within the range between the minimum value at `power[1-]_cap_min` 46 46 + and the maximum value at `power[1-]_cap_max (both in microWatts)`. 47 47 + 48 48 + When the average power consumption exceeds the cap, an ACPI event will be 49 49 + broadcast on the netlink event socket and a poll notification will be sent to the 43 50 appropriate `power[1-*]_alarm` file to indicate that capping has begun, and the 44 51 hardware has taken action to reduce power consumption. Most likely this will 45 52 result in reduced performance. ··· 59 52 `power[1-*]_cap` will be notified if the firmware changes the power cap. 60 53 `power[1-*]_interval` will be notified if the firmware changes the averaging 61 54 interval. 55 55 + 56 56 + Module Parameters 57 57 + ----------------- 58 58 + 59 59 + * force_cap_on: bool 60 60 + Forcefully enable the power capping feature to specify 61 61 + the upper limit of the system's power consumption. 62 62 + 63 63 + By default, the driver's power capping feature is only 64 64 + enabled on IBM products. 65 65 + Therefore, on other systems that support power capping, 66 66 + you will need to use the option to enable it. 67 67 + 68 68 + Note: power capping is potentially unsafe feature. 69 69 + Please check the platform specifications to make sure 70 70 + that capping is supported before using this option.

+2

Documentation/hwmon/asus_ec_sensors.rst

reviewed

··· 4 4 ================================= 5 5 6 6 Supported boards: 7 7 + * MAXIMUS VI HERO 7 8 * PRIME X470-PRO 8 9 * PRIME X570-PRO 9 10 * PRIME X670E-PRO WIFI ··· 21 20 * ROG CROSSHAIR X670E GENE 22 21 * ROG MAXIMUS XI HERO 23 22 * ROG MAXIMUS XI HERO (WI-FI) 23 23 + * ROG MAXIMUS Z690 FORMULA 24 24 * ROG STRIX B550-E GAMING 25 25 * ROG STRIX B550-I GAMING 26 26 * ROG STRIX X570-E GAMING

+15

Documentation/hwmon/ina238.rst

reviewed

··· 14 14 Datasheet: 15 15 https://www.ti.com/lit/gpn/ina238 16 16 17 17 + * Silergy SQ52206 18 18 + 19 19 + Prefix: 'SQ52206' 20 20 + 21 21 + Addresses: I2C 0x40 - 0x4f 22 22 + 17 23 Author: Nathan Rossi <nathan.rossi@digi.com> 18 24 19 25 Description ··· 59 53 temp1_input Die temperature measurement (mC) 60 54 temp1_max Maximum die temperature threshold (mC) 61 55 temp1_max_alarm Maximum die temperature alarm 56 56 + ======================= ======================================================= 57 57 + 58 58 + Additional sysfs entries for sq52206 59 59 + ------------------------------------ 60 60 + 61 61 + ======================= ======================================================= 62 62 + energy1_input Energy measurement (mJ) 63 63 + 64 64 + power1_input_highest Peak Power (uW) 62 65 ======================= =======================================================

+4

Documentation/hwmon/index.rst

reviewed

··· 106 106 jc42 107 107 k10temp 108 108 k8temp 109 109 + kbatt 110 110 + kfan 109 111 lan966x 110 112 lineage-pem 111 113 lm25066 ··· 127 125 lm95234 128 126 lm95245 129 127 lochnagar 128 128 + lt3074 130 129 lt7182s 131 130 ltc2992 132 131 ltc2945 ··· 164 161 max6639 165 162 max6650 166 163 max6697 164 164 + max77705 167 165 max8688 168 166 mc13783-adc 169 167 mc34vr500

+60

Documentation/hwmon/kbatt.rst

reviewed

··· 1 1 + .. SPDX-License-Identifier: GPL-2.0 2 2 + 3 3 + Kernel driver kbatt 4 4 + =================== 5 5 + 6 6 + Supported chips: 7 7 + 8 8 + * KEBA battery monitoring controller (IP core in FPGA) 9 9 + 10 10 + Prefix: 'kbatt' 11 11 + 12 12 + Authors: 13 13 + 14 14 + Gerhard Engleder <eg@keba.com> 15 15 + Petar Bojanic <boja@keba.com> 16 16 + 17 17 + Description 18 18 + ----------- 19 19 + 20 20 + The KEBA battery monitoring controller is an IP core for FPGAs, which 21 21 + monitors the health of a coin cell battery. The coin cell battery is 22 22 + typically used to supply the RTC during power off to keep the current 23 23 + time. E.g., the CP500 FPGA includes this IP core to monitor the coin cell 24 24 + battery of PLCs and the corresponding cp500 driver creates an auxiliary 25 25 + device for the kbatt driver. 26 26 + 27 27 + This driver provides information about the coin cell battery health to 28 28 + user space. Actually the user space shall be informed that the coin cell 29 29 + battery is nearly empty and needs to be replaced. 30 30 + 31 31 + The coin cell battery must be tested actively to get to know if its nearly 32 32 + empty or not. Therefore, a load is put on the coin cell battery and the 33 33 + resulting voltage is evaluated. This evaluation is done by some hard wired 34 34 + analog logic, which compares the voltage to a defined limit. If the 35 35 + voltage is above the limit, then the coin cell battery is assumed to be 36 36 + ok. If the voltage is below the limit, then the coin cell battery is 37 37 + nearly empty (or broken, removed, ...) and shall be replaced by a new one. 38 38 + The KEBA battery monitoring controller allows to start the test of the 39 39 + coin cell battery and to get the result if the voltage is above or below 40 40 + the limit. The actual voltage is not available. Only the information if 41 41 + the voltage is below a limit is available. 42 42 + 43 43 + The test load, which is put on the coin cell battery for the health check, 44 44 + is similar to the load during power off. Therefore, the lifetime of the 45 45 + coin cell battery is reduced directly by the duration of each test. To 46 46 + limit the negative impact to the lifetime the test is limited to at most 47 47 + once every 10 seconds. The test load is put on the coin cell battery for 48 48 + 100ms. Thus, in worst case the coin cell battery lifetime is reduced by 49 49 + 1% of the uptime or 3.65 days per year. As the coin cell battery lasts 50 50 + multiple years, this lifetime reduction negligible. 51 51 + 52 52 + This driver only provides a single alarm attribute, which is raised when 53 53 + the coin cell battery is nearly empty. 54 54 + 55 55 + ====================== ==== =================================================== 56 56 + Attribute R/W Contents 57 57 + ====================== ==== =================================================== 58 58 + in0_min_alarm R voltage of coin cell battery under load is below 59 59 + limit 60 60 + ====================== ==== ===================================================

+39

Documentation/hwmon/kfan.rst

reviewed

··· 1 1 + .. SPDX-License-Identifier: GPL-2.0 2 2 + 3 3 + Kernel driver kfan 4 4 + ================== 5 5 + 6 6 + Supported chips: 7 7 + 8 8 + * KEBA fan controller (IP core in FPGA) 9 9 + 10 10 + Prefix: 'kfan' 11 11 + 12 12 + Authors: 13 13 + 14 14 + Gerhard Engleder <eg@keba.com> 15 15 + Petar Bojanic <boja@keba.com> 16 16 + 17 17 + Description 18 18 + ----------- 19 19 + 20 20 + The KEBA fan controller is an IP core for FPGAs, which monitors the health 21 21 + and controls the speed of a fan. The fan is typically used to cool the CPU 22 22 + and the whole device. E.g., the CP500 FPGA includes this IP core to monitor 23 23 + and control the fan of PLCs and the corresponding cp500 driver creates an 24 24 + auxiliary device for the kfan driver. 25 25 + 26 26 + This driver provides information about the fan health to user space. 27 27 + The user space shall be informed if the fan is removed or blocked. 28 28 + Additionally, the speed in RPM is reported for fans with tacho signal. 29 29 + 30 30 + For fan control PWM is supported. For PWM 255 equals 100%. None-regulable 31 31 + fans can be turned on with PWM 255 and turned off with PWM 0. 32 32 + 33 33 + ====================== ==== =================================================== 34 34 + Attribute R/W Contents 35 35 + ====================== ==== =================================================== 36 36 + fan1_fault R Fan fault 37 37 + fan1_input R Fan tachometer input (in RPM) 38 38 + pwm1 RW Fan target duty cycle (0..255) 39 39 + ====================== ==== ===================================================

+72

Documentation/hwmon/lt3074.rst

reviewed

··· 1 1 + .. SPDX-License-Identifier: GPL-2.0 2 2 + 3 3 + Kernel driver lt3074 4 4 + ==================== 5 5 + 6 6 + Supported chips: 7 7 + 8 8 + * Analog Devices LT3074 9 9 + 10 10 + Prefix: 'lt3074' 11 11 + 12 12 + Addresses scanned: - 13 13 + 14 14 + Datasheet: https://www.analog.com/en/products/lt3074.html 15 15 + 16 16 + Authors: Cedric Encarnacion <cedricjustine.encarnacion@analog.com> 17 17 + 18 18 + 19 19 + Description 20 20 + ----------- 21 21 + 22 22 + This driver supports hardware monitoring for Analog Devices LT3074 Linear 23 23 + Regulator with PMBus interface. 24 24 + 25 25 + The LT3074 is a low voltage, ultra-low noise and ultra-fast transient 26 26 + response linear regulator with PMBus serial interface. PMBus telemetry 27 27 + feature provides information regarding the output voltage and current, 28 28 + input voltage, bias voltage and die temperature. 29 29 + 30 30 + The driver is a client driver to the core PMBus driver. Please see 31 31 + Documentation/hwmon/pmbus.rst for details on PMBus client drivers. 32 32 + 33 33 + Usage Notes 34 34 + ----------- 35 35 + 36 36 + This driver does not auto-detect devices. You will have to instantiate 37 37 + the devices explicitly. Please see Documentation/i2c/instantiating-devices.rst 38 38 + for details. 39 39 + 40 40 + Platform data support 41 41 + --------------------- 42 42 + 43 43 + The driver supports standard PMBus driver platform data. 44 44 + 45 45 + Sysfs entries 46 46 + ------------- 47 47 + 48 48 + ======================= ======================================================= 49 49 + in1_label "vin" 50 50 + in1_input Measured input voltage 51 51 + in1_max Input overvoltage warning limit 52 52 + in1_max_alarm Input overvoltage warning status 53 53 + in1_min Input undervoltage warning limit 54 54 + in1_min_alarm Input undervoltage warning status 55 55 + in2_label "vmon" 56 56 + in2_input Measured bias voltage 57 57 + in2_max Bias overvoltage warning limit 58 58 + in2_min Bias undervoltage warning limit 59 59 + in3_label "vout1" 60 60 + in3_input Measured output voltage 61 61 + in3_max Output overvoltage warning limit 62 62 + in3_max_alarm Output overvoltage warning status 63 63 + in3_min Output undervoltage warning limit 64 64 + in3_min_alarm Output undervoltage warning status 65 65 + curr1_label "iout1" 66 66 + curr1_input Measured output current. 67 67 + curr1_crit Output overcurrent fault limit 68 68 + curr1_crit_alarm Output overcurrent fault status 69 69 + temp1_input Measured temperature 70 70 + temp1_max Maximum temperature limit 71 71 + temp1_max_alarm Overtemperature warning status 72 72 + ======================= =======================================================

+22 -8

Documentation/hwmon/max34440.rst

reviewed

··· 3 3 4 4 Supported chips: 5 5 6 6 + * ADI ADPM12160 7 7 + 8 8 + Prefixes: 'adpm12160' 9 9 + 10 10 + Addresses scanned: - 11 11 + 12 12 + Datasheet: - 13 13 + 6 14 * Maxim MAX34440 7 15 8 16 Prefixes: 'max34440' ··· 75 67 Description 76 68 ----------- 77 69 78 78 - This driver supports hardware monitoring for Maxim MAX34440 PMBus 6-Channel 79 79 - Power-Supply Manager, MAX34441 PMBus 5-Channel Power-Supply Manager 80 80 - and Intelligent Fan Controller, and MAX34446 PMBus Power-Supply Data Logger. 81 81 - It also supports the MAX34451, MAX34460, and MAX34461 PMBus Voltage Monitor & 82 82 - Sequencers. The MAX34451 supports monitoring voltage or current of 12 channels 83 83 - based on GIN pins. The MAX34460 supports 12 voltage channels, and the MAX34461 84 84 - supports 16 voltage channels. 70 70 + This driver supports multiple devices: hardware monitoring for Maxim MAX34440 71 71 + PMBus 6-Channel Power-Supply Manager, MAX34441 PMBus 5-Channel Power-Supply 72 72 + Manager and Intelligent Fan Controller, and MAX34446 PMBus Power-Supply Data 73 73 + Logger; PMBus Voltage Monitor and Sequencers for MAX34451, MAX34460, and 74 74 + MAX34461; PMBus DC/DC Power Module ADPM12160. The MAX34451 supports monitoring 75 75 + voltage or current of 12 channels based on GIN pins. The MAX34460 supports 12 76 76 + voltage channels, and the MAX34461 supports 16 voltage channels. The ADPM1260 77 77 + also monitors both input and output of voltage and current. 85 78 86 79 The driver is a client driver to the core PMBus driver. Please see 87 80 Documentation/hwmon/pmbus.rst for details on PMBus client drivers. ··· 137 128 in[1-6]_reset_history Write any value to reset history. 138 129 ======================= ======================================================= 139 130 140 140 - .. note:: MAX34446 only supports in[1-4]. 131 131 + .. note:: 132 132 + 133 133 + - MAX34446 only supports in[1-4]. 134 134 + - ADPM12160 only supports in[1-2]. Label is "vin1" and "vout1" respectively. 141 135 142 136 Curr 143 137 ~~~~ ··· 162 150 163 151 - in6 and curr6 attributes only exist for MAX34440. 164 152 - MAX34446 only supports curr[1-4]. 153 153 + - For ADPM12160, curr[1] is "iin1" and curr[2-6] are "iout[1-5]. 165 154 166 155 Power 167 156 ~~~~~ ··· 198 185 .. note:: 199 186 - temp7 and temp8 attributes only exist for MAX34440. 200 187 - MAX34446 only supports temp[1-3]. 188 188 + - ADPM12160 only supports temp[1]. 201 189 202 190 203 191 .. note::

+39

Documentation/hwmon/max77705.rst

reviewed

··· 1 1 + .. SPDX-License-Identifier: GPL-2.0 2 2 + 3 3 + Kernel driver max77705 4 4 + ====================== 5 5 + 6 6 + Supported chips: 7 7 + 8 8 + * Maxim Integrated MAX77705 9 9 + 10 10 + Prefix: 'max77705' 11 11 + 12 12 + Addresses scanned: none 13 13 + 14 14 + Datasheet: Not available 15 15 + 16 16 + Authors: 17 17 + - Dzmitry Sankouski <dsankouski@gmail.com> 18 18 + 19 19 + Description 20 20 + ----------- 21 21 + 22 22 + The MAX77705 PMIC provides current and voltage measurements besides fuelgauge: 23 23 + - chip input current 24 24 + - system bus current and voltage 25 25 + - VBYP voltage 26 26 + 27 27 + Sysfs Attributes 28 28 + ---------------- 29 29 + 30 30 + ================= ======================================== 31 31 + in1_label "vbyp" 32 32 + in1_input Measured chip vbyp voltage 33 33 + in2_label "vsys" 34 34 + in2_input Measured chip system bus voltage 35 35 + curr1_label "iin" 36 36 + curr1_input Measured chip input current. 37 37 + curr2_label "isys" 38 38 + curr2_input Measured chip system bus current. 39 39 + ================= ========================================

+21 -6

Documentation/hwmon/mpq8785.rst

reviewed

··· 5 5 6 6 Supported chips: 7 7 8 8 + * MPS MPM3695 family 9 9 + * MPS MPM82504 8 10 * MPS MPQ8785 9 11 10 12 Prefix: 'mpq8785' ··· 15 13 16 14 Description 17 15 ----------- 16 16 + 17 17 + The MPM3695 family is a scalable, ultra-thin, fully integrated power module with 18 18 + a PMBus interface. It offers a complete power solution that achieves up to 19 19 + 10A (-10 variant), 20A (-25 variant), 25A (-20 variant), 100A (-100 variant) 20 20 + of output current with excellent load and line regulation across a wide input 21 21 + voltage range. It operates at high efficiency over a wide load range, and can 22 22 + be parallled to deliver higher current. Variants -10,-20 and -100 have different 23 23 + voltage scale configuration register range (10 bits) than -25 version (11 bits). 24 24 + 25 25 + The MPM82504 is a quad 25A, scalable, fully integrated power module with a PMBus 26 26 + interface. The device offers a complete power solution that achieves up to 25A 27 27 + per output channel. The MPM82504 has four output channels that can be paralleled 28 28 + to provide 50A, 75A, or 100A of output current for flexible configurations. 29 29 + The device can also operate in parallel with the MPM3695-100 and additional 30 30 + MPM82504 devices to provide a higher output current. The MPM82504 operates 31 31 + at high efficiency across a wide load range. 18 32 19 33 The MPQ8785 is a fully integrated, PMBus-compatible, high-frequency, synchronous 20 34 buck converter. The MPQ8785 offers a very compact solution that achieves up to ··· 41 23 The PMBus interface provides converter configurations and key parameters 42 24 monitoring. 43 25 44 44 - The MPQ8785 adopts MPS's proprietary multi-phase digital constant-on-time (MCOT) 26 26 + The devices adopts MPS's proprietary multi-phase digital constant-on-time (MCOT) 45 27 control, which provides fast transient response and eases loop stabilization. 46 46 - The MCOT scheme also allows multiple MPQ8785 devices to be connected in parallel 47 47 - with excellent current sharing and phase interleaving for high-current 28 28 + The MCOT scheme also allows multiple devices or channels to be connected in 29 29 + parallel with excellent current sharing and phase interleaving for high-current 48 30 applications. 49 31 50 32 Fully integrated protection features include over-current protection (OCP), 51 33 over-voltage protection (OVP), under-voltage protection (UVP), and 52 34 over-temperature protection (OTP). 53 53 - 54 54 - The MPQ8785 requires a minimal number of readily available, standard external 55 55 - components, and is available in a TLGA (5mmx6mm) package. 56 35 57 36 Device compliant with: 58 37

+16

MAINTAINERS

reviewed

··· 14156 14156 S: Maintained 14157 14157 F: drivers/scsi/sym53c8xx_2/ 14158 14158 14159 14159 + LT3074 HARDWARE MONITOR DRIVER 14160 14160 + M: Cedric Encarnacion <cedricjustine.encarnacion@analog.com> 14161 14161 + L: linux-hwmon@vger.kernel.org 14162 14162 + S: Supported 14163 14163 + W: https://ez.analog.com/linux-software-drivers 14164 14164 + F: Documentation/devicetree/bindings/hwmon/pmbus/adi,lt3074.yaml 14165 14165 + F: Documentation/hwmon/lt3074.rst 14166 14166 + F: drivers/hwmon/pmbus/lt3074.c 14167 14167 + 14159 14168 LTC1660 DAC DRIVER 14160 14169 M: Marcus Folkesson <marcus.folkesson@gmail.com> 14161 14170 L: linux-iio@vger.kernel.org ··· 18785 18776 S: Maintained 18786 18777 F: Documentation/hwmon/pc87427.rst 18787 18778 F: drivers/hwmon/pc87427.c 18779 18779 + 18780 18780 + MAX77705 HARDWARE MONITORING DRIVER 18781 18781 + M: Dzmitry Sankouski <dsankouski@gmail.com> 18782 18782 + L: linux-hwmon@vger.kernel.org 18783 18783 + S: Maintained 18784 18784 + F: Documentation/hwmon/max77705.rst 18785 18785 + F: drivers/hwmon/max77705-hwmon.c 18788 18786 18789 18787 PCA9532 LED DRIVER 18790 18788 M: Riku Voipio <riku.voipio@iki.fi>

+29

drivers/hwmon/Kconfig

reviewed

··· 335 335 This driver can also be built as a module. If so, the module 336 336 will be called k10temp. 337 337 338 338 + config SENSORS_KBATT 339 339 + tristate "KEBA battery controller support" 340 340 + depends on KEBA_CP500 341 341 + help 342 342 + This driver supports the battery monitoring controller found in 343 343 + KEBA system FPGA devices. 344 344 + 345 345 + This driver can also be built as a module. If so, the module 346 346 + will be called kbatt. 347 347 + 348 348 + config SENSORS_KFAN 349 349 + tristate "KEBA fan controller support" 350 350 + depends on KEBA_CP500 351 351 + help 352 352 + This driver supports the fan controller found in KEBA system 353 353 + FPGA devices. 354 354 + 355 355 + This driver can also be built as a module. If so, the module 356 356 + will be called kfan. 357 357 + 338 358 config SENSORS_FAM15H_POWER 339 359 tristate "AMD Family 15h processor power" 340 360 depends on X86 && PCI && CPU_SUP_AMD ··· 1327 1307 1328 1308 This driver can also be built as a module. If so, the module 1329 1309 will be called max31790. 1310 1310 + 1311 1311 + config SENSORS_MAX77705 1312 1312 + tristate "MAX77705 current and voltage sensor" 1313 1313 + depends on MFD_MAX77705 1314 1314 + help 1315 1315 + If you say yes here you get support for MAX77705 sensors connected with I2C. 1316 1316 + 1317 1317 + This driver can also be built as a module. If so, the module 1318 1318 + will be called max77705-hwmon. 1330 1319 1331 1320 config SENSORS_MC34VR500 1332 1321 tristate "NXP MC34VR500 hardware monitoring driver"

+3

drivers/hwmon/Makefile

reviewed

··· 110 110 obj-$(CONFIG_SENSORS_JC42) += jc42.o 111 111 obj-$(CONFIG_SENSORS_K8TEMP) += k8temp.o 112 112 obj-$(CONFIG_SENSORS_K10TEMP) += k10temp.o 113 113 + obj-$(CONFIG_SENSORS_KBATT) += kbatt.o 114 114 + obj-$(CONFIG_SENSORS_KFAN) += kfan.o 113 115 obj-$(CONFIG_SENSORS_LAN966X) += lan966x-hwmon.o 114 116 obj-$(CONFIG_SENSORS_LENOVO_EC) += lenovo-ec-sensors.o 115 117 obj-$(CONFIG_SENSORS_LINEAGE) += lineage-pem.o ··· 163 161 obj-$(CONFIG_SENSORS_MAX6697) += max6697.o 164 162 obj-$(CONFIG_SENSORS_MAX31790) += max31790.o 165 163 obj-$(CONFIG_MAX31827) += max31827.o 164 164 + obj-$(CONFIG_SENSORS_MAX77705) += max77705-hwmon.o 166 165 obj-$(CONFIG_SENSORS_MC13783_ADC)+= mc13783-adc.o 167 166 obj-$(CONFIG_SENSORS_MC34VR500) += mc34vr500.o 168 167 obj-$(CONFIG_SENSORS_MCP3021) += mcp3021.o

+8 -8

drivers/hwmon/aht10.c

reviewed

··· 94 94 unsigned int meas_size; 95 95 }; 96 96 97 97 - /** 97 97 + /* 98 98 * aht10_init() - Initialize an AHT10/AHT20 chip 99 99 * @data: the data associated with this AHT10/AHT20 chip 100 100 * Return: 0 if successful, 1 if not ··· 124 124 return 0; 125 125 } 126 126 127 127 - /** 127 127 + /* 128 128 * aht10_polltime_expired() - check if the minimum poll interval has 129 129 * expired 130 130 * @data: the data containing the time to compare ··· 140 140 141 141 DECLARE_CRC8_TABLE(crc8_table); 142 142 143 143 - /** 143 143 + /* 144 144 * crc8_check() - check crc of the sensor's measurements 145 145 * @raw_data: data frame received from sensor(including crc as the last byte) 146 146 * @count: size of the data frame ··· 155 155 return crc8(crc8_table, raw_data, count, CRC8_INIT_VALUE); 156 156 } 157 157 158 158 - /** 158 158 + /* 159 159 * aht10_read_values() - read and parse the raw data from the AHT10/AHT20 160 160 * @data: the struct aht10_data to use for the lock 161 161 * Return: 0 if successful, 1 if not ··· 214 214 return 0; 215 215 } 216 216 217 217 - /** 217 217 + /* 218 218 * aht10_interval_write() - store the given minimum poll interval. 219 219 * Return: 0 on success, -EINVAL if a value lower than the 220 220 * AHT10_MIN_POLL_INTERVAL is given ··· 226 226 return 0; 227 227 } 228 228 229 229 - /** 229 229 + /* 230 230 * aht10_interval_read() - read the minimum poll interval 231 231 * in milliseconds 232 232 */ ··· 237 237 return 0; 238 238 } 239 239 240 240 - /** 240 240 + /* 241 241 * aht10_temperature1_read() - read the temperature in millidegrees 242 242 */ 243 243 static int aht10_temperature1_read(struct aht10_data *data, long *val) ··· 252 252 return 0; 253 253 } 254 254 255 255 - /** 255 255 + /* 256 256 * aht10_humidity1_read() - read the relative humidity in millipercent 257 257 */ 258 258 static int aht10_humidity1_read(struct aht10_data *data, long *val)

+45 -5

drivers/hwmon/amc6821.c

reviewed

··· 23 23 #include <linux/module.h> 24 24 #include <linux/mutex.h> 25 25 #include <linux/of_platform.h> 26 26 + #include <linux/pwm.h> 26 27 #include <linux/regmap.h> 27 28 #include <linux/slab.h> 29 29 + 30 30 + #include <dt-bindings/pwm/pwm.h> 28 31 29 32 /* 30 33 * Addresses to scan. ··· 40 37 * Insmod parameters 41 38 */ 42 39 43 43 - static int pwminv; /*Inverted PWM output. */ 40 40 + static int pwminv = -1; /*Inverted PWM output. */ 44 41 module_param(pwminv, int, 0444); 45 42 46 43 static int init = 1; /*Power-on initialization.*/ ··· 848 845 return 0; 849 846 } 850 847 851 851 - static int amc6821_init_client(struct amc6821_data *data) 848 848 + static enum pwm_polarity amc6821_pwm_polarity(struct i2c_client *client) 849 849 + { 850 850 + enum pwm_polarity polarity = PWM_POLARITY_NORMAL; 851 851 + struct of_phandle_args args; 852 852 + struct device_node *fan_np; 853 853 + 854 854 + /* 855 855 + * For backward compatibility, the pwminv module parameter takes 856 856 + * always the precedence over any other device description 857 857 + */ 858 858 + if (pwminv == 0) 859 859 + return PWM_POLARITY_NORMAL; 860 860 + if (pwminv > 0) 861 861 + return PWM_POLARITY_INVERSED; 862 862 + 863 863 + fan_np = of_get_child_by_name(client->dev.of_node, "fan"); 864 864 + if (!fan_np) 865 865 + return PWM_POLARITY_NORMAL; 866 866 + 867 867 + if (of_parse_phandle_with_args(fan_np, "pwms", "#pwm-cells", 0, &args)) 868 868 + goto out; 869 869 + of_node_put(args.np); 870 870 + 871 871 + if (args.args_count != 2) 872 872 + goto out; 873 873 + 874 874 + if (args.args[1] & PWM_POLARITY_INVERTED) 875 875 + polarity = PWM_POLARITY_INVERSED; 876 876 + out: 877 877 + of_node_put(fan_np); 878 878 + return polarity; 879 879 + } 880 880 + 881 881 + static int amc6821_init_client(struct i2c_client *client, struct amc6821_data *data) 852 882 { 853 883 struct regmap *regmap = data->regmap; 884 884 + u32 regval; 854 885 int err; 855 886 856 887 if (init) { ··· 901 864 if (err) 902 865 return err; 903 866 867 867 + regval = AMC6821_CONF1_START; 868 868 + if (amc6821_pwm_polarity(client) == PWM_POLARITY_INVERSED) 869 869 + regval |= AMC6821_CONF1_PWMINV; 870 870 + 904 871 err = regmap_update_bits(regmap, AMC6821_REG_CONF1, 905 872 AMC6821_CONF1_THERMOVIE | AMC6821_CONF1_FANIE | 906 873 AMC6821_CONF1_START | AMC6821_CONF1_PWMINV, 907 907 - AMC6821_CONF1_START | 908 908 - (pwminv ? AMC6821_CONF1_PWMINV : 0)); 874 874 + regval); 909 875 if (err) 910 876 return err; 911 877 } ··· 956 916 "Failed to initialize regmap\n"); 957 917 data->regmap = regmap; 958 918 959 959 - err = amc6821_init_client(data); 919 919 + err = amc6821_init_client(client, data); 960 920 if (err) 961 921 return err; 962 922

+45 -8

drivers/hwmon/asus-ec-sensors.c

reviewed

··· 169 169 family_intel_600_series 170 170 }; 171 171 172 172 - /* All the known sensors for ASUS EC controllers */ 172 172 + /* 173 173 + * All the known sensors for ASUS EC controllers. These arrays have to be sorted 174 174 + * by the full ((bank << 8) + index) register index (see asus_ec_block_read() as 175 175 + * to why). 176 176 + */ 173 177 static const struct ec_sensor_info sensors_family_amd_400[] = { 174 178 [ec_sensor_temp_chipset] = 175 179 EC_SENSOR("Chipset", hwmon_temp, 1, 0x00, 0x3a), ··· 187 183 EC_SENSOR("VRM", hwmon_temp, 1, 0x00, 0x3e), 188 184 [ec_sensor_in_cpu_core] = 189 185 EC_SENSOR("CPU Core", hwmon_in, 2, 0x00, 0xa2), 190 190 - [ec_sensor_fan_cpu_opt] = 191 191 - EC_SENSOR("CPU_Opt", hwmon_fan, 2, 0x00, 0xbc), 192 186 [ec_sensor_fan_vrm_hs] = 193 187 EC_SENSOR("VRM HS", hwmon_fan, 2, 0x00, 0xb2), 188 188 + [ec_sensor_fan_cpu_opt] = 189 189 + EC_SENSOR("CPU_Opt", hwmon_fan, 2, 0x00, 0xbc), 194 190 [ec_sensor_fan_chipset] = 195 191 /* no chipset fans in this generation */ 196 192 EC_SENSOR("Chipset", hwmon_fan, 0, 0x00, 0x00), ··· 198 194 EC_SENSOR("Water_Flow", hwmon_fan, 2, 0x00, 0xb4), 199 195 [ec_sensor_curr_cpu] = 200 196 EC_SENSOR("CPU", hwmon_curr, 1, 0x00, 0xf4), 201 201 - [ec_sensor_temp_water_in] = 202 202 - EC_SENSOR("Water_In", hwmon_temp, 1, 0x01, 0x0d), 203 197 [ec_sensor_temp_water_out] = 204 198 EC_SENSOR("Water_Out", hwmon_temp, 1, 0x01, 0x0b), 199 199 + [ec_sensor_temp_water_in] = 200 200 + EC_SENSOR("Water_In", hwmon_temp, 1, 0x01, 0x0d), 205 201 }; 206 202 207 203 static const struct ec_sensor_info sensors_family_amd_500[] = { ··· 243 239 244 240 static const struct ec_sensor_info sensors_family_amd_600[] = { 245 241 [ec_sensor_temp_cpu] = EC_SENSOR("CPU", hwmon_temp, 1, 0x00, 0x30), 246 246 - [ec_sensor_temp_cpu_package] = EC_SENSOR("CPU Package", hwmon_temp, 1, 0x00, 0x31), 242 242 + [ec_sensor_temp_cpu_package] = 243 243 + EC_SENSOR("CPU Package", hwmon_temp, 1, 0x00, 0x31), 247 244 [ec_sensor_temp_mb] = 248 245 EC_SENSOR("Motherboard", hwmon_temp, 1, 0x00, 0x32), 249 246 [ec_sensor_temp_vrm] = 250 247 EC_SENSOR("VRM", hwmon_temp, 1, 0x00, 0x33), 251 248 [ec_sensor_temp_t_sensor] = 252 249 EC_SENSOR("T_Sensor", hwmon_temp, 1, 0x00, 0x36), 250 250 + [ec_sensor_fan_cpu_opt] = 251 251 + EC_SENSOR("CPU_Opt", hwmon_fan, 2, 0x00, 0xb0), 253 252 [ec_sensor_temp_water_in] = 254 253 EC_SENSOR("Water_In", hwmon_temp, 1, 0x01, 0x00), 255 254 [ec_sensor_temp_water_out] = 256 255 EC_SENSOR("Water_Out", hwmon_temp, 1, 0x01, 0x01), 257 257 - [ec_sensor_fan_cpu_opt] = 258 258 - EC_SENSOR("CPU_Opt", hwmon_fan, 2, 0x00, 0xb0), 259 256 }; 260 257 261 258 static const struct ec_sensor_info sensors_family_intel_300[] = { ··· 283 278 [ec_sensor_temp_t_sensor] = 284 279 EC_SENSOR("T_Sensor", hwmon_temp, 1, 0x00, 0x3d), 285 280 [ec_sensor_temp_vrm] = EC_SENSOR("VRM", hwmon_temp, 1, 0x00, 0x3e), 281 281 + [ec_sensor_fan_water_flow] = 282 282 + EC_SENSOR("Water_Flow", hwmon_fan, 2, 0x00, 0xbe), 283 283 + [ec_sensor_temp_water_in] = 284 284 + EC_SENSOR("Water_In", hwmon_temp, 1, 0x01, 0x00), 285 285 + [ec_sensor_temp_water_out] = 286 286 + EC_SENSOR("Water_Out", hwmon_temp, 1, 0x01, 0x01), 287 287 + [ec_sensor_temp_water_block_in] = 288 288 + EC_SENSOR("Water_Block_In", hwmon_temp, 1, 0x01, 0x02), 286 289 }; 287 290 288 291 /* Shortcuts for common combinations */ ··· 311 298 */ 312 299 const char *mutex_path; 313 300 enum board_family family; 301 301 + }; 302 302 + 303 303 + static const struct ec_board_info board_info_maximus_vi_hero = { 304 304 + .sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB | 305 305 + SENSOR_TEMP_T_SENSOR | 306 306 + SENSOR_TEMP_VRM | SENSOR_SET_TEMP_WATER | 307 307 + SENSOR_FAN_CPU_OPT | SENSOR_FAN_WATER_FLOW, 308 308 + .mutex_path = ACPI_GLOBAL_LOCK_PSEUDO_PATH, 309 309 + .family = family_intel_300_series, 314 310 }; 315 311 316 312 static const struct ec_board_info board_info_prime_x470_pro = { ··· 422 400 SENSOR_FAN_CPU_OPT | SENSOR_FAN_WATER_FLOW, 423 401 .mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX, 424 402 .family = family_intel_300_series, 403 403 + }; 404 404 + 405 405 + static const struct ec_board_info board_info_maximus_z690_formula = { 406 406 + .sensors = SENSOR_TEMP_T_SENSOR | SENSOR_TEMP_VRM | 407 407 + SENSOR_SET_TEMP_WATER | SENSOR_FAN_WATER_FLOW, 408 408 + .mutex_path = ASUS_HW_ACCESS_MUTEX_RMTW_ASMX, 409 409 + .family = family_intel_600_series, 425 410 }; 426 411 427 412 static const struct ec_board_info board_info_crosshair_viii_impact = { ··· 536 507 } 537 508 538 509 static const struct dmi_system_id dmi_table[] = { 510 510 + DMI_EXACT_MATCH_ASUS_BOARD_NAME("MAXIMUS VI HERO", 511 511 + &board_info_maximus_vi_hero), 539 512 DMI_EXACT_MATCH_ASUS_BOARD_NAME("PRIME X470-PRO", 540 513 &board_info_prime_x470_pro), 541 514 DMI_EXACT_MATCH_ASUS_BOARD_NAME("PRIME X570-PRO", ··· 568 537 &board_info_maximus_xi_hero), 569 538 DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG MAXIMUS XI HERO (WI-FI)", 570 539 &board_info_maximus_xi_hero), 540 540 + DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG MAXIMUS Z690 FORMULA", 541 541 + &board_info_maximus_z690_formula), 571 542 DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VIII IMPACT", 572 543 &board_info_crosshair_viii_impact), 573 544 DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG STRIX B550-E GAMING", ··· 966 933 { 967 934 struct ec_sensors_data *state = dev_get_drvdata(dev); 968 935 int sensor_index = find_ec_sensor_index(state, type, channel); 936 936 + 937 937 + if (sensor_index < 0) 938 938 + return sensor_index; 939 939 + 969 940 *str = get_sensor_info(state, sensor_index)->label; 970 941 971 942 return 0;

+7

drivers/hwmon/dell-smm-hwmon.c

reviewed

··· 1274 1274 }, 1275 1275 }, 1276 1276 { 1277 1277 + .ident = "Dell OptiPlex 7050", 1278 1278 + .matches = { 1279 1279 + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1280 1280 + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "OptiPlex 7050"), 1281 1281 + }, 1282 1282 + }, 1283 1283 + { 1277 1284 .ident = "Dell Precision", 1278 1285 .matches = { 1279 1286 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),

+87 -16

drivers/hwmon/gpio-fan.c

reviewed

··· 20 20 #include <linux/gpio/consumer.h> 21 21 #include <linux/of.h> 22 22 #include <linux/of_platform.h> 23 23 + #include <linux/pm.h> 24 24 + #include <linux/pm_runtime.h> 25 25 + #include <linux/regulator/consumer.h> 23 26 #include <linux/thermal.h> 24 27 25 28 struct gpio_fan_speed { ··· 45 42 bool pwm_enable; 46 43 struct gpio_desc *alarm_gpio; 47 44 struct work_struct alarm_work; 45 45 + struct regulator *supply; 48 46 }; 49 47 50 48 /* ··· 129 125 } 130 126 131 127 /* Must be called with fan_data->lock held, except during initialization. */ 132 132 - static void set_fan_speed(struct gpio_fan_data *fan_data, int speed_index) 128 128 + static int set_fan_speed(struct gpio_fan_data *fan_data, int speed_index) 133 129 { 134 130 if (fan_data->speed_index == speed_index) 135 135 - return; 131 131 + return 0; 132 132 + 133 133 + if (fan_data->speed_index == 0 && speed_index > 0) { 134 134 + int ret; 135 135 + 136 136 + ret = pm_runtime_resume_and_get(fan_data->dev); 137 137 + if (ret < 0) 138 138 + return ret; 139 139 + } 136 140 137 141 __set_fan_ctrl(fan_data, fan_data->speed[speed_index].ctrl_val); 142 142 + 143 143 + if (fan_data->speed_index > 0 && speed_index == 0) { 144 144 + int ret; 145 145 + 146 146 + ret = pm_runtime_put_sync(fan_data->dev); 147 147 + if (ret < 0) 148 148 + return ret; 149 149 + } 150 150 + 138 151 fan_data->speed_index = speed_index; 152 152 + 153 153 + return 0; 139 154 } 140 155 141 156 static int get_fan_speed_index(struct gpio_fan_data *fan_data) ··· 199 176 struct gpio_fan_data *fan_data = dev_get_drvdata(dev); 200 177 unsigned long pwm; 201 178 int speed_index; 202 202 - int ret = count; 179 179 + int ret; 203 180 204 181 if (kstrtoul(buf, 10, &pwm) || pwm > 255) 205 182 return -EINVAL; ··· 212 189 } 213 190 214 191 speed_index = DIV_ROUND_UP(pwm * (fan_data->num_speed - 1), 255); 215 215 - set_fan_speed(fan_data, speed_index); 192 192 + ret = set_fan_speed(fan_data, speed_index); 216 193 217 194 exit_unlock: 218 195 mutex_unlock(&fan_data->lock); 219 196 220 220 - return ret; 197 197 + return ret ? ret : count; 221 198 } 222 199 223 200 static ssize_t pwm1_enable_show(struct device *dev, ··· 234 211 { 235 212 struct gpio_fan_data *fan_data = dev_get_drvdata(dev); 236 213 unsigned long val; 214 214 + int ret = 0; 237 215 238 216 if (kstrtoul(buf, 10, &val) || val > 1) 239 217 return -EINVAL; ··· 248 224 249 225 /* Disable manual control mode: set fan at full speed. */ 250 226 if (val == 0) 251 251 - set_fan_speed(fan_data, fan_data->num_speed - 1); 227 227 + ret = set_fan_speed(fan_data, fan_data->num_speed - 1); 252 228 253 229 mutex_unlock(&fan_data->lock); 254 230 255 255 - return count; 231 231 + return ret ? ret : count; 256 232 } 257 233 258 234 static ssize_t pwm1_mode_show(struct device *dev, ··· 303 279 goto exit_unlock; 304 280 } 305 281 306 306 - set_fan_speed(fan_data, rpm_to_speed_index(fan_data, rpm)); 282 282 + ret = set_fan_speed(fan_data, rpm_to_speed_index(fan_data, rpm)); 307 283 308 284 exit_unlock: 309 285 mutex_unlock(&fan_data->lock); ··· 410 386 unsigned long state) 411 387 { 412 388 struct gpio_fan_data *fan_data = cdev->devdata; 389 389 + int ret; 413 390 414 391 if (!fan_data) 415 392 return -EINVAL; ··· 420 395 421 396 mutex_lock(&fan_data->lock); 422 397 423 423 - set_fan_speed(fan_data, state); 398 398 + ret = set_fan_speed(fan_data, state); 424 399 425 400 mutex_unlock(&fan_data->lock); 426 401 427 427 - return 0; 402 402 + return ret; 428 403 } 429 404 430 405 static const struct thermal_cooling_device_ops gpio_fan_cool_ops = { ··· 524 499 mutex_lock(&fan_data->lock); 525 500 set_fan_speed(data, 0); 526 501 mutex_unlock(&fan_data->lock); 502 502 + 503 503 + pm_runtime_disable(fan_data->dev); 527 504 } 528 505 529 506 static int gpio_fan_probe(struct platform_device *pdev) ··· 547 520 548 521 platform_set_drvdata(pdev, fan_data); 549 522 mutex_init(&fan_data->lock); 523 523 + 524 524 + fan_data->supply = devm_regulator_get(dev, "fan"); 525 525 + if (IS_ERR(fan_data->supply)) 526 526 + return dev_err_probe(dev, PTR_ERR(fan_data->supply), 527 527 + "Failed to get fan-supply"); 550 528 551 529 /* Configure control GPIOs if available. */ 552 530 if (fan_data->gpios && fan_data->num_gpios > 0) { ··· 580 548 return err; 581 549 } 582 550 551 551 + pm_runtime_set_suspended(&pdev->dev); 552 552 + pm_runtime_enable(&pdev->dev); 553 553 + /* If current GPIO state is active, mark RPM as active as well */ 554 554 + if (fan_data->speed_index > 0) { 555 555 + int ret; 556 556 + 557 557 + ret = pm_runtime_resume_and_get(&pdev->dev); 558 558 + if (ret) 559 559 + return ret; 560 560 + } 561 561 + 583 562 /* Optional cooling device register for Device tree platforms */ 584 563 fan_data->cdev = devm_thermal_of_cooling_device_register(dev, np, 585 564 "gpio-fan", fan_data, &gpio_fan_cool_ops); ··· 608 565 set_fan_speed(fan_data, 0); 609 566 } 610 567 568 568 + static int gpio_fan_runtime_suspend(struct device *dev) 569 569 + { 570 570 + struct gpio_fan_data *fan_data = dev_get_drvdata(dev); 571 571 + int ret = 0; 572 572 + 573 573 + if (fan_data->supply) 574 574 + ret = regulator_disable(fan_data->supply); 575 575 + 576 576 + return ret; 577 577 + } 578 578 + 579 579 + static int gpio_fan_runtime_resume(struct device *dev) 580 580 + { 581 581 + struct gpio_fan_data *fan_data = dev_get_drvdata(dev); 582 582 + int ret = 0; 583 583 + 584 584 + if (fan_data->supply) 585 585 + ret = regulator_enable(fan_data->supply); 586 586 + 587 587 + return ret; 588 588 + } 589 589 + 611 590 static int gpio_fan_suspend(struct device *dev) 612 591 { 613 592 struct gpio_fan_data *fan_data = dev_get_drvdata(dev); 593 593 + int ret = 0; 614 594 615 595 if (fan_data->gpios) { 616 596 fan_data->resume_speed = fan_data->speed_index; 617 597 mutex_lock(&fan_data->lock); 618 618 - set_fan_speed(fan_data, 0); 598 598 + ret = set_fan_speed(fan_data, 0); 619 599 mutex_unlock(&fan_data->lock); 620 600 } 621 601 622 622 - return 0; 602 602 + return ret; 623 603 } 624 604 625 605 static int gpio_fan_resume(struct device *dev) 626 606 { 627 607 struct gpio_fan_data *fan_data = dev_get_drvdata(dev); 608 608 + int ret = 0; 628 609 629 610 if (fan_data->gpios) { 630 611 mutex_lock(&fan_data->lock); 631 631 - set_fan_speed(fan_data, fan_data->resume_speed); 612 612 + ret = set_fan_speed(fan_data, fan_data->resume_speed); 632 613 mutex_unlock(&fan_data->lock); 633 614 } 634 615 635 635 - return 0; 616 616 + return ret; 636 617 } 637 618 638 638 - static DEFINE_SIMPLE_DEV_PM_OPS(gpio_fan_pm, gpio_fan_suspend, gpio_fan_resume); 619 619 + static const struct dev_pm_ops gpio_fan_pm = { 620 620 + RUNTIME_PM_OPS(gpio_fan_runtime_suspend, 621 621 + gpio_fan_runtime_resume, NULL) 622 622 + SYSTEM_SLEEP_PM_OPS(gpio_fan_suspend, gpio_fan_resume) 623 623 + }; 639 624 640 625 static struct platform_driver gpio_fan_driver = { 641 626 .probe = gpio_fan_probe, 642 627 .shutdown = gpio_fan_shutdown, 643 628 .driver = { 644 629 .name = "gpio-fan", 645 645 - .pm = pm_sleep_ptr(&gpio_fan_pm), 630 630 + .pm = pm_ptr(&gpio_fan_pm), 646 631 .of_match_table = of_gpio_fan_match, 647 632 }, 648 633 };

+180 -34

drivers/hwmon/ina238.c

reviewed

··· 21 21 #define INA238_CONFIG 0x0 22 22 #define INA238_ADC_CONFIG 0x1 23 23 #define INA238_SHUNT_CALIBRATION 0x2 24 24 + #define SQ52206_SHUNT_TEMPCO 0x3 24 25 #define INA238_SHUNT_VOLTAGE 0x4 25 26 #define INA238_BUS_VOLTAGE 0x5 26 27 #define INA238_DIE_TEMP 0x6 27 28 #define INA238_CURRENT 0x7 28 29 #define INA238_POWER 0x8 30 30 + #define SQ52206_ENERGY 0x9 31 31 + #define SQ52206_CHARGE 0xa 29 32 #define INA238_DIAG_ALERT 0xb 30 33 #define INA238_SHUNT_OVER_VOLTAGE 0xc 31 34 #define INA238_SHUNT_UNDER_VOLTAGE 0xd ··· 36 33 #define INA238_BUS_UNDER_VOLTAGE 0xf 37 34 #define INA238_TEMP_LIMIT 0x10 38 35 #define INA238_POWER_LIMIT 0x11 36 36 + #define SQ52206_POWER_PEAK 0x20 39 37 #define INA238_DEVICE_ID 0x3f /* not available on INA237 */ 40 38 41 39 #define INA238_CONFIG_ADCRANGE BIT(4) 40 40 + #define SQ52206_CONFIG_ADCRANGE_HIGH BIT(4) 41 41 + #define SQ52206_CONFIG_ADCRANGE_LOW BIT(3) 42 42 43 43 #define INA238_DIAG_ALERT_TMPOL BIT(7) 44 44 #define INA238_DIAG_ALERT_SHNTOL BIT(6) ··· 50 44 #define INA238_DIAG_ALERT_BUSUL BIT(3) 51 45 #define INA238_DIAG_ALERT_POL BIT(2) 52 46 53 53 - #define INA238_REGISTERS 0x11 47 47 + #define INA238_REGISTERS 0x20 54 48 55 49 #define INA238_RSHUNT_DEFAULT 10000 /* uOhm */ 56 50 57 51 /* Default configuration of device on reset. */ 58 52 #define INA238_CONFIG_DEFAULT 0 53 53 + #define SQ52206_CONFIG_DEFAULT 0x0005 59 54 /* 16 sample averaging, 1052us conversion time, continuous mode */ 60 55 #define INA238_ADC_CONFIG_DEFAULT 0xfb6a 61 56 /* Configure alerts to be based on averaged value (SLOWALERT) */ ··· 94 87 * shunt = 0x4000 / (819.2 * 10^6) / 0.001 = 20000 uOhms (with 1mA/lsb) 95 88 * 96 89 * Current (mA) = register value * 20000 / rshunt / 4 * gain 97 97 - * Power (W) = 0.2 * register value * 20000 / rshunt / 4 * gain 90 90 + * Power (mW) = 0.2 * register value * 20000 / rshunt / 4 * gain 91 91 + * (Specific for SQ52206) 92 92 + * Power (mW) = 0.24 * register value * 20000 / rshunt / 4 * gain 93 93 + * Energy (mJ) = 16 * 0.24 * register value * 20000 / rshunt / 4 * gain 98 94 */ 99 95 #define INA238_CALIBRATION_VALUE 16384 100 96 #define INA238_FIXED_SHUNT 20000 101 97 102 98 #define INA238_SHUNT_VOLTAGE_LSB 5 /* 5 uV/lsb */ 103 99 #define INA238_BUS_VOLTAGE_LSB 3125 /* 3.125 mV/lsb */ 104 104 - #define INA238_DIE_TEMP_LSB 125 /* 125 mC/lsb */ 100 100 + #define INA238_DIE_TEMP_LSB 1250000 /* 125.0000 mC/lsb */ 101 101 + #define SQ52206_BUS_VOLTAGE_LSB 3750 /* 3.75 mV/lsb */ 102 102 + #define SQ52206_DIE_TEMP_LSB 78125 /* 7.8125 mC/lsb */ 105 103 106 104 static const struct regmap_config ina238_regmap_config = { 107 105 .max_register = INA238_REGISTERS, ··· 114 102 .val_bits = 16, 115 103 }; 116 104 105 105 + enum ina238_ids { ina238, ina237, sq52206 }; 106 106 + 107 107 + struct ina238_config { 108 108 + bool has_power_highest; /* chip detection power peak */ 109 109 + bool has_energy; /* chip detection energy */ 110 110 + u8 temp_shift; /* fixed parameters for temp calculate */ 111 111 + u32 power_calculate_factor; /* fixed parameters for power calculate */ 112 112 + u16 config_default; /* Power-on default state */ 113 113 + int bus_voltage_lsb; /* use for temperature calculate, uV/lsb */ 114 114 + int temp_lsb; /* use for temperature calculate */ 115 115 + }; 116 116 + 117 117 struct ina238_data { 118 118 + const struct ina238_config *config; 118 119 struct i2c_client *client; 119 120 struct mutex config_lock; 120 121 struct regmap *regmap; 121 122 u32 rshunt; 122 123 int gain; 124 124 + }; 125 125 + 126 126 + static const struct ina238_config ina238_config[] = { 127 127 + [ina238] = { 128 128 + .has_energy = false, 129 129 + .has_power_highest = false, 130 130 + .temp_shift = 4, 131 131 + .power_calculate_factor = 20, 132 132 + .config_default = INA238_CONFIG_DEFAULT, 133 133 + .bus_voltage_lsb = INA238_BUS_VOLTAGE_LSB, 134 134 + .temp_lsb = INA238_DIE_TEMP_LSB, 135 135 + }, 136 136 + [ina237] = { 137 137 + .has_energy = false, 138 138 + .has_power_highest = false, 139 139 + .temp_shift = 4, 140 140 + .power_calculate_factor = 20, 141 141 + .config_default = INA238_CONFIG_DEFAULT, 142 142 + .bus_voltage_lsb = INA238_BUS_VOLTAGE_LSB, 143 143 + .temp_lsb = INA238_DIE_TEMP_LSB, 144 144 + }, 145 145 + [sq52206] = { 146 146 + .has_energy = true, 147 147 + .has_power_highest = true, 148 148 + .temp_shift = 0, 149 149 + .power_calculate_factor = 24, 150 150 + .config_default = SQ52206_CONFIG_DEFAULT, 151 151 + .bus_voltage_lsb = SQ52206_BUS_VOLTAGE_LSB, 152 152 + .temp_lsb = SQ52206_DIE_TEMP_LSB, 153 153 + }, 123 154 }; 124 155 125 156 static int ina238_read_reg24(const struct i2c_client *client, u8 reg, u32 *val) ··· 177 122 if (err != 3) 178 123 return -EIO; 179 124 *val = (data[0] << 16) | (data[1] << 8) | data[2]; 125 125 + 126 126 + return 0; 127 127 + } 128 128 + 129 129 + static int ina238_read_reg40(const struct i2c_client *client, u8 reg, u64 *val) 130 130 + { 131 131 + u8 data[5]; 132 132 + u32 low; 133 133 + int err; 134 134 + 135 135 + /* 40-bit register read */ 136 136 + err = i2c_smbus_read_i2c_block_data(client, reg, 5, data); 137 137 + if (err < 0) 138 138 + return err; 139 139 + if (err != 5) 140 140 + return -EIO; 141 141 + low = (data[1] << 24) | (data[2] << 16) | (data[3] << 8) | data[4]; 142 142 + *val = ((long long)data[0] << 32) | low; 180 143 181 144 return 0; 182 145 } ··· 270 197 regval = (s16)regval; 271 198 if (channel == 0) 272 199 /* gain of 1 -> LSB / 4 */ 273 273 - *val = (regval * INA238_SHUNT_VOLTAGE_LSB) / 274 274 - (1000 * (4 - data->gain + 1)); 200 200 + *val = (regval * INA238_SHUNT_VOLTAGE_LSB) * 201 201 + data->gain / (1000 * 4); 275 202 else 276 276 - *val = (regval * INA238_BUS_VOLTAGE_LSB) / 1000; 203 203 + *val = (regval * data->config->bus_voltage_lsb) / 1000; 277 204 break; 278 205 case hwmon_in_max_alarm: 279 206 case hwmon_in_min_alarm: ··· 298 225 case 0: 299 226 /* signed value, clamp to max range +/-163 mV */ 300 227 regval = clamp_val(val, -163, 163); 301 301 - regval = (regval * 1000 * (4 - data->gain + 1)) / 302 302 - INA238_SHUNT_VOLTAGE_LSB; 228 228 + regval = (regval * 1000 * 4) / 229 229 + (INA238_SHUNT_VOLTAGE_LSB * data->gain); 303 230 regval = clamp_val(regval, S16_MIN, S16_MAX); 304 231 305 232 switch (attr) { ··· 315 242 case 1: 316 243 /* signed value, positive values only. Clamp to max 102.396 V */ 317 244 regval = clamp_val(val, 0, 102396); 318 318 - regval = (regval * 1000) / INA238_BUS_VOLTAGE_LSB; 245 245 + regval = (regval * 1000) / data->config->bus_voltage_lsb; 319 246 regval = clamp_val(regval, 0, S16_MAX); 320 247 321 248 switch (attr) { ··· 370 297 return err; 371 298 372 299 /* Fixed 1mA lsb, scaled by 1000000 to have result in uW */ 373 373 - power = div_u64(regval * 1000ULL * INA238_FIXED_SHUNT * 374 374 - data->gain, 20 * data->rshunt); 300 300 + power = div_u64(regval * 1000ULL * INA238_FIXED_SHUNT * data->gain * 301 301 + data->config->power_calculate_factor, 4 * 100 * data->rshunt); 302 302 + /* Clamp value to maximum value of long */ 303 303 + *val = clamp_val(power, 0, LONG_MAX); 304 304 + break; 305 305 + case hwmon_power_input_highest: 306 306 + err = ina238_read_reg24(data->client, SQ52206_POWER_PEAK, &regval); 307 307 + if (err) 308 308 + return err; 309 309 + 310 310 + /* Fixed 1mA lsb, scaled by 1000000 to have result in uW */ 311 311 + power = div_u64(regval * 1000ULL * INA238_FIXED_SHUNT * data->gain * 312 312 + data->config->power_calculate_factor, 4 * 100 * data->rshunt); 375 313 /* Clamp value to maximum value of long */ 376 314 *val = clamp_val(power, 0, LONG_MAX); 377 315 break; ··· 395 311 * Truncated 24-bit compare register, lower 8-bits are 396 312 * truncated. Same conversion to/from uW as POWER register. 397 313 */ 398 398 - power = div_u64((regval << 8) * 1000ULL * INA238_FIXED_SHUNT * 399 399 - data->gain, 20 * data->rshunt); 314 314 + power = div_u64((regval << 8) * 1000ULL * INA238_FIXED_SHUNT * data->gain * 315 315 + data->config->power_calculate_factor, 4 * 100 * data->rshunt); 400 316 /* Clamp value to maximum value of long */ 401 317 *val = clamp_val(power, 0, LONG_MAX); 402 318 break; ··· 428 344 * register. 429 345 */ 430 346 regval = clamp_val(val, 0, LONG_MAX); 431 431 - regval = div_u64(val * 20ULL * data->rshunt, 432 432 - 1000ULL * INA238_FIXED_SHUNT * data->gain); 347 347 + regval = div_u64(val * 4 * 100 * data->rshunt, data->config->power_calculate_factor * 348 348 + 1000ULL * INA238_FIXED_SHUNT * data->gain); 433 349 regval = clamp_val(regval >> 8, 0, U16_MAX); 434 350 435 351 return regmap_write(data->regmap, INA238_POWER_LIMIT, regval); ··· 446 362 err = regmap_read(data->regmap, INA238_DIE_TEMP, &regval); 447 363 if (err) 448 364 return err; 449 449 - 450 450 - /* Signed, bits 15-4 of register, result in mC */ 451 451 - *val = ((s16)regval >> 4) * INA238_DIE_TEMP_LSB; 365 365 + /* Signed, result in mC */ 366 366 + *val = div_s64(((s64)((s16)regval) >> data->config->temp_shift) * 367 367 + (s64)data->config->temp_lsb, 10000); 452 368 break; 453 369 case hwmon_temp_max: 454 370 err = regmap_read(data->regmap, INA238_TEMP_LIMIT, &regval); 455 371 if (err) 456 372 return err; 457 457 - 458 458 - /* Signed, bits 15-4 of register, result in mC */ 459 459 - *val = ((s16)regval >> 4) * INA238_DIE_TEMP_LSB; 373 373 + /* Signed, result in mC */ 374 374 + *val = div_s64(((s64)((s16)regval) >> data->config->temp_shift) * 375 375 + (s64)data->config->temp_lsb, 10000); 460 376 break; 461 377 case hwmon_temp_max_alarm: 462 378 err = regmap_read(data->regmap, INA238_DIAG_ALERT, &regval); ··· 480 396 if (attr != hwmon_temp_max) 481 397 return -EOPNOTSUPP; 482 398 483 483 - /* Signed, bits 15-4 of register */ 484 484 - regval = (val / INA238_DIE_TEMP_LSB) << 4; 485 485 - regval = clamp_val(regval, S16_MIN, S16_MAX) & 0xfff0; 399 399 + /* Signed */ 400 400 + regval = clamp_val(val, -40000, 125000); 401 401 + regval = div_s64(val * 10000, data->config->temp_lsb) << data->config->temp_shift; 402 402 + regval = clamp_val(regval, S16_MIN, S16_MAX) & (0xffff << data->config->temp_shift); 486 403 487 404 return regmap_write(data->regmap, INA238_TEMP_LIMIT, regval); 405 405 + } 406 406 + 407 407 + static ssize_t energy1_input_show(struct device *dev, 408 408 + struct device_attribute *da, char *buf) 409 409 + { 410 410 + struct ina238_data *data = dev_get_drvdata(dev); 411 411 + int ret; 412 412 + u64 regval; 413 413 + u64 energy; 414 414 + 415 415 + ret = ina238_read_reg40(data->client, SQ52206_ENERGY, &regval); 416 416 + if (ret) 417 417 + return ret; 418 418 + 419 419 + /* result in mJ */ 420 420 + energy = div_u64(regval * INA238_FIXED_SHUNT * data->gain * 16 * 421 421 + data->config->power_calculate_factor, 4 * 100 * data->rshunt); 422 422 + 423 423 + return sysfs_emit(buf, "%llu\n", energy); 488 424 } 489 425 490 426 static int ina238_read(struct device *dev, enum hwmon_sensor_types type, ··· 526 422 } 527 423 528 424 static int ina238_write(struct device *dev, enum hwmon_sensor_types type, 529 529 - u32 attr, int channel, long val) 425 425 + u32 attr, int channel, long val) 530 426 { 531 427 struct ina238_data *data = dev_get_drvdata(dev); 532 428 int err; ··· 556 452 enum hwmon_sensor_types type, 557 453 u32 attr, int channel) 558 454 { 455 455 + const struct ina238_data *data = drvdata; 456 456 + bool has_power_highest = data->config->has_power_highest; 457 457 + 559 458 switch (type) { 560 459 case hwmon_in: 561 460 switch (attr) { ··· 586 479 return 0444; 587 480 case hwmon_power_max: 588 481 return 0644; 482 482 + case hwmon_power_input_highest: 483 483 + if (has_power_highest) 484 484 + return 0444; 485 485 + return 0; 589 486 default: 590 487 return 0; 591 488 } ··· 623 512 HWMON_C_INPUT), 624 513 HWMON_CHANNEL_INFO(power, 625 514 /* 0: power */ 626 626 - HWMON_P_INPUT | HWMON_P_MAX | HWMON_P_MAX_ALARM), 515 515 + HWMON_P_INPUT | HWMON_P_MAX | 516 516 + HWMON_P_MAX_ALARM | HWMON_P_INPUT_HIGHEST), 627 517 HWMON_CHANNEL_INFO(temp, 628 518 /* 0: die temperature */ 629 519 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_ALARM), ··· 642 530 .info = ina238_info, 643 531 }; 644 532 533 533 + /* energy attributes are 5 bytes wide so we need u64 */ 534 534 + static DEVICE_ATTR_RO(energy1_input); 535 535 + 536 536 + static struct attribute *ina238_attrs[] = { 537 537 + &dev_attr_energy1_input.attr, 538 538 + NULL, 539 539 + }; 540 540 + ATTRIBUTE_GROUPS(ina238); 541 541 + 645 542 static int ina238_probe(struct i2c_client *client) 646 543 { 647 544 struct ina2xx_platform_data *pdata = dev_get_platdata(&client->dev); 648 545 struct device *dev = &client->dev; 649 546 struct device *hwmon_dev; 650 547 struct ina238_data *data; 548 548 + enum ina238_ids chip; 651 549 int config; 652 550 int ret; 551 551 + 552 552 + chip = (uintptr_t)i2c_get_match_data(client); 653 553 654 554 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 655 555 if (!data) 656 556 return -ENOMEM; 657 557 658 558 data->client = client; 559 559 + /* set the device type */ 560 560 + data->config = &ina238_config[chip]; 561 561 + 659 562 mutex_init(&data->config_lock); 660 563 661 564 data->regmap = devm_regmap_init_i2c(client, &ina238_regmap_config); ··· 691 564 /* load shunt gain value */ 692 565 if (device_property_read_u32(dev, "ti,shunt-gain", &data->gain) < 0) 693 566 data->gain = 4; /* Default of ADCRANGE = 0 */ 694 694 - if (data->gain != 1 && data->gain != 4) { 567 567 + if (data->gain != 1 && data->gain != 2 && data->gain != 4) { 695 568 dev_err(dev, "invalid shunt gain value %u\n", data->gain); 696 569 return -EINVAL; 697 570 } 698 571 699 572 /* Setup CONFIG register */ 700 700 - config = INA238_CONFIG_DEFAULT; 701 701 - if (data->gain == 1) 573 573 + config = data->config->config_default; 574 574 + if (chip == sq52206) { 575 575 + if (data->gain == 1) 576 576 + config |= SQ52206_CONFIG_ADCRANGE_HIGH; /* ADCRANGE = 10/11 is /1 */ 577 577 + else if (data->gain == 2) 578 578 + config |= SQ52206_CONFIG_ADCRANGE_LOW; /* ADCRANGE = 01 is /2 */ 579 579 + } else if (data->gain == 1) { 702 580 config |= INA238_CONFIG_ADCRANGE; /* ADCRANGE = 1 is /1 */ 581 581 + } 703 582 ret = regmap_write(data->regmap, INA238_CONFIG, config); 704 583 if (ret < 0) { 705 584 dev_err(dev, "error configuring the device: %d\n", ret); ··· 738 605 739 606 hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, data, 740 607 &ina238_chip_info, 741 741 - NULL); 608 608 + data->config->has_energy ? 609 609 + ina238_groups : NULL); 742 610 if (IS_ERR(hwmon_dev)) 743 611 return PTR_ERR(hwmon_dev); 744 612 ··· 750 616 } 751 617 752 618 static const struct i2c_device_id ina238_id[] = { 753 753 - { "ina238" }, 619 619 + { "ina237", ina237 }, 620 620 + { "ina238", ina238 }, 621 621 + { "sq52206", sq52206 }, 754 622 { } 755 623 }; 756 624 MODULE_DEVICE_TABLE(i2c, ina238_id); 757 625 758 626 static const struct of_device_id __maybe_unused ina238_of_match[] = { 759 759 - { .compatible = "ti,ina237" }, 760 760 - { .compatible = "ti,ina238" }, 761 761 - { }, 627 627 + { 628 628 + .compatible = "ti,ina237", 629 629 + .data = (void *)ina237 630 630 + }, 631 631 + { 632 632 + .compatible = "ti,ina238", 633 633 + .data = (void *)ina238 634 634 + }, 635 635 + { 636 636 + .compatible = "silergy,sq52206", 637 637 + .data = (void *)sq52206 638 638 + }, 639 639 + { } 762 640 }; 763 641 MODULE_DEVICE_TABLE(of, ina238_of_match); 764 642

+6 -2

drivers/hwmon/ina2xx.c

reviewed

··· 959 959 return PTR_ERR(data->regmap); 960 960 } 961 961 962 962 - ret = devm_regulator_get_enable(dev, "vs"); 963 963 - if (ret) 962 962 + /* 963 963 + * Regulator core returns -ENODEV if the 'vs' is not available. 964 964 + * Hence the check for -ENODEV return code is necessary. 965 965 + */ 966 966 + ret = devm_regulator_get_enable_optional(dev, "vs"); 967 967 + if (ret < 0 && ret != -ENODEV) 964 968 return dev_err_probe(dev, ret, "failed to enable vs regulator\n"); 965 969 966 970 ret = ina2xx_init(dev, data);

+5 -3

drivers/hwmon/isl28022.c

reviewed

··· 154 154 struct isl28022_data *data = dev_get_drvdata(dev); 155 155 unsigned int regval; 156 156 int err; 157 157 + u16 sign_bit; 157 158 158 159 switch (attr) { 159 160 case hwmon_curr_input: ··· 162 161 ISL28022_REG_CURRENT, &regval); 163 162 if (err < 0) 164 163 return err; 165 165 - *val = ((long)regval * 1250L * (long)data->gain) / 166 166 - (long)data->shunt; 164 164 + sign_bit = (regval >> 15) & 0x01; 165 165 + *val = (((long)(((u16)regval) & 0x7FFF) - (sign_bit * 32768)) * 166 166 + 1250L * (long)data->gain) / (long)data->shunt; 167 167 break; 168 168 default: 169 169 return -EOPNOTSUPP; ··· 303 301 .writeable_reg = isl28022_is_writeable_reg, 304 302 .volatile_reg = isl28022_is_volatile_reg, 305 303 .val_format_endian = REGMAP_ENDIAN_BIG, 306 306 - .cache_type = REGCACHE_RBTREE, 304 304 + .cache_type = REGCACHE_MAPLE, 307 305 .use_single_read = true, 308 306 .use_single_write = true, 309 307 };

+7

drivers/hwmon/k10temp.c

reviewed

··· 503 503 k10temp_get_ccd_support(data, 12); 504 504 break; 505 505 } 506 506 + } else if (boot_cpu_data.x86 == 0x1a) { 507 507 + switch (boot_cpu_data.x86_model) { 508 508 + case 0x40 ... 0x4f: /* Zen5 Ryzen Desktop */ 509 509 + data->ccd_offset = 0x308; 510 510 + k10temp_get_ccd_support(data, 8); 511 511 + break; 512 512 + } 506 513 } 507 514 508 515 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {

+147

drivers/hwmon/kbatt.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2025 KEBA Industrial Automation GmbH 4 4 + * 5 5 + * Driver for KEBA battery monitoring controller FPGA IP core 6 6 + */ 7 7 + 8 8 + #include <linux/hwmon.h> 9 9 + #include <linux/io.h> 10 10 + #include <linux/delay.h> 11 11 + #include <linux/module.h> 12 12 + #include <linux/device.h> 13 13 + #include <linux/auxiliary_bus.h> 14 14 + #include <linux/misc/keba.h> 15 15 + #include <linux/mutex.h> 16 16 + 17 17 + #define KBATT "kbatt" 18 18 + 19 19 + #define KBATT_CONTROL_REG 0x4 20 20 + #define KBATT_CONTROL_BAT_TEST 0x01 21 21 + 22 22 + #define KBATT_STATUS_REG 0x8 23 23 + #define KBATT_STATUS_BAT_OK 0x01 24 24 + 25 25 + #define KBATT_MAX_UPD_INTERVAL (10 * HZ) 26 26 + #define KBATT_SETTLE_TIME_US (100 * USEC_PER_MSEC) 27 27 + 28 28 + struct kbatt { 29 29 + /* update lock */ 30 30 + struct mutex lock; 31 31 + void __iomem *base; 32 32 + 33 33 + unsigned long next_update; /* in jiffies */ 34 34 + bool alarm; 35 35 + }; 36 36 + 37 37 + static bool kbatt_alarm(struct kbatt *kbatt) 38 38 + { 39 39 + mutex_lock(&kbatt->lock); 40 40 + 41 41 + if (!kbatt->next_update || time_after(jiffies, kbatt->next_update)) { 42 42 + /* switch load on */ 43 43 + iowrite8(KBATT_CONTROL_BAT_TEST, 44 44 + kbatt->base + KBATT_CONTROL_REG); 45 45 + 46 46 + /* wait some time to let things settle */ 47 47 + fsleep(KBATT_SETTLE_TIME_US); 48 48 + 49 49 + /* check battery state */ 50 50 + if (ioread8(kbatt->base + KBATT_STATUS_REG) & 51 51 + KBATT_STATUS_BAT_OK) 52 52 + kbatt->alarm = false; 53 53 + else 54 54 + kbatt->alarm = true; 55 55 + 56 56 + /* switch load off */ 57 57 + iowrite8(0, kbatt->base + KBATT_CONTROL_REG); 58 58 + 59 59 + kbatt->next_update = jiffies + KBATT_MAX_UPD_INTERVAL; 60 60 + } 61 61 + 62 62 + mutex_unlock(&kbatt->lock); 63 63 + 64 64 + return kbatt->alarm; 65 65 + } 66 66 + 67 67 + static int kbatt_read(struct device *dev, enum hwmon_sensor_types type, 68 68 + u32 attr, int channel, long *val) 69 69 + { 70 70 + struct kbatt *kbatt = dev_get_drvdata(dev); 71 71 + 72 72 + *val = kbatt_alarm(kbatt) ? 1 : 0; 73 73 + 74 74 + return 0; 75 75 + } 76 76 + 77 77 + static umode_t kbatt_is_visible(const void *data, enum hwmon_sensor_types type, 78 78 + u32 attr, int channel) 79 79 + { 80 80 + if (channel == 0 && attr == hwmon_in_min_alarm) 81 81 + return 0444; 82 82 + 83 83 + return 0; 84 84 + } 85 85 + 86 86 + static const struct hwmon_channel_info *kbatt_info[] = { 87 87 + HWMON_CHANNEL_INFO(in, 88 88 + /* 0: input minimum alarm channel */ 89 89 + HWMON_I_MIN_ALARM), 90 90 + NULL 91 91 + }; 92 92 + 93 93 + static const struct hwmon_ops kbatt_hwmon_ops = { 94 94 + .is_visible = kbatt_is_visible, 95 95 + .read = kbatt_read, 96 96 + }; 97 97 + 98 98 + static const struct hwmon_chip_info kbatt_chip_info = { 99 99 + .ops = &kbatt_hwmon_ops, 100 100 + .info = kbatt_info, 101 101 + }; 102 102 + 103 103 + static int kbatt_probe(struct auxiliary_device *auxdev, 104 104 + const struct auxiliary_device_id *id) 105 105 + { 106 106 + struct keba_batt_auxdev *kbatt_auxdev = 107 107 + container_of(auxdev, struct keba_batt_auxdev, auxdev); 108 108 + struct device *dev = &auxdev->dev; 109 109 + struct device *hwmon_dev; 110 110 + struct kbatt *kbatt; 111 111 + int retval; 112 112 + 113 113 + kbatt = devm_kzalloc(dev, sizeof(*kbatt), GFP_KERNEL); 114 114 + if (!kbatt) 115 115 + return -ENOMEM; 116 116 + 117 117 + retval = devm_mutex_init(dev, &kbatt->lock); 118 118 + if (retval) 119 119 + return retval; 120 120 + 121 121 + kbatt->base = devm_ioremap_resource(dev, &kbatt_auxdev->io); 122 122 + if (IS_ERR(kbatt->base)) 123 123 + return PTR_ERR(kbatt->base); 124 124 + 125 125 + hwmon_dev = devm_hwmon_device_register_with_info(dev, KBATT, kbatt, 126 126 + &kbatt_chip_info, 127 127 + NULL); 128 128 + return PTR_ERR_OR_ZERO(hwmon_dev); 129 129 + } 130 130 + 131 131 + static const struct auxiliary_device_id kbatt_devtype_aux[] = { 132 132 + { .name = "keba.batt" }, 133 133 + {} 134 134 + }; 135 135 + MODULE_DEVICE_TABLE(auxiliary, kbatt_devtype_aux); 136 136 + 137 137 + static struct auxiliary_driver kbatt_driver_aux = { 138 138 + .name = KBATT, 139 139 + .id_table = kbatt_devtype_aux, 140 140 + .probe = kbatt_probe, 141 141 + }; 142 142 + module_auxiliary_driver(kbatt_driver_aux); 143 143 + 144 144 + MODULE_AUTHOR("Petar Bojanic <boja@keba.com>"); 145 145 + MODULE_AUTHOR("Gerhard Engleder <eg@keba.com>"); 146 146 + MODULE_DESCRIPTION("KEBA battery monitoring controller driver"); 147 147 + MODULE_LICENSE("GPL");

+246

drivers/hwmon/kfan.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright (C) 2025 KEBA Industrial Automation GmbH 4 4 + * 5 5 + * Driver for KEBA fan controller FPGA IP core 6 6 + * 7 7 + */ 8 8 + 9 9 + #include <linux/hwmon.h> 10 10 + #include <linux/io.h> 11 11 + #include <linux/module.h> 12 12 + #include <linux/device.h> 13 13 + #include <linux/auxiliary_bus.h> 14 14 + #include <linux/misc/keba.h> 15 15 + 16 16 + #define KFAN "kfan" 17 17 + 18 18 + #define KFAN_CONTROL_REG 0x04 19 19 + 20 20 + #define KFAN_STATUS_REG 0x08 21 21 + #define KFAN_STATUS_PRESENT 0x01 22 22 + #define KFAN_STATUS_REGULABLE 0x02 23 23 + #define KFAN_STATUS_TACHO 0x04 24 24 + #define KFAN_STATUS_BLOCKED 0x08 25 25 + 26 26 + #define KFAN_TACHO_REG 0x0c 27 27 + 28 28 + #define KFAN_DEFAULT_DIV 2 29 29 + 30 30 + struct kfan { 31 31 + void __iomem *base; 32 32 + bool tacho; 33 33 + bool regulable; 34 34 + 35 35 + /* hwmon API configuration */ 36 36 + u32 fan_channel_config[2]; 37 37 + struct hwmon_channel_info fan_info; 38 38 + u32 pwm_channel_config[2]; 39 39 + struct hwmon_channel_info pwm_info; 40 40 + const struct hwmon_channel_info *info[3]; 41 41 + struct hwmon_chip_info chip; 42 42 + }; 43 43 + 44 44 + static bool kfan_get_fault(struct kfan *kfan) 45 45 + { 46 46 + u8 status = ioread8(kfan->base + KFAN_STATUS_REG); 47 47 + 48 48 + if (!(status & KFAN_STATUS_PRESENT)) 49 49 + return true; 50 50 + 51 51 + if (!kfan->tacho && (status & KFAN_STATUS_BLOCKED)) 52 52 + return true; 53 53 + 54 54 + return false; 55 55 + } 56 56 + 57 57 + static unsigned int kfan_count_to_rpm(u16 count) 58 58 + { 59 59 + if (count == 0 || count == 0xffff) 60 60 + return 0; 61 61 + 62 62 + return 5000000UL / (KFAN_DEFAULT_DIV * count); 63 63 + } 64 64 + 65 65 + static unsigned int kfan_get_rpm(struct kfan *kfan) 66 66 + { 67 67 + unsigned int rpm; 68 68 + u16 count; 69 69 + 70 70 + count = ioread16(kfan->base + KFAN_TACHO_REG); 71 71 + rpm = kfan_count_to_rpm(count); 72 72 + 73 73 + return rpm; 74 74 + } 75 75 + 76 76 + static unsigned int kfan_get_pwm(struct kfan *kfan) 77 77 + { 78 78 + return ioread8(kfan->base + KFAN_CONTROL_REG); 79 79 + } 80 80 + 81 81 + static int kfan_set_pwm(struct kfan *kfan, long val) 82 82 + { 83 83 + if (val < 0 || val > 0xff) 84 84 + return -EINVAL; 85 85 + 86 86 + /* if none-regulable, then only 0 or 0xff can be written */ 87 87 + if (!kfan->regulable && val > 0) 88 88 + val = 0xff; 89 89 + 90 90 + iowrite8(val, kfan->base + KFAN_CONTROL_REG); 91 91 + 92 92 + return 0; 93 93 + } 94 94 + 95 95 + static int kfan_write(struct device *dev, enum hwmon_sensor_types type, 96 96 + u32 attr, int channel, long val) 97 97 + { 98 98 + struct kfan *kfan = dev_get_drvdata(dev); 99 99 + 100 100 + switch (type) { 101 101 + case hwmon_pwm: 102 102 + switch (attr) { 103 103 + case hwmon_pwm_input: 104 104 + return kfan_set_pwm(kfan, val); 105 105 + default: 106 106 + break; 107 107 + } 108 108 + break; 109 109 + default: 110 110 + break; 111 111 + } 112 112 + 113 113 + return -EOPNOTSUPP; 114 114 + } 115 115 + 116 116 + static int kfan_read(struct device *dev, enum hwmon_sensor_types type, 117 117 + u32 attr, int channel, long *val) 118 118 + { 119 119 + struct kfan *kfan = dev_get_drvdata(dev); 120 120 + 121 121 + switch (type) { 122 122 + case hwmon_fan: 123 123 + switch (attr) { 124 124 + case hwmon_fan_fault: 125 125 + *val = kfan_get_fault(kfan); 126 126 + return 0; 127 127 + case hwmon_fan_input: 128 128 + *val = kfan_get_rpm(kfan); 129 129 + return 0; 130 130 + default: 131 131 + break; 132 132 + } 133 133 + break; 134 134 + case hwmon_pwm: 135 135 + switch (attr) { 136 136 + case hwmon_pwm_input: 137 137 + *val = kfan_get_pwm(kfan); 138 138 + return 0; 139 139 + default: 140 140 + break; 141 141 + } 142 142 + break; 143 143 + default: 144 144 + break; 145 145 + } 146 146 + 147 147 + return -EOPNOTSUPP; 148 148 + } 149 149 + 150 150 + static umode_t kfan_is_visible(const void *data, enum hwmon_sensor_types type, 151 151 + u32 attr, int channel) 152 152 + { 153 153 + switch (type) { 154 154 + case hwmon_fan: 155 155 + switch (attr) { 156 156 + case hwmon_fan_input: 157 157 + return 0444; 158 158 + case hwmon_fan_fault: 159 159 + return 0444; 160 160 + default: 161 161 + break; 162 162 + } 163 163 + break; 164 164 + case hwmon_pwm: 165 165 + switch (attr) { 166 166 + case hwmon_pwm_input: 167 167 + return 0644; 168 168 + default: 169 169 + break; 170 170 + } 171 171 + break; 172 172 + default: 173 173 + break; 174 174 + } 175 175 + 176 176 + return 0; 177 177 + } 178 178 + 179 179 + static const struct hwmon_ops kfan_hwmon_ops = { 180 180 + .is_visible = kfan_is_visible, 181 181 + .read = kfan_read, 182 182 + .write = kfan_write, 183 183 + }; 184 184 + 185 185 + static int kfan_probe(struct auxiliary_device *auxdev, 186 186 + const struct auxiliary_device_id *id) 187 187 + { 188 188 + struct keba_fan_auxdev *kfan_auxdev = 189 189 + container_of(auxdev, struct keba_fan_auxdev, auxdev); 190 190 + struct device *dev = &auxdev->dev; 191 191 + struct device *hwmon_dev; 192 192 + struct kfan *kfan; 193 193 + u8 status; 194 194 + 195 195 + kfan = devm_kzalloc(dev, sizeof(*kfan), GFP_KERNEL); 196 196 + if (!kfan) 197 197 + return -ENOMEM; 198 198 + 199 199 + kfan->base = devm_ioremap_resource(dev, &kfan_auxdev->io); 200 200 + if (IS_ERR(kfan->base)) 201 201 + return PTR_ERR(kfan->base); 202 202 + 203 203 + status = ioread8(kfan->base + KFAN_STATUS_REG); 204 204 + if (status & KFAN_STATUS_REGULABLE) 205 205 + kfan->regulable = true; 206 206 + if (status & KFAN_STATUS_TACHO) 207 207 + kfan->tacho = true; 208 208 + 209 209 + /* fan */ 210 210 + kfan->fan_channel_config[0] = HWMON_F_FAULT; 211 211 + if (kfan->tacho) 212 212 + kfan->fan_channel_config[0] |= HWMON_F_INPUT; 213 213 + kfan->fan_info.type = hwmon_fan; 214 214 + kfan->fan_info.config = kfan->fan_channel_config; 215 215 + kfan->info[0] = &kfan->fan_info; 216 216 + 217 217 + /* PWM */ 218 218 + kfan->pwm_channel_config[0] = HWMON_PWM_INPUT; 219 219 + kfan->pwm_info.type = hwmon_pwm; 220 220 + kfan->pwm_info.config = kfan->pwm_channel_config; 221 221 + kfan->info[1] = &kfan->pwm_info; 222 222 + 223 223 + kfan->chip.ops = &kfan_hwmon_ops; 224 224 + kfan->chip.info = kfan->info; 225 225 + hwmon_dev = devm_hwmon_device_register_with_info(dev, KFAN, kfan, 226 226 + &kfan->chip, NULL); 227 227 + return PTR_ERR_OR_ZERO(hwmon_dev); 228 228 + } 229 229 + 230 230 + static const struct auxiliary_device_id kfan_devtype_aux[] = { 231 231 + { .name = "keba.fan" }, 232 232 + {} 233 233 + }; 234 234 + MODULE_DEVICE_TABLE(auxiliary, kfan_devtype_aux); 235 235 + 236 236 + static struct auxiliary_driver kfan_driver_aux = { 237 237 + .name = KFAN, 238 238 + .id_table = kfan_devtype_aux, 239 239 + .probe = kfan_probe, 240 240 + }; 241 241 + module_auxiliary_driver(kfan_driver_aux); 242 242 + 243 243 + MODULE_AUTHOR("Petar Bojanic <boja@keba.com>"); 244 244 + MODULE_AUTHOR("Gerhard Engleder <eg@keba.com>"); 245 245 + MODULE_DESCRIPTION("KEBA fan controller driver"); 246 246 + MODULE_LICENSE("GPL");

+1 -1

drivers/hwmon/lm75.c

reviewed

··· 622 622 { 623 623 .rnw = true, 624 624 .len = 2, 625 625 - .data.out = data->val_buf, 625 625 + .data.in = data->val_buf, 626 626 }, 627 627 }; 628 628 int ret;

+1 -1

drivers/hwmon/lm90.c

reviewed

··· 1235 1235 1236 1236 static void lm90_alert_work(struct work_struct *__work) 1237 1237 { 1238 1238 - struct delayed_work *delayed_work = container_of(__work, struct delayed_work, work); 1238 1238 + struct delayed_work *delayed_work = to_delayed_work(__work); 1239 1239 struct lm90_data *data = container_of(delayed_work, struct lm90_data, alert_work); 1240 1240 1241 1241 /* Nothing to do if alerts are enabled */

+20 -10

drivers/hwmon/ltc2992.c

reviewed

··· 256 256 return 0; 257 257 } 258 258 259 259 - static void ltc2992_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 259 259 + static int ltc2992_gpio_set(struct gpio_chip *chip, unsigned int offset, 260 260 + int value) 260 261 { 261 262 struct ltc2992_state *st = gpiochip_get_data(chip); 262 263 unsigned long gpio_ctrl; 263 263 - int reg; 264 264 + int reg, ret; 264 265 265 266 mutex_lock(&st->gpio_mutex); 266 267 reg = ltc2992_read_reg(st, ltc2992_gpio_addr_map[offset].ctrl, 1); 267 268 if (reg < 0) { 268 269 mutex_unlock(&st->gpio_mutex); 269 269 - return; 270 270 + return reg; 270 271 } 271 272 272 273 gpio_ctrl = reg; 273 274 assign_bit(ltc2992_gpio_addr_map[offset].ctrl_bit, &gpio_ctrl, value); 274 275 275 275 - ltc2992_write_reg(st, ltc2992_gpio_addr_map[offset].ctrl, 1, gpio_ctrl); 276 276 + ret = ltc2992_write_reg(st, ltc2992_gpio_addr_map[offset].ctrl, 1, 277 277 + gpio_ctrl); 276 278 mutex_unlock(&st->gpio_mutex); 279 279 + 280 280 + return ret; 277 281 } 278 282 279 279 - static void ltc2992_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, 280 280 - unsigned long *bits) 283 283 + static int ltc2992_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, 284 284 + unsigned long *bits) 281 285 { 282 286 struct ltc2992_state *st = gpiochip_get_data(chip); 283 287 unsigned long gpio_ctrl_io = 0; 284 288 unsigned long gpio_ctrl = 0; 285 289 unsigned int gpio_nr; 290 290 + int ret; 286 291 287 292 for_each_set_bit(gpio_nr, mask, LTC2992_GPIO_NR) { 288 293 if (gpio_nr < 3) ··· 298 293 } 299 294 300 295 mutex_lock(&st->gpio_mutex); 301 301 - ltc2992_write_reg(st, LTC2992_GPIO_IO_CTRL, 1, gpio_ctrl_io); 302 302 - ltc2992_write_reg(st, LTC2992_GPIO_CTRL, 1, gpio_ctrl); 296 296 + ret = ltc2992_write_reg(st, LTC2992_GPIO_IO_CTRL, 1, gpio_ctrl_io); 297 297 + if (ret) 298 298 + goto out; 299 299 + 300 300 + ret = ltc2992_write_reg(st, LTC2992_GPIO_CTRL, 1, gpio_ctrl); 301 301 + out: 303 302 mutex_unlock(&st->gpio_mutex); 303 303 + return ret; 304 304 } 305 305 306 306 static int ltc2992_config_gpio(struct ltc2992_state *st) ··· 339 329 st->gc.ngpio = ARRAY_SIZE(st->gpio_names); 340 330 st->gc.get = ltc2992_gpio_get; 341 331 st->gc.get_multiple = ltc2992_gpio_get_multiple; 342 342 - st->gc.set = ltc2992_gpio_set; 343 343 - st->gc.set_multiple = ltc2992_gpio_set_multiple; 332 332 + st->gc.set_rv = ltc2992_gpio_set; 333 333 + st->gc.set_multiple_rv = ltc2992_gpio_set_multiple; 344 334 345 335 ret = devm_gpiochip_add_data(&st->client->dev, &st->gc, st); 346 336 if (ret)

+14 -2

drivers/hwmon/max6639.c

reviewed

··· 80 80 /* Register values initialized only once */ 81 81 u8 ppr[MAX6639_NUM_CHANNELS]; /* Pulses per rotation 0..3 for 1..4 ppr */ 82 82 u8 rpm_range[MAX6639_NUM_CHANNELS]; /* Index in above rpm_ranges table */ 83 83 + u32 target_rpm[MAX6639_NUM_CHANNELS]; 83 84 84 85 /* Optional regulator for FAN supply */ 85 86 struct regulator *reg; ··· 564 563 if (!err) 565 564 data->rpm_range[i] = rpm_range_to_reg(val); 566 565 566 566 + err = of_property_read_u32(child, "target-rpm", &val); 567 567 + if (!err) 568 568 + data->target_rpm[i] = val; 569 569 + 567 570 return 0; 568 571 } 569 572 ··· 578 573 const struct device_node *np = dev->of_node; 579 574 struct device_node *child; 580 575 int i, err; 576 576 + u8 target_duty; 581 577 582 578 /* Reset chip to default values, see below for GCONFIG setup */ 583 579 err = regmap_write(data->regmap, MAX6639_REG_GCONFIG, MAX6639_GCONFIG_POR); ··· 592 586 /* default: 4000 RPM */ 593 587 data->rpm_range[0] = 1; 594 588 data->rpm_range[1] = 1; 589 589 + data->target_rpm[0] = 4000; 590 590 + data->target_rpm[1] = 4000; 595 591 596 592 for_each_child_of_node(np, child) { 597 593 if (strcmp(child->name, "fan")) ··· 647 639 if (err) 648 640 return err; 649 641 650 650 - /* PWM 120/120 (i.e. 100%) */ 651 651 - err = regmap_write(data->regmap, MAX6639_REG_TARGTDUTY(i), 120); 642 642 + /* Set PWM based on target RPM if specified */ 643 643 + if (data->target_rpm[i] > rpm_ranges[data->rpm_range[i]]) 644 644 + data->target_rpm[i] = rpm_ranges[data->rpm_range[i]]; 645 645 + 646 646 + target_duty = 120 * data->target_rpm[i] / rpm_ranges[data->rpm_range[i]]; 647 647 + err = regmap_write(data->regmap, MAX6639_REG_TARGTDUTY(i), target_duty); 652 648 if (err) 653 649 return err; 654 650 }

+221

drivers/hwmon/max77705-hwmon.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * MAX77705 voltage and current hwmon driver. 4 4 + * 5 5 + * Copyright (C) 2025 Dzmitry Sankouski <dsankouski@gmail.com> 6 6 + */ 7 7 + 8 8 + #include <linux/err.h> 9 9 + #include <linux/hwmon-sysfs.h> 10 10 + #include <linux/hwmon.h> 11 11 + #include <linux/kernel.h> 12 12 + #include <linux/mfd/max77705-private.h> 13 13 + #include <linux/platform_device.h> 14 14 + #include <linux/regmap.h> 15 15 + 16 16 + struct channel_desc { 17 17 + u8 reg; 18 18 + u8 avg_reg; 19 19 + const char *const label; 20 20 + // register resolution. nano Volts for voltage, nano Amperes for current 21 21 + u32 resolution; 22 22 + }; 23 23 + 24 24 + static const struct channel_desc current_channel_desc[] = { 25 25 + { 26 26 + .reg = IIN_REG, 27 27 + .label = "IIN_REG", 28 28 + .resolution = 125000 29 29 + }, 30 30 + { 31 31 + .reg = ISYS_REG, 32 32 + .avg_reg = AVGISYS_REG, 33 33 + .label = "ISYS_REG", 34 34 + .resolution = 312500 35 35 + } 36 36 + }; 37 37 + 38 38 + static const struct channel_desc voltage_channel_desc[] = { 39 39 + { 40 40 + .reg = VBYP_REG, 41 41 + .label = "VBYP_REG", 42 42 + .resolution = 427246 43 43 + }, 44 44 + { 45 45 + .reg = VSYS_REG, 46 46 + .label = "VSYS_REG", 47 47 + .resolution = 156250 48 48 + } 49 49 + }; 50 50 + 51 51 + static int max77705_read_and_convert(struct regmap *regmap, u8 reg, u32 res, 52 52 + bool is_signed, long *val) 53 53 + { 54 54 + int ret; 55 55 + u32 regval; 56 56 + 57 57 + ret = regmap_read(regmap, reg, &regval); 58 58 + if (ret < 0) 59 59 + return ret; 60 60 + 61 61 + if (is_signed) 62 62 + *val = mult_frac((long)sign_extend32(regval, 15), res, 1000000); 63 63 + else 64 64 + *val = mult_frac((long)regval, res, 1000000); 65 65 + 66 66 + return 0; 67 67 + } 68 68 + 69 69 + static umode_t max77705_is_visible(const void *data, 70 70 + enum hwmon_sensor_types type, 71 71 + u32 attr, int channel) 72 72 + { 73 73 + switch (type) { 74 74 + case hwmon_in: 75 75 + switch (attr) { 76 76 + case hwmon_in_input: 77 77 + case hwmon_in_label: 78 78 + return 0444; 79 79 + default: 80 80 + break; 81 81 + } 82 82 + break; 83 83 + case hwmon_curr: 84 84 + switch (attr) { 85 85 + case hwmon_curr_input: 86 86 + case hwmon_in_label: 87 87 + return 0444; 88 88 + case hwmon_curr_average: 89 89 + if (current_channel_desc[channel].avg_reg) 90 90 + return 0444; 91 91 + break; 92 92 + default: 93 93 + break; 94 94 + } 95 95 + break; 96 96 + default: 97 97 + break; 98 98 + } 99 99 + return 0; 100 100 + } 101 101 + 102 102 + static int max77705_read_string(struct device *dev, enum hwmon_sensor_types type, u32 attr, 103 103 + int channel, const char **buf) 104 104 + { 105 105 + switch (type) { 106 106 + case hwmon_curr: 107 107 + switch (attr) { 108 108 + case hwmon_in_label: 109 109 + *buf = current_channel_desc[channel].label; 110 110 + return 0; 111 111 + default: 112 112 + return -EOPNOTSUPP; 113 113 + } 114 114 + 115 115 + case hwmon_in: 116 116 + switch (attr) { 117 117 + case hwmon_in_label: 118 118 + *buf = voltage_channel_desc[channel].label; 119 119 + return 0; 120 120 + default: 121 121 + return -EOPNOTSUPP; 122 122 + } 123 123 + default: 124 124 + return -EOPNOTSUPP; 125 125 + } 126 126 + } 127 127 + 128 128 + static int max77705_read(struct device *dev, enum hwmon_sensor_types type, 129 129 + u32 attr, int channel, long *val) 130 130 + { 131 131 + struct regmap *regmap = dev_get_drvdata(dev); 132 132 + u8 reg; 133 133 + u32 res; 134 134 + 135 135 + switch (type) { 136 136 + case hwmon_curr: 137 137 + switch (attr) { 138 138 + case hwmon_curr_input: 139 139 + reg = current_channel_desc[channel].reg; 140 140 + res = current_channel_desc[channel].resolution; 141 141 + 142 142 + return max77705_read_and_convert(regmap, reg, res, true, val); 143 143 + case hwmon_curr_average: 144 144 + reg = current_channel_desc[channel].avg_reg; 145 145 + res = current_channel_desc[channel].resolution; 146 146 + 147 147 + return max77705_read_and_convert(regmap, reg, res, true, val); 148 148 + default: 149 149 + return -EOPNOTSUPP; 150 150 + } 151 151 + 152 152 + case hwmon_in: 153 153 + switch (attr) { 154 154 + case hwmon_in_input: 155 155 + reg = voltage_channel_desc[channel].reg; 156 156 + res = voltage_channel_desc[channel].resolution; 157 157 + 158 158 + return max77705_read_and_convert(regmap, reg, res, false, val); 159 159 + default: 160 160 + return -EOPNOTSUPP; 161 161 + } 162 162 + default: 163 163 + return -EOPNOTSUPP; 164 164 + } 165 165 + 166 166 + return 0; 167 167 + } 168 168 + 169 169 + static const struct hwmon_ops max77705_hwmon_ops = { 170 170 + .is_visible = max77705_is_visible, 171 171 + .read = max77705_read, 172 172 + .read_string = max77705_read_string, 173 173 + }; 174 174 + 175 175 + static const struct hwmon_channel_info *max77705_info[] = { 176 176 + HWMON_CHANNEL_INFO(in, 177 177 + HWMON_I_INPUT | HWMON_I_LABEL, 178 178 + HWMON_I_INPUT | HWMON_I_LABEL 179 179 + ), 180 180 + HWMON_CHANNEL_INFO(curr, 181 181 + HWMON_C_INPUT | HWMON_C_LABEL, 182 182 + HWMON_C_INPUT | HWMON_C_AVERAGE | HWMON_C_LABEL 183 183 + ), 184 184 + NULL 185 185 + }; 186 186 + 187 187 + static const struct hwmon_chip_info max77705_chip_info = { 188 188 + .ops = &max77705_hwmon_ops, 189 189 + .info = max77705_info, 190 190 + }; 191 191 + 192 192 + static int max77705_hwmon_probe(struct platform_device *pdev) 193 193 + { 194 194 + struct device *hwmon_dev; 195 195 + struct regmap *regmap; 196 196 + 197 197 + regmap = dev_get_regmap(pdev->dev.parent, NULL); 198 198 + if (!regmap) 199 199 + return -ENODEV; 200 200 + 201 201 + hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev, "max77705", regmap, 202 202 + &max77705_chip_info, NULL); 203 203 + if (IS_ERR(hwmon_dev)) 204 204 + return dev_err_probe(&pdev->dev, PTR_ERR(hwmon_dev), 205 205 + "Unable to register hwmon device\n"); 206 206 + 207 207 + return 0; 208 208 + }; 209 209 + 210 210 + static struct platform_driver max77705_hwmon_driver = { 211 211 + .driver = { 212 212 + .name = "max77705-hwmon", 213 213 + }, 214 214 + .probe = max77705_hwmon_probe, 215 215 + }; 216 216 + 217 217 + module_platform_driver(max77705_hwmon_driver); 218 218 + 219 219 + MODULE_AUTHOR("Dzmitry Sankouski <dsankouski@gmail.com>"); 220 220 + MODULE_DESCRIPTION("MAX77705 monitor driver"); 221 221 + MODULE_LICENSE("GPL");

+1 -1

drivers/hwmon/nct7363.c

reviewed

··· 391 391 .val_bits = 8, 392 392 .use_single_read = true, 393 393 .use_single_write = true, 394 394 - .cache_type = REGCACHE_RBTREE, 394 394 + .cache_type = REGCACHE_MAPLE, 395 395 .volatile_reg = nct7363_regmap_is_volatile, 396 396 }; 397 397

+18

drivers/hwmon/pmbus/Kconfig

reviewed

··· 218 218 If you say yes here you get regulator support for National 219 219 Semiconductor LM25066, LM5064, and LM5066. 220 220 221 221 + config SENSORS_LT3074 222 222 + tristate "Analog Devices LT3074" 223 223 + help 224 224 + If you say yes here you get hardware monitoring support for Analog 225 225 + Devices LT3074. 226 226 + 227 227 + This driver can also be built as a module. If so, the module will 228 228 + be called lt3074. 229 229 + 230 230 + config SENSORS_LT3074_REGULATOR 231 231 + tristate "Regulator support for LT3074" 232 232 + depends on SENSORS_LT3074 && REGULATOR 233 233 + help 234 234 + If you say yes here you get regulator support for Analog Devices 235 235 + LT3074. The LT3074 is a low voltage, ultralow noise, high PSRR, 236 236 + dropout linear regulator. The device supplies up to 3A with a 237 237 + typical dropout voltage of 45mV. 238 238 + 221 239 config SENSORS_LT7182S 222 240 tristate "Analog Devices LT7182S" 223 241 help

+1

drivers/hwmon/pmbus/Makefile

reviewed

··· 23 23 obj-$(CONFIG_SENSORS_IRPS5401) += irps5401.o 24 24 obj-$(CONFIG_SENSORS_ISL68137) += isl68137.o 25 25 obj-$(CONFIG_SENSORS_LM25066) += lm25066.o 26 26 + obj-$(CONFIG_SENSORS_LT3074) += lt3074.o 26 27 obj-$(CONFIG_SENSORS_LT7182S) += lt7182s.o 27 28 obj-$(CONFIG_SENSORS_LTC2978) += ltc2978.o 28 29 obj-$(CONFIG_SENSORS_LTC3815) += ltc3815.o

+1 -1

drivers/hwmon/pmbus/lm25066.c

reviewed

··· 437 437 438 438 #if IS_ENABLED(CONFIG_SENSORS_LM25066_REGULATOR) 439 439 static const struct regulator_desc lm25066_reg_desc[] = { 440 440 - PMBUS_REGULATOR_ONE("vout"), 440 440 + PMBUS_REGULATOR_ONE_NODE("vout"), 441 441 }; 442 442 #endif 443 443

+122

drivers/hwmon/pmbus/lt3074.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Hardware monitoring driver for Analog Devices LT3074 4 4 + * 5 5 + * Copyright (C) 2025 Analog Devices, Inc. 6 6 + */ 7 7 + #include <linux/err.h> 8 8 + #include <linux/i2c.h> 9 9 + #include <linux/mod_devicetable.h> 10 10 + #include <linux/module.h> 11 11 + 12 12 + #include "pmbus.h" 13 13 + 14 14 + #define LT3074_MFR_READ_VBIAS 0xc6 15 15 + #define LT3074_MFR_BIAS_OV_WARN_LIMIT 0xc7 16 16 + #define LT3074_MFR_BIAS_UV_WARN_LIMIT 0xc8 17 17 + #define LT3074_MFR_SPECIAL_ID 0xe7 18 18 + 19 19 + #define LT3074_SPECIAL_ID_VALUE 0x1c1d 20 20 + 21 21 + static const struct regulator_desc __maybe_unused lt3074_reg_desc[] = { 22 22 + PMBUS_REGULATOR_ONE("regulator"), 23 23 + }; 24 24 + 25 25 + static int lt3074_read_word_data(struct i2c_client *client, int page, 26 26 + int phase, int reg) 27 27 + { 28 28 + switch (reg) { 29 29 + case PMBUS_VIRT_READ_VMON: 30 30 + return pmbus_read_word_data(client, page, phase, 31 31 + LT3074_MFR_READ_VBIAS); 32 32 + case PMBUS_VIRT_VMON_UV_WARN_LIMIT: 33 33 + return pmbus_read_word_data(client, page, phase, 34 34 + LT3074_MFR_BIAS_UV_WARN_LIMIT); 35 35 + case PMBUS_VIRT_VMON_OV_WARN_LIMIT: 36 36 + return pmbus_read_word_data(client, page, phase, 37 37 + LT3074_MFR_BIAS_OV_WARN_LIMIT); 38 38 + default: 39 39 + return -ENODATA; 40 40 + } 41 41 + } 42 42 + 43 43 + static int lt3074_write_word_data(struct i2c_client *client, int page, 44 44 + int reg, u16 word) 45 45 + { 46 46 + switch (reg) { 47 47 + case PMBUS_VIRT_VMON_UV_WARN_LIMIT: 48 48 + return pmbus_write_word_data(client, 0, 49 49 + LT3074_MFR_BIAS_UV_WARN_LIMIT, 50 50 + word); 51 51 + case PMBUS_VIRT_VMON_OV_WARN_LIMIT: 52 52 + return pmbus_write_word_data(client, 0, 53 53 + LT3074_MFR_BIAS_OV_WARN_LIMIT, 54 54 + word); 55 55 + default: 56 56 + return -ENODATA; 57 57 + } 58 58 + } 59 59 + 60 60 + static struct pmbus_driver_info lt3074_info = { 61 61 + .pages = 1, 62 62 + .format[PSC_VOLTAGE_IN] = linear, 63 63 + .format[PSC_VOLTAGE_OUT] = linear, 64 64 + .format[PSC_CURRENT_OUT] = linear, 65 65 + .format[PSC_TEMPERATURE] = linear, 66 66 + .func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_VOUT | PMBUS_HAVE_IOUT | 67 67 + PMBUS_HAVE_TEMP | PMBUS_HAVE_VMON | 68 68 + PMBUS_HAVE_STATUS_VOUT | PMBUS_HAVE_STATUS_IOUT | 69 69 + PMBUS_HAVE_STATUS_INPUT | PMBUS_HAVE_STATUS_TEMP, 70 70 + .read_word_data = lt3074_read_word_data, 71 71 + .write_word_data = lt3074_write_word_data, 72 72 + #if IS_ENABLED(CONFIG_SENSORS_LT3074_REGULATOR) 73 73 + .num_regulators = 1, 74 74 + .reg_desc = lt3074_reg_desc, 75 75 + #endif 76 76 + }; 77 77 + 78 78 + static int lt3074_probe(struct i2c_client *client) 79 79 + { 80 80 + int ret; 81 81 + struct device *dev = &client->dev; 82 82 + 83 83 + if (!i2c_check_functionality(client->adapter, 84 84 + I2C_FUNC_SMBUS_READ_WORD_DATA)) 85 85 + return -ENODEV; 86 86 + 87 87 + ret = i2c_smbus_read_word_data(client, LT3074_MFR_SPECIAL_ID); 88 88 + if (ret < 0) 89 89 + return dev_err_probe(dev, ret, "Failed to read ID\n"); 90 90 + 91 91 + if (ret != LT3074_SPECIAL_ID_VALUE) 92 92 + return dev_err_probe(dev, -ENODEV, "ID mismatch\n"); 93 93 + 94 94 + return pmbus_do_probe(client, &lt3074_info); 95 95 + } 96 96 + 97 97 + static const struct i2c_device_id lt3074_id[] = { 98 98 + { "lt3074", 0 }, 99 99 + {} 100 100 + }; 101 101 + MODULE_DEVICE_TABLE(i2c, lt3074_id); 102 102 + 103 103 + static const struct of_device_id __maybe_unused lt3074_of_match[] = { 104 104 + { .compatible = "adi,lt3074" }, 105 105 + {} 106 106 + }; 107 107 + MODULE_DEVICE_TABLE(of, lt3074_of_match); 108 108 + 109 109 + static struct i2c_driver lt3074_driver = { 110 110 + .driver = { 111 111 + .name = "lt3074", 112 112 + .of_match_table = of_match_ptr(lt3074_of_match), 113 113 + }, 114 114 + .probe = lt3074_probe, 115 115 + .id_table = lt3074_id, 116 116 + }; 117 117 + module_i2c_driver(lt3074_driver); 118 118 + 119 119 + MODULE_AUTHOR("Cedric Encarnacion <cedricjustine.encarnacion@analog.com>"); 120 120 + MODULE_DESCRIPTION("PMBus driver for Analog Devices LT3074"); 121 121 + MODULE_LICENSE("GPL"); 122 122 + MODULE_IMPORT_NS("PMBUS");

+112 -7

drivers/hwmon/pmbus/max34440.c

reviewed

··· 12 12 #include <linux/init.h> 13 13 #include <linux/err.h> 14 14 #include <linux/i2c.h> 15 15 + #include <linux/delay.h> 15 16 #include "pmbus.h" 16 17 17 17 - enum chips { max34440, max34441, max34446, max34451, max34460, max34461 }; 18 18 + enum chips { 19 19 + adpm12160, 20 20 + max34440, 21 21 + max34441, 22 22 + max34446, 23 23 + max34451, 24 24 + max34460, 25 25 + max34461, 26 26 + }; 27 27 + 28 28 + /* 29 29 + * Firmware is sometimes not ready if we try and read the 30 30 + * data from the page immediately after setting. Maxim 31 31 + * recommends 50us delay due to the chip failing to clock 32 32 + * stretch long enough here. 33 33 + */ 34 34 + #define MAX34440_PAGE_CHANGE_DELAY 50 18 35 19 36 #define MAX34440_MFR_VOUT_PEAK 0xd4 20 37 #define MAX34440_MFR_IOUT_PEAK 0xd5 ··· 51 34 /* 52 35 * The whole max344* family have IOUT_OC_WARN_LIMIT and IOUT_OC_FAULT_LIMIT 53 36 * swapped from the standard pmbus spec addresses. 37 37 + * For max34451, version MAX34451ETNA6+ and later has this issue fixed. 54 38 */ 55 39 #define MAX34440_IOUT_OC_WARN_LIMIT 0x46 56 40 #define MAX34440_IOUT_OC_FAULT_LIMIT 0x4A 41 41 + 42 42 + #define MAX34451ETNA6_MFR_REV 0x0012 57 43 58 44 #define MAX34451_MFR_CHANNEL_CONFIG 0xe4 59 45 #define MAX34451_MFR_CHANNEL_CONFIG_SEL_MASK 0x3f ··· 64 44 struct max34440_data { 65 45 int id; 66 46 struct pmbus_driver_info info; 47 47 + u8 iout_oc_warn_limit; 48 48 + u8 iout_oc_fault_limit; 67 49 }; 68 50 69 51 #define to_max34440_data(x) container_of(x, struct max34440_data, info) ··· 82 60 switch (reg) { 83 61 case PMBUS_IOUT_OC_FAULT_LIMIT: 84 62 ret = pmbus_read_word_data(client, page, phase, 85 85 - MAX34440_IOUT_OC_FAULT_LIMIT); 63 63 + data->iout_oc_fault_limit); 86 64 break; 87 65 case PMBUS_IOUT_OC_WARN_LIMIT: 88 66 ret = pmbus_read_word_data(client, page, phase, 89 89 - MAX34440_IOUT_OC_WARN_LIMIT); 67 67 + data->iout_oc_warn_limit); 90 68 break; 91 69 case PMBUS_VIRT_READ_VOUT_MIN: 92 70 ret = pmbus_read_word_data(client, page, phase, ··· 97 75 MAX34440_MFR_VOUT_PEAK); 98 76 break; 99 77 case PMBUS_VIRT_READ_IOUT_AVG: 100 100 - if (data->id != max34446 && data->id != max34451) 78 78 + if (data->id != max34446 && data->id != max34451 && 79 79 + data->id != adpm12160) 101 80 return -ENXIO; 102 81 ret = pmbus_read_word_data(client, page, phase, 103 82 MAX34446_MFR_IOUT_AVG); ··· 156 133 157 134 switch (reg) { 158 135 case PMBUS_IOUT_OC_FAULT_LIMIT: 159 159 - ret = pmbus_write_word_data(client, page, MAX34440_IOUT_OC_FAULT_LIMIT, 136 136 + ret = pmbus_write_word_data(client, page, data->iout_oc_fault_limit, 160 137 word); 161 138 break; 162 139 case PMBUS_IOUT_OC_WARN_LIMIT: 163 163 - ret = pmbus_write_word_data(client, page, MAX34440_IOUT_OC_WARN_LIMIT, 140 140 + ret = pmbus_write_word_data(client, page, data->iout_oc_warn_limit, 164 141 word); 165 142 break; 166 143 case PMBUS_VIRT_RESET_POUT_HISTORY: ··· 182 159 case PMBUS_VIRT_RESET_IOUT_HISTORY: 183 160 ret = pmbus_write_word_data(client, page, 184 161 MAX34440_MFR_IOUT_PEAK, 0); 185 185 - if (!ret && (data->id == max34446 || data->id == max34451)) 162 162 + if (!ret && (data->id == max34446 || data->id == max34451 || 163 163 + data->id == adpm12160)) 186 164 ret = pmbus_write_word_data(client, page, 187 165 MAX34446_MFR_IOUT_AVG, 0); 188 166 ··· 259 235 */ 260 236 261 237 int page, rv; 238 238 + bool max34451_na6 = false; 239 239 + 240 240 + rv = i2c_smbus_read_word_data(client, PMBUS_MFR_REVISION); 241 241 + if (rv < 0) 242 242 + return rv; 243 243 + 244 244 + if (rv >= MAX34451ETNA6_MFR_REV) { 245 245 + max34451_na6 = true; 246 246 + data->info.format[PSC_VOLTAGE_IN] = direct; 247 247 + data->info.format[PSC_CURRENT_IN] = direct; 248 248 + data->info.m[PSC_VOLTAGE_IN] = 1; 249 249 + data->info.b[PSC_VOLTAGE_IN] = 0; 250 250 + data->info.R[PSC_VOLTAGE_IN] = 3; 251 251 + data->info.m[PSC_CURRENT_IN] = 1; 252 252 + data->info.b[PSC_CURRENT_IN] = 0; 253 253 + data->info.R[PSC_CURRENT_IN] = 2; 254 254 + data->iout_oc_fault_limit = PMBUS_IOUT_OC_FAULT_LIMIT; 255 255 + data->iout_oc_warn_limit = PMBUS_IOUT_OC_WARN_LIMIT; 256 256 + } 262 257 263 258 for (page = 0; page < 16; page++) { 264 259 rv = i2c_smbus_write_byte_data(client, PMBUS_PAGE, page); 260 260 + fsleep(MAX34440_PAGE_CHANGE_DELAY); 265 261 if (rv < 0) 266 262 return rv; 267 263 ··· 295 251 case 0x20: 296 252 data->info.func[page] = PMBUS_HAVE_VOUT | 297 253 PMBUS_HAVE_STATUS_VOUT; 254 254 + 255 255 + if (max34451_na6) 256 256 + data->info.func[page] |= PMBUS_HAVE_VIN | 257 257 + PMBUS_HAVE_STATUS_INPUT; 298 258 break; 299 259 case 0x21: 300 260 data->info.func[page] = PMBUS_HAVE_VOUT; 261 261 + 262 262 + if (max34451_na6) 263 263 + data->info.func[page] |= PMBUS_HAVE_VIN; 301 264 break; 302 265 case 0x22: 303 266 data->info.func[page] = PMBUS_HAVE_IOUT | 304 267 PMBUS_HAVE_STATUS_IOUT; 268 268 + 269 269 + if (max34451_na6) 270 270 + data->info.func[page] |= PMBUS_HAVE_IIN | 271 271 + PMBUS_HAVE_STATUS_INPUT; 305 272 break; 306 273 case 0x23: 307 274 data->info.func[page] = PMBUS_HAVE_IOUT; 275 275 + 276 276 + if (max34451_na6) 277 277 + data->info.func[page] |= PMBUS_HAVE_IIN; 308 278 break; 309 279 default: 310 280 break; ··· 329 271 } 330 272 331 273 static struct pmbus_driver_info max34440_info[] = { 274 274 + [adpm12160] = { 275 275 + .pages = 19, 276 276 + .format[PSC_VOLTAGE_IN] = direct, 277 277 + .format[PSC_VOLTAGE_OUT] = direct, 278 278 + .format[PSC_CURRENT_IN] = direct, 279 279 + .format[PSC_CURRENT_OUT] = direct, 280 280 + .format[PSC_TEMPERATURE] = direct, 281 281 + .m[PSC_VOLTAGE_IN] = 1, 282 282 + .b[PSC_VOLTAGE_IN] = 0, 283 283 + .R[PSC_VOLTAGE_IN] = 0, 284 284 + .m[PSC_VOLTAGE_OUT] = 1, 285 285 + .b[PSC_VOLTAGE_OUT] = 0, 286 286 + .R[PSC_VOLTAGE_OUT] = 0, 287 287 + .m[PSC_CURRENT_IN] = 1, 288 288 + .b[PSC_CURRENT_IN] = 0, 289 289 + .R[PSC_CURRENT_IN] = 2, 290 290 + .m[PSC_CURRENT_OUT] = 1, 291 291 + .b[PSC_CURRENT_OUT] = 0, 292 292 + .R[PSC_CURRENT_OUT] = 2, 293 293 + .m[PSC_TEMPERATURE] = 1, 294 294 + .b[PSC_TEMPERATURE] = 0, 295 295 + .R[PSC_TEMPERATURE] = 2, 296 296 + /* absent func below [18] are not for monitoring */ 297 297 + .func[2] = PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT, 298 298 + .func[4] = PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT, 299 299 + .func[5] = PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT, 300 300 + .func[6] = PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT, 301 301 + .func[7] = PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT, 302 302 + .func[8] = PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT, 303 303 + .func[9] = PMBUS_HAVE_VIN | PMBUS_HAVE_STATUS_INPUT, 304 304 + .func[10] = PMBUS_HAVE_IIN | PMBUS_HAVE_STATUS_INPUT, 305 305 + .func[18] = PMBUS_HAVE_TEMP | PMBUS_HAVE_STATUS_TEMP, 306 306 + .read_word_data = max34440_read_word_data, 307 307 + .write_word_data = max34440_write_word_data, 308 308 + }, 332 309 [max34440] = { 333 310 .pages = 14, 334 311 .format[PSC_VOLTAGE_IN] = direct, ··· 405 312 .read_byte_data = max34440_read_byte_data, 406 313 .read_word_data = max34440_read_word_data, 407 314 .write_word_data = max34440_write_word_data, 315 315 + .page_change_delay = MAX34440_PAGE_CHANGE_DELAY, 408 316 }, 409 317 [max34441] = { 410 318 .pages = 12, ··· 449 355 .read_byte_data = max34440_read_byte_data, 450 356 .read_word_data = max34440_read_word_data, 451 357 .write_word_data = max34440_write_word_data, 358 358 + .page_change_delay = MAX34440_PAGE_CHANGE_DELAY, 452 359 }, 453 360 [max34446] = { 454 361 .pages = 7, ··· 487 392 .read_byte_data = max34440_read_byte_data, 488 393 .read_word_data = max34440_read_word_data, 489 394 .write_word_data = max34440_write_word_data, 395 395 + .page_change_delay = MAX34440_PAGE_CHANGE_DELAY, 490 396 }, 491 397 [max34451] = { 492 398 .pages = 21, ··· 511 415 .func[20] = PMBUS_HAVE_TEMP | PMBUS_HAVE_STATUS_TEMP, 512 416 .read_word_data = max34440_read_word_data, 513 417 .write_word_data = max34440_write_word_data, 418 418 + .page_change_delay = MAX34440_PAGE_CHANGE_DELAY, 514 419 }, 515 420 [max34460] = { 516 421 .pages = 18, ··· 542 445 .func[17] = PMBUS_HAVE_TEMP | PMBUS_HAVE_STATUS_TEMP, 543 446 .read_word_data = max34440_read_word_data, 544 447 .write_word_data = max34440_write_word_data, 448 448 + .page_change_delay = MAX34440_PAGE_CHANGE_DELAY, 545 449 }, 546 450 [max34461] = { 547 451 .pages = 23, ··· 578 480 .func[21] = PMBUS_HAVE_TEMP | PMBUS_HAVE_STATUS_TEMP, 579 481 .read_word_data = max34440_read_word_data, 580 482 .write_word_data = max34440_write_word_data, 483 483 + .page_change_delay = MAX34440_PAGE_CHANGE_DELAY, 581 484 }, 582 485 }; 583 486 ··· 593 494 return -ENOMEM; 594 495 data->id = i2c_match_id(max34440_id, client)->driver_data; 595 496 data->info = max34440_info[data->id]; 497 497 + data->iout_oc_fault_limit = MAX34440_IOUT_OC_FAULT_LIMIT; 498 498 + data->iout_oc_warn_limit = MAX34440_IOUT_OC_WARN_LIMIT; 596 499 597 500 if (data->id == max34451) { 598 501 rv = max34451_set_supported_funcs(client, data); 599 502 if (rv) 600 503 return rv; 504 504 + } else if (data->id == adpm12160) { 505 505 + data->iout_oc_fault_limit = PMBUS_IOUT_OC_FAULT_LIMIT; 506 506 + data->iout_oc_warn_limit = PMBUS_IOUT_OC_WARN_LIMIT; 601 507 } 602 508 603 509 return pmbus_do_probe(client, &data->info); 604 510 } 605 511 606 512 static const struct i2c_device_id max34440_id[] = { 513 513 + {"adpm12160", adpm12160}, 607 514 {"max34440", max34440}, 608 515 {"max34441", max34441}, 609 516 {"max34446", max34446},

+2 -2

drivers/hwmon/pmbus/mpq7932.c

reviewed

··· 51 51 }; 52 52 53 53 static const struct regulator_desc mpq7932_regulators_desc_one[] = { 54 54 - PMBUS_REGULATOR_STEP_ONE("buck", MPQ7932_N_VOLTAGES, 55 55 - MPQ7932_UV_STEP, MPQ7932_BUCK_UV_MIN), 54 54 + PMBUS_REGULATOR_STEP_ONE_NODE("buck", MPQ7932_N_VOLTAGES, 55 55 + MPQ7932_UV_STEP, MPQ7932_BUCK_UV_MIN), 56 56 }; 57 57 #endif 58 58

+83 -8

drivers/hwmon/pmbus/mpq8785.c

reviewed

··· 4 4 */ 5 5 6 6 #include <linux/i2c.h> 7 7 + #include <linux/bitops.h> 7 8 #include <linux/module.h> 9 9 + #include <linux/property.h> 8 10 #include <linux/of_device.h> 9 11 #include "pmbus.h" 12 12 + 13 13 + #define MPM82504_READ_TEMPERATURE_1_SIGN_POS 9 14 14 + 15 15 + enum chips { mpm3695, mpm3695_25, mpm82504, mpq8785 }; 16 16 + 17 17 + static u16 voltage_scale_loop_max_val[] = { 18 18 + [mpm3695] = GENMASK(9, 0), 19 19 + [mpm3695_25] = GENMASK(11, 0), 20 20 + [mpm82504] = GENMASK(9, 0), 21 21 + [mpq8785] = GENMASK(10, 0), 22 22 + }; 10 23 11 24 static int mpq8785_identify(struct i2c_client *client, 12 25 struct pmbus_driver_info *info) ··· 47 34 return 0; 48 35 }; 49 36 37 37 + static int mpm82504_read_word_data(struct i2c_client *client, int page, 38 38 + int phase, int reg) 39 39 + { 40 40 + int ret; 41 41 + 42 42 + ret = pmbus_read_word_data(client, page, phase, reg); 43 43 + 44 44 + if (ret < 0 || reg != PMBUS_READ_TEMPERATURE_1) 45 45 + return ret; 46 46 + 47 47 + /* Fix PMBUS_READ_TEMPERATURE_1 signedness */ 48 48 + return sign_extend32(ret, MPM82504_READ_TEMPERATURE_1_SIGN_POS) & 0xffff; 49 49 + } 50 50 + 50 51 static struct pmbus_driver_info mpq8785_info = { 51 52 .pages = 1, 52 53 .format[PSC_VOLTAGE_IN] = direct, ··· 80 53 PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT | 81 54 PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT | 82 55 PMBUS_HAVE_TEMP | PMBUS_HAVE_STATUS_TEMP, 83 83 - .identify = mpq8785_identify, 84 84 - }; 85 85 - 86 86 - static int mpq8785_probe(struct i2c_client *client) 87 87 - { 88 88 - return pmbus_do_probe(client, &mpq8785_info); 89 56 }; 90 57 91 58 static const struct i2c_device_id mpq8785_id[] = { 92 92 - { "mpq8785" }, 59 59 + { "mpm3695", mpm3695 }, 60 60 + { "mpm3695-25", mpm3695_25 }, 61 61 + { "mpm82504", mpm82504 }, 62 62 + { "mpq8785", mpq8785 }, 93 63 { }, 94 64 }; 95 65 MODULE_DEVICE_TABLE(i2c, mpq8785_id); 96 66 97 67 static const struct of_device_id __maybe_unused mpq8785_of_match[] = { 98 98 - { .compatible = "mps,mpq8785" }, 68 68 + { .compatible = "mps,mpm3695", .data = (void *)mpm3695 }, 69 69 + { .compatible = "mps,mpm3695-25", .data = (void *)mpm3695_25 }, 70 70 + { .compatible = "mps,mpm82504", .data = (void *)mpm82504 }, 71 71 + { .compatible = "mps,mpq8785", .data = (void *)mpq8785 }, 99 72 {} 100 73 }; 101 74 MODULE_DEVICE_TABLE(of, mpq8785_of_match); 75 75 + 76 76 + static int mpq8785_probe(struct i2c_client *client) 77 77 + { 78 78 + struct device *dev = &client->dev; 79 79 + struct pmbus_driver_info *info; 80 80 + enum chips chip_id; 81 81 + u32 voltage_scale; 82 82 + int ret; 83 83 + 84 84 + info = devm_kmemdup(dev, &mpq8785_info, sizeof(*info), GFP_KERNEL); 85 85 + if (!info) 86 86 + return -ENOMEM; 87 87 + 88 88 + if (dev->of_node) 89 89 + chip_id = (kernel_ulong_t)of_device_get_match_data(dev); 90 90 + else 91 91 + chip_id = (kernel_ulong_t)i2c_get_match_data(client); 92 92 + 93 93 + switch (chip_id) { 94 94 + case mpm3695: 95 95 + case mpm3695_25: 96 96 + case mpm82504: 97 97 + info->format[PSC_VOLTAGE_OUT] = direct; 98 98 + info->m[PSC_VOLTAGE_OUT] = 8; 99 99 + info->b[PSC_VOLTAGE_OUT] = 0; 100 100 + info->R[PSC_VOLTAGE_OUT] = 2; 101 101 + info->read_word_data = mpm82504_read_word_data; 102 102 + break; 103 103 + case mpq8785: 104 104 + info->identify = mpq8785_identify; 105 105 + break; 106 106 + default: 107 107 + return -ENODEV; 108 108 + } 109 109 + 110 110 + if (!device_property_read_u32(dev, "mps,vout-fb-divider-ratio-permille", 111 111 + &voltage_scale)) { 112 112 + if (voltage_scale > voltage_scale_loop_max_val[chip_id]) 113 113 + return -EINVAL; 114 114 + 115 115 + ret = i2c_smbus_write_word_data(client, PMBUS_VOUT_SCALE_LOOP, 116 116 + voltage_scale); 117 117 + if (ret) 118 118 + return ret; 119 119 + } 120 120 + 121 121 + return pmbus_do_probe(client, info); 122 122 + }; 102 123 103 124 static struct i2c_driver mpq8785_driver = { 104 125 .driver = {

+16 -3

drivers/hwmon/pmbus/pmbus.h

reviewed

··· 482 482 */ 483 483 int access_delay; /* in microseconds */ 484 484 int write_delay; /* in microseconds */ 485 485 + int page_change_delay; /* in microseconds */ 485 486 }; 486 487 487 488 /* Regulator ops */ ··· 509 508 510 509 #define PMBUS_REGULATOR(_name, _id) PMBUS_REGULATOR_STEP(_name, _id, 0, 0, 0) 511 510 512 512 - #define PMBUS_REGULATOR_STEP_ONE(_name, _voltages, _step, _min_uV) \ 511 511 + #define __PMBUS_REGULATOR_STEP_ONE(_name, _node, _voltages, _step, _min_uV) \ 513 512 { \ 514 513 .name = (_name), \ 515 514 .of_match = of_match_ptr(_name), \ 516 516 - .regulators_node = of_match_ptr("regulators"), \ 515 515 + .regulators_node = of_match_ptr(_node), \ 517 516 .ops = &pmbus_regulator_ops, \ 518 517 .type = REGULATOR_VOLTAGE, \ 519 518 .owner = THIS_MODULE, \ ··· 523 522 .init_cb = pmbus_regulator_init_cb, \ 524 523 } 525 524 526 526 - #define PMBUS_REGULATOR_ONE(_name) PMBUS_REGULATOR_STEP_ONE(_name, 0, 0, 0) 525 525 + /* 526 526 + * _NODE macros are defined for historic reasons and MUST NOT be used in new 527 527 + * drivers. 528 528 + */ 529 529 + #define PMBUS_REGULATOR_STEP_ONE_NODE(_name, _voltages, _step, _min_uV) \ 530 530 + __PMBUS_REGULATOR_STEP_ONE(_name, "regulators", _voltages, _step, _min_uV) 531 531 + 532 532 + #define PMBUS_REGULATOR_ONE_NODE(_name) PMBUS_REGULATOR_STEP_ONE_NODE(_name, 0, 0, 0) 533 533 + 534 534 + #define PMBUS_REGULATOR_STEP_ONE(_name, _voltages, _step, _min_uV) \ 535 535 + __PMBUS_REGULATOR_STEP_ONE(_name, NULL, _voltages, _step, _min_uV) 536 536 + 537 537 + #define PMBUS_REGULATOR_ONE(_name) PMBUS_REGULATOR_STEP_ONE(_name, 0, 0, 0) 527 538 528 539 /* Function declarations */ 529 540

+35 -34

drivers/hwmon/pmbus/pmbus_core.c

reviewed

··· 32 32 #define PMBUS_ATTR_ALLOC_SIZE 32 33 33 #define PMBUS_NAME_SIZE 24 34 34 35 35 + /* 36 36 + * The type of operation used for picking the delay between 37 37 + * successive pmbus operations. 38 38 + */ 39 39 + #define PMBUS_OP_WRITE BIT(0) 40 40 + #define PMBUS_OP_PAGE_CHANGE BIT(1) 41 41 + 35 42 static int wp = -1; 36 43 module_param(wp, int, 0444); 37 44 ··· 120 113 121 114 int vout_low[PMBUS_PAGES]; /* voltage low margin */ 122 115 int vout_high[PMBUS_PAGES]; /* voltage high margin */ 123 123 - ktime_t write_time; /* Last SMBUS write timestamp */ 124 124 - ktime_t access_time; /* Last SMBUS access timestamp */ 116 116 + 117 117 + ktime_t next_access_backoff; /* Wait until at least this time */ 125 118 }; 126 119 127 120 struct pmbus_debugfs_entry { ··· 176 169 static void pmbus_wait(struct i2c_client *client) 177 170 { 178 171 struct pmbus_data *data = i2c_get_clientdata(client); 179 179 - const struct pmbus_driver_info *info = data->info; 180 180 - s64 delta; 172 172 + s64 delay = ktime_us_delta(data->next_access_backoff, ktime_get()); 181 173 182 182 - if (info->access_delay) { 183 183 - delta = ktime_us_delta(ktime_get(), data->access_time); 184 184 - 185 185 - if (delta < info->access_delay) 186 186 - fsleep(info->access_delay - delta); 187 187 - } else if (info->write_delay) { 188 188 - delta = ktime_us_delta(ktime_get(), data->write_time); 189 189 - 190 190 - if (delta < info->write_delay) 191 191 - fsleep(info->write_delay - delta); 192 192 - } 174 174 + if (delay > 0) 175 175 + fsleep(delay); 193 176 } 194 177 195 195 - /* Sets the last accessed timestamp for pmbus_wait */ 196 196 - static void pmbus_update_ts(struct i2c_client *client, bool write_op) 178 178 + /* Sets the last operation timestamp for pmbus_wait */ 179 179 + static void pmbus_update_ts(struct i2c_client *client, int op) 197 180 { 198 181 struct pmbus_data *data = i2c_get_clientdata(client); 199 182 const struct pmbus_driver_info *info = data->info; 183 183 + int delay = info->access_delay; 200 184 201 201 - if (info->access_delay) 202 202 - data->access_time = ktime_get(); 203 203 - else if (info->write_delay && write_op) 204 204 - data->write_time = ktime_get(); 185 185 + if (op & PMBUS_OP_WRITE) 186 186 + delay = max(delay, info->write_delay); 187 187 + if (op & PMBUS_OP_PAGE_CHANGE) 188 188 + delay = max(delay, info->page_change_delay); 189 189 + 190 190 + if (delay > 0) 191 191 + data->next_access_backoff = ktime_add_us(ktime_get(), delay); 205 192 } 206 193 207 194 int pmbus_set_page(struct i2c_client *client, int page, int phase) ··· 210 209 data->info->pages > 1 && page != data->currpage) { 211 210 pmbus_wait(client); 212 211 rv = i2c_smbus_write_byte_data(client, PMBUS_PAGE, page); 213 213 - pmbus_update_ts(client, true); 212 212 + pmbus_update_ts(client, PMBUS_OP_WRITE | PMBUS_OP_PAGE_CHANGE); 214 213 if (rv < 0) 215 214 return rv; 216 215 217 216 pmbus_wait(client); 218 217 rv = i2c_smbus_read_byte_data(client, PMBUS_PAGE); 219 219 - pmbus_update_ts(client, false); 218 218 + pmbus_update_ts(client, 0); 220 219 if (rv < 0) 221 220 return rv; 222 221 ··· 230 229 pmbus_wait(client); 231 230 rv = i2c_smbus_write_byte_data(client, PMBUS_PHASE, 232 231 phase); 233 233 - pmbus_update_ts(client, true); 232 232 + pmbus_update_ts(client, PMBUS_OP_WRITE); 234 233 if (rv) 235 234 return rv; 236 235 } ··· 250 249 251 250 pmbus_wait(client); 252 251 rv = i2c_smbus_write_byte(client, value); 253 253 - pmbus_update_ts(client, true); 252 252 + pmbus_update_ts(client, PMBUS_OP_WRITE); 254 253 255 254 return rv; 256 255 } ··· 285 284 286 285 pmbus_wait(client); 287 286 rv = i2c_smbus_write_word_data(client, reg, word); 288 288 - pmbus_update_ts(client, true); 287 287 + pmbus_update_ts(client, PMBUS_OP_WRITE); 289 288 290 289 return rv; 291 290 } ··· 406 405 407 406 pmbus_wait(client); 408 407 rv = i2c_smbus_read_word_data(client, reg); 409 409 - pmbus_update_ts(client, false); 408 408 + pmbus_update_ts(client, 0); 410 409 411 410 return rv; 412 411 } ··· 469 468 470 469 pmbus_wait(client); 471 470 rv = i2c_smbus_read_byte_data(client, reg); 472 472 - pmbus_update_ts(client, false); 471 471 + pmbus_update_ts(client, 0); 473 472 474 473 return rv; 475 474 } ··· 485 484 486 485 pmbus_wait(client); 487 486 rv = i2c_smbus_write_byte_data(client, reg, value); 488 488 - pmbus_update_ts(client, true); 487 487 + pmbus_update_ts(client, PMBUS_OP_WRITE); 489 488 490 489 return rv; 491 490 } ··· 521 520 522 521 pmbus_wait(client); 523 522 rv = i2c_smbus_read_block_data(client, reg, data_buf); 524 524 - pmbus_update_ts(client, false); 523 523 + pmbus_update_ts(client, 0); 525 524 526 525 return rv; 527 526 } ··· 2525 2524 rv = i2c_smbus_xfer(client->adapter, client->addr, client->flags, 2526 2525 I2C_SMBUS_WRITE, PMBUS_COEFFICIENTS, 2527 2526 I2C_SMBUS_BLOCK_PROC_CALL, &data); 2528 2528 - pmbus_update_ts(client, true); 2527 2527 + pmbus_update_ts(client, PMBUS_OP_WRITE); 2529 2528 2530 2529 if (rv < 0) 2531 2530 return rv; ··· 2729 2728 if (!(data->flags & PMBUS_NO_CAPABILITY)) { 2730 2729 pmbus_wait(client); 2731 2730 ret = i2c_smbus_read_byte_data(client, PMBUS_CAPABILITY); 2732 2732 - pmbus_update_ts(client, false); 2731 2731 + pmbus_update_ts(client, 0); 2733 2732 2734 2733 if (ret >= 0 && (ret & PB_CAPABILITY_ERROR_CHECK)) { 2735 2734 if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_PEC)) ··· 2745 2744 data->read_status = pmbus_read_status_word; 2746 2745 pmbus_wait(client); 2747 2746 ret = i2c_smbus_read_word_data(client, PMBUS_STATUS_WORD); 2748 2748 - pmbus_update_ts(client, false); 2747 2747 + pmbus_update_ts(client, 0); 2749 2748 2750 2749 if (ret < 0 || ret == 0xffff) { 2751 2750 data->read_status = pmbus_read_status_byte; 2752 2751 pmbus_wait(client); 2753 2752 ret = i2c_smbus_read_byte_data(client, PMBUS_STATUS_BYTE); 2754 2754 - pmbus_update_ts(client, false); 2753 2753 + pmbus_update_ts(client, 0); 2755 2754 2756 2755 if (ret < 0 || ret == 0xff) { 2757 2756 dev_err(dev, "PMBus status register not found\n");

+1 -1

drivers/hwmon/pmbus/tda38640.c

reviewed

··· 15 15 #include "pmbus.h" 16 16 17 17 static const struct regulator_desc __maybe_unused tda38640_reg_desc[] = { 18 18 - PMBUS_REGULATOR_ONE("vout"), 18 18 + PMBUS_REGULATOR_ONE_NODE("vout"), 19 19 }; 20 20 21 21 struct tda38640_data {

+1 -1

drivers/hwmon/pmbus/tps25990.c

reviewed

··· 333 333 334 334 #if IS_ENABLED(CONFIG_SENSORS_TPS25990_REGULATOR) 335 335 static const struct regulator_desc tps25990_reg_desc[] = { 336 336 - PMBUS_REGULATOR_ONE("vout"), 336 336 + PMBUS_REGULATOR_ONE_NODE("vout"), 337 337 }; 338 338 #endif 339 339

+9 -7

drivers/hwmon/pmbus/ucd9000.c

reviewed

··· 212 212 return !!(ret & UCD9000_GPIO_CONFIG_STATUS); 213 213 } 214 214 215 215 - static void ucd9000_gpio_set(struct gpio_chip *gc, unsigned int offset, 216 216 - int value) 215 215 + static int ucd9000_gpio_set(struct gpio_chip *gc, unsigned int offset, 216 216 + int value) 217 217 { 218 218 struct i2c_client *client = gpiochip_get_data(gc); 219 219 int ret; ··· 222 222 if (ret < 0) { 223 223 dev_dbg(&client->dev, "failed to read GPIO %d config: %d\n", 224 224 offset, ret); 225 225 - return; 225 225 + return ret; 226 226 } 227 227 228 228 if (value) { 229 229 if (ret & UCD9000_GPIO_CONFIG_STATUS) 230 230 - return; 230 230 + return 0; 231 231 232 232 ret |= UCD9000_GPIO_CONFIG_STATUS; 233 233 } else { 234 234 if (!(ret & UCD9000_GPIO_CONFIG_STATUS)) 235 235 - return; 235 235 + return 0; 236 236 237 237 ret &= ~UCD9000_GPIO_CONFIG_STATUS; 238 238 } ··· 244 244 if (ret < 0) { 245 245 dev_dbg(&client->dev, "Failed to write GPIO %d config: %d\n", 246 246 offset, ret); 247 247 - return; 247 247 + return ret; 248 248 } 249 249 250 250 ret &= ~UCD9000_GPIO_CONFIG_ENABLE; ··· 253 253 if (ret < 0) 254 254 dev_dbg(&client->dev, "Failed to write GPIO %d config: %d\n", 255 255 offset, ret); 256 256 + 257 257 + return ret; 256 258 } 257 259 258 260 static int ucd9000_gpio_get_direction(struct gpio_chip *gc, ··· 364 362 data->gpio.direction_input = ucd9000_gpio_direction_input; 365 363 data->gpio.direction_output = ucd9000_gpio_direction_output; 366 364 data->gpio.get = ucd9000_gpio_get; 367 367 - data->gpio.set = ucd9000_gpio_set; 365 365 + data->gpio.set_rv = ucd9000_gpio_set; 368 366 data->gpio.can_sleep = true; 369 367 data->gpio.base = -1; 370 368 data->gpio.parent = &client->dev;

+2 -2

drivers/hwmon/pwm-fan.c

reviewed

··· 620 620 if (tach->irq == -EPROBE_DEFER) 621 621 return tach->irq; 622 622 if (tach->irq > 0) { 623 623 - ret = devm_request_irq(dev, tach->irq, pulse_handler, 0, 624 624 - pdev->name, tach); 623 623 + ret = devm_request_irq(dev, tach->irq, pulse_handler, 624 624 + IRQF_NO_THREAD, pdev->name, tach); 625 625 if (ret) { 626 626 dev_err(dev, 627 627 "Failed to request interrupt: %d\n",

-1

drivers/hwmon/qnap-mcu-hwmon.c

reviewed

··· 6 6 * Copyright (C) 2024 Heiko Stuebner <heiko@sntech.de> 7 7 */ 8 8 9 9 - #include <linux/fwnode.h> 10 9 #include <linux/hwmon.h> 11 10 #include <linux/mfd/qnap-mcu.h> 12 11 #include <linux/module.h>

+220 -139

drivers/hwmon/spd5118.c

reviewed

··· 66 66 #define SPD5118_EEPROM_BASE 0x80 67 67 #define SPD5118_EEPROM_SIZE (SPD5118_PAGE_SIZE * SPD5118_NUM_PAGES) 68 68 69 69 + #define PAGE_ADDR0(page) (((page) & BIT(0)) << 6) 70 70 + #define PAGE_ADDR1_4(page) (((page) & GENMASK(4, 1)) >> 1) 71 71 + 69 72 /* Temperature unit in millicelsius */ 70 73 #define SPD5118_TEMP_UNIT (MILLIDEGREE_PER_DEGREE / 4) 71 74 /* Representable temperature range in millicelsius */ ··· 78 75 struct spd5118_data { 79 76 struct regmap *regmap; 80 77 struct mutex nvmem_lock; 78 78 + bool is_16bit; 81 79 }; 82 80 83 81 /* hwmon */ ··· 309 305 return id && id != 0x7f; 310 306 } 311 307 312 312 - /* Return 0 if detection is successful, -ENODEV otherwise */ 313 313 - static int spd5118_detect(struct i2c_client *client, struct i2c_board_info *info) 314 314 - { 315 315 - struct i2c_adapter *adapter = client->adapter; 316 316 - int regval; 317 317 - 318 318 - if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | 319 319 - I2C_FUNC_SMBUS_WORD_DATA)) 320 320 - return -ENODEV; 321 321 - 322 322 - regval = i2c_smbus_read_word_swapped(client, SPD5118_REG_TYPE); 323 323 - if (regval != 0x5118) 324 324 - return -ENODEV; 325 325 - 326 326 - regval = i2c_smbus_read_word_data(client, SPD5118_REG_VENDOR); 327 327 - if (regval < 0 || !spd5118_vendor_valid(regval & 0xff, regval >> 8)) 328 328 - return -ENODEV; 329 329 - 330 330 - regval = i2c_smbus_read_byte_data(client, SPD5118_REG_CAPABILITY); 331 331 - if (regval < 0) 332 332 - return -ENODEV; 333 333 - if (!(regval & SPD5118_CAP_TS_SUPPORT) || (regval & 0xfc)) 334 334 - return -ENODEV; 335 335 - 336 336 - regval = i2c_smbus_read_byte_data(client, SPD5118_REG_TEMP_CLR); 337 337 - if (regval) 338 338 - return -ENODEV; 339 339 - regval = i2c_smbus_read_byte_data(client, SPD5118_REG_ERROR_CLR); 340 340 - if (regval) 341 341 - return -ENODEV; 342 342 - 343 343 - regval = i2c_smbus_read_byte_data(client, SPD5118_REG_REVISION); 344 344 - if (regval < 0 || (regval & 0xc1)) 345 345 - return -ENODEV; 346 346 - 347 347 - regval = i2c_smbus_read_byte_data(client, SPD5118_REG_TEMP_CONFIG); 348 348 - if (regval < 0) 349 349 - return -ENODEV; 350 350 - if (regval & ~SPD5118_TS_DISABLE) 351 351 - return -ENODEV; 352 352 - 353 353 - strscpy(info->type, "spd5118", I2C_NAME_SIZE); 354 354 - return 0; 355 355 - } 356 356 - 357 308 static const struct hwmon_channel_info *spd5118_info[] = { 358 309 HWMON_CHANNEL_INFO(chip, 359 310 HWMON_C_REGISTER_TZ), ··· 335 376 336 377 /* nvmem */ 337 378 338 338 - static ssize_t spd5118_nvmem_read_page(struct regmap *regmap, char *buf, 379 379 + static ssize_t spd5118_nvmem_read_page(struct spd5118_data *data, char *buf, 339 380 unsigned int offset, size_t count) 340 381 { 341 341 - int addr = (offset >> SPD5118_PAGE_SHIFT) * 0x100 + SPD5118_EEPROM_BASE; 342 342 - int err; 382 382 + int page = offset >> SPD5118_PAGE_SHIFT; 383 383 + struct regmap *regmap = data->regmap; 384 384 + int err, addr; 343 385 344 386 offset &= SPD5118_PAGE_MASK; 345 387 ··· 348 388 if (offset + count > SPD5118_PAGE_SIZE) 349 389 count = SPD5118_PAGE_SIZE - offset; 350 390 391 391 + if (data->is_16bit) { 392 392 + addr = SPD5118_EEPROM_BASE | PAGE_ADDR0(page) | 393 393 + (PAGE_ADDR1_4(page) << 8); 394 394 + } else { 395 395 + addr = page * 0x100 + SPD5118_EEPROM_BASE; 396 396 + } 351 397 err = regmap_bulk_read(regmap, addr + offset, buf, count); 352 398 if (err) 353 399 return err; ··· 376 410 mutex_lock(&data->nvmem_lock); 377 411 378 412 while (count) { 379 379 - ret = spd5118_nvmem_read_page(data->regmap, buf, off, count); 413 413 + ret = spd5118_nvmem_read_page(data, buf, off, count); 380 414 if (ret < 0) { 381 415 mutex_unlock(&data->nvmem_lock); 382 416 return ret; ··· 449 483 } 450 484 } 451 485 452 452 - static const struct regmap_range_cfg spd5118_regmap_range_cfg[] = { 486 486 + static const struct regmap_range_cfg spd5118_i2c_regmap_range_cfg[] = { 453 487 { 454 488 .selector_reg = SPD5118_REG_I2C_LEGACY_MODE, 455 489 .selector_mask = SPD5118_LEGACY_PAGE_MASK, ··· 461 495 }, 462 496 }; 463 497 464 464 - static const struct regmap_config spd5118_regmap_config = { 498 498 + static const struct regmap_config spd5118_regmap8_config = { 465 499 .reg_bits = 8, 466 500 .val_bits = 8, 467 501 .max_register = 0x7ff, ··· 469 503 .volatile_reg = spd5118_volatile_reg, 470 504 .cache_type = REGCACHE_MAPLE, 471 505 472 472 - .ranges = spd5118_regmap_range_cfg, 473 473 - .num_ranges = ARRAY_SIZE(spd5118_regmap_range_cfg), 506 506 + .ranges = spd5118_i2c_regmap_range_cfg, 507 507 + .num_ranges = ARRAY_SIZE(spd5118_i2c_regmap_range_cfg), 474 508 }; 475 509 476 476 - static int spd5118_init(struct i2c_client *client) 510 510 + static const struct regmap_config spd5118_regmap16_config = { 511 511 + .reg_bits = 16, 512 512 + .val_bits = 8, 513 513 + .max_register = 0x7ff, 514 514 + .writeable_reg = spd5118_writeable_reg, 515 515 + .volatile_reg = spd5118_volatile_reg, 516 516 + .cache_type = REGCACHE_MAPLE, 517 517 + }; 518 518 + 519 519 + static int spd5118_suspend(struct device *dev) 477 520 { 478 478 - struct i2c_adapter *adapter = client->adapter; 479 479 - int err, regval, mode; 480 480 - 481 481 - if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | 482 482 - I2C_FUNC_SMBUS_WORD_DATA)) 483 483 - return -ENODEV; 484 484 - 485 485 - regval = i2c_smbus_read_word_swapped(client, SPD5118_REG_TYPE); 486 486 - if (regval < 0 || (regval && regval != 0x5118)) 487 487 - return -ENODEV; 521 521 + struct spd5118_data *data = dev_get_drvdata(dev); 522 522 + struct regmap *regmap = data->regmap; 523 523 + u32 regval; 524 524 + int err; 488 525 489 526 /* 490 490 - * If the device type registers return 0, it is possible that the chip 491 491 - * has a non-zero page selected and takes the specification literally, 492 492 - * i.e. disables access to volatile registers besides the page register 493 493 - * if the page is not 0. Try to identify such chips. 527 527 + * Make sure the configuration register in the regmap cache is current 528 528 + * before bypassing it. 494 529 */ 495 495 - if (!regval) { 496 496 - /* Vendor ID registers must also be 0 */ 497 497 - regval = i2c_smbus_read_word_data(client, SPD5118_REG_VENDOR); 498 498 - if (regval) 499 499 - return -ENODEV; 530 530 + err = regmap_read(regmap, SPD5118_REG_TEMP_CONFIG, &regval); 531 531 + if (err < 0) 532 532 + return err; 500 533 501 501 - /* The selected page in MR11 must not be 0 */ 502 502 - mode = i2c_smbus_read_byte_data(client, SPD5118_REG_I2C_LEGACY_MODE); 503 503 - if (mode < 0 || (mode & ~SPD5118_LEGACY_MODE_MASK) || 504 504 - !(mode & SPD5118_LEGACY_PAGE_MASK)) 505 505 - return -ENODEV; 534 534 + regcache_cache_bypass(regmap, true); 535 535 + regmap_update_bits(regmap, SPD5118_REG_TEMP_CONFIG, SPD5118_TS_DISABLE, 536 536 + SPD5118_TS_DISABLE); 537 537 + regcache_cache_bypass(regmap, false); 506 538 507 507 - err = i2c_smbus_write_byte_data(client, SPD5118_REG_I2C_LEGACY_MODE, 508 508 - mode & SPD5118_LEGACY_MODE_ADDR); 509 509 - if (err) 510 510 - return -ENODEV; 539 539 + regcache_cache_only(regmap, true); 540 540 + regcache_mark_dirty(regmap); 511 541 512 512 - /* 513 513 - * If the device type registers are still bad after selecting 514 514 - * page 0, this is not a SPD5118 device. Restore original 515 515 - * legacy mode register value and abort. 516 516 - */ 517 517 - regval = i2c_smbus_read_word_swapped(client, SPD5118_REG_TYPE); 518 518 - if (regval != 0x5118) { 519 519 - i2c_smbus_write_byte_data(client, SPD5118_REG_I2C_LEGACY_MODE, mode); 520 520 - return -ENODEV; 521 521 - } 522 522 - } 523 523 - 524 524 - /* We are reasonably sure that this is really a SPD5118 hub controller */ 525 542 return 0; 526 543 } 527 544 528 528 - static int spd5118_probe(struct i2c_client *client) 545 545 + static int spd5118_resume(struct device *dev) 529 546 { 530 530 - struct device *dev = &client->dev; 531 531 - unsigned int regval, revision, vendor, bank; 547 547 + struct spd5118_data *data = dev_get_drvdata(dev); 548 548 + struct regmap *regmap = data->regmap; 549 549 + 550 550 + regcache_cache_only(regmap, false); 551 551 + return regcache_sync(regmap); 552 552 + } 553 553 + 554 554 + static DEFINE_SIMPLE_DEV_PM_OPS(spd5118_pm_ops, spd5118_suspend, spd5118_resume); 555 555 + 556 556 + static int spd5118_common_probe(struct device *dev, struct regmap *regmap, 557 557 + bool is_16bit) 558 558 + { 559 559 + unsigned int capability, revision, vendor, bank; 532 560 struct spd5118_data *data; 533 561 struct device *hwmon_dev; 534 534 - struct regmap *regmap; 535 562 int err; 536 536 - 537 537 - err = spd5118_init(client); 538 538 - if (err) 539 539 - return err; 540 563 541 564 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 542 565 if (!data) 543 566 return -ENOMEM; 544 567 545 545 - regmap = devm_regmap_init_i2c(client, &spd5118_regmap_config); 546 546 - if (IS_ERR(regmap)) 547 547 - return dev_err_probe(dev, PTR_ERR(regmap), "regmap init failed\n"); 548 548 - 549 549 - err = regmap_read(regmap, SPD5118_REG_CAPABILITY, &regval); 568 568 + err = regmap_read(regmap, SPD5118_REG_CAPABILITY, &capability); 550 569 if (err) 551 570 return err; 552 552 - if (!(regval & SPD5118_CAP_TS_SUPPORT)) 571 571 + if (!(capability & SPD5118_CAP_TS_SUPPORT)) 553 572 return -ENODEV; 573 573 + 574 574 + data->is_16bit = is_16bit; 554 575 555 576 err = regmap_read(regmap, SPD5118_REG_REVISION, &revision); 556 577 if (err) ··· 580 627 return 0; 581 628 } 582 629 583 583 - static int spd5118_suspend(struct device *dev) 630 630 + /* I2C */ 631 631 + 632 632 + /* Return 0 if detection is successful, -ENODEV otherwise */ 633 633 + static int spd5118_detect(struct i2c_client *client, struct i2c_board_info *info) 584 634 { 585 585 - struct spd5118_data *data = dev_get_drvdata(dev); 586 586 - struct regmap *regmap = data->regmap; 587 587 - u32 regval; 588 588 - int err; 635 635 + struct i2c_adapter *adapter = client->adapter; 636 636 + int regval; 589 637 590 590 - /* 591 591 - * Make sure the configuration register in the regmap cache is current 592 592 - * before bypassing it. 593 593 - */ 594 594 - err = regmap_read(regmap, SPD5118_REG_TEMP_CONFIG, &regval); 595 595 - if (err < 0) 596 596 - return err; 638 638 + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | 639 639 + I2C_FUNC_SMBUS_WORD_DATA)) 640 640 + return -ENODEV; 597 641 598 598 - regcache_cache_bypass(regmap, true); 599 599 - regmap_update_bits(regmap, SPD5118_REG_TEMP_CONFIG, SPD5118_TS_DISABLE, 600 600 - SPD5118_TS_DISABLE); 601 601 - regcache_cache_bypass(regmap, false); 642 642 + regval = i2c_smbus_read_word_swapped(client, SPD5118_REG_TYPE); 643 643 + if (regval != 0x5118) 644 644 + return -ENODEV; 602 645 603 603 - regcache_cache_only(regmap, true); 604 604 - regcache_mark_dirty(regmap); 646 646 + regval = i2c_smbus_read_word_data(client, SPD5118_REG_VENDOR); 647 647 + if (regval < 0 || !spd5118_vendor_valid(regval & 0xff, regval >> 8)) 648 648 + return -ENODEV; 605 649 650 650 + regval = i2c_smbus_read_byte_data(client, SPD5118_REG_CAPABILITY); 651 651 + if (regval < 0) 652 652 + return -ENODEV; 653 653 + if (!(regval & SPD5118_CAP_TS_SUPPORT) || (regval & 0xfc)) 654 654 + return -ENODEV; 655 655 + 656 656 + regval = i2c_smbus_read_byte_data(client, SPD5118_REG_TEMP_CLR); 657 657 + if (regval) 658 658 + return -ENODEV; 659 659 + regval = i2c_smbus_read_byte_data(client, SPD5118_REG_ERROR_CLR); 660 660 + if (regval) 661 661 + return -ENODEV; 662 662 + 663 663 + regval = i2c_smbus_read_byte_data(client, SPD5118_REG_REVISION); 664 664 + if (regval < 0 || (regval & 0xc1)) 665 665 + return -ENODEV; 666 666 + 667 667 + regval = i2c_smbus_read_byte_data(client, SPD5118_REG_TEMP_CONFIG); 668 668 + if (regval < 0) 669 669 + return -ENODEV; 670 670 + if (regval & ~SPD5118_TS_DISABLE) 671 671 + return -ENODEV; 672 672 + 673 673 + strscpy(info->type, "spd5118", I2C_NAME_SIZE); 606 674 return 0; 607 675 } 608 676 609 609 - static int spd5118_resume(struct device *dev) 677 677 + static int spd5118_i2c_init(struct i2c_client *client) 610 678 { 611 611 - struct spd5118_data *data = dev_get_drvdata(dev); 612 612 - struct regmap *regmap = data->regmap; 679 679 + struct i2c_adapter *adapter = client->adapter; 680 680 + int err, regval, mode; 613 681 614 614 - regcache_cache_only(regmap, false); 615 615 - return regcache_sync(regmap); 682 682 + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | 683 683 + I2C_FUNC_SMBUS_WORD_DATA)) 684 684 + return -ENODEV; 685 685 + 686 686 + regval = i2c_smbus_read_word_swapped(client, SPD5118_REG_TYPE); 687 687 + if (regval < 0 || (regval && regval != 0x5118)) 688 688 + return -ENODEV; 689 689 + 690 690 + /* 691 691 + * If the device type registers return 0, it is possible that the chip 692 692 + * has a non-zero page selected and takes the specification literally, 693 693 + * i.e. disables access to volatile registers besides the page register 694 694 + * if the page is not 0. The Renesas/ITD SPD5118 Hub Controller is known 695 695 + * to show this behavior. Try to identify such chips. 696 696 + */ 697 697 + if (!regval) { 698 698 + /* Vendor ID registers must also be 0 */ 699 699 + regval = i2c_smbus_read_word_data(client, SPD5118_REG_VENDOR); 700 700 + if (regval) 701 701 + return -ENODEV; 702 702 + 703 703 + /* The selected page in MR11 must not be 0 */ 704 704 + mode = i2c_smbus_read_byte_data(client, SPD5118_REG_I2C_LEGACY_MODE); 705 705 + if (mode < 0 || (mode & ~SPD5118_LEGACY_MODE_MASK) || 706 706 + !(mode & SPD5118_LEGACY_PAGE_MASK)) 707 707 + return -ENODEV; 708 708 + 709 709 + err = i2c_smbus_write_byte_data(client, SPD5118_REG_I2C_LEGACY_MODE, 710 710 + mode & SPD5118_LEGACY_MODE_ADDR); 711 711 + if (err) 712 712 + return -ENODEV; 713 713 + 714 714 + /* 715 715 + * If the device type registers are still bad after selecting 716 716 + * page 0, this is not a SPD5118 device. Restore original 717 717 + * legacy mode register value and abort. 718 718 + */ 719 719 + regval = i2c_smbus_read_word_swapped(client, SPD5118_REG_TYPE); 720 720 + if (regval != 0x5118) { 721 721 + i2c_smbus_write_byte_data(client, SPD5118_REG_I2C_LEGACY_MODE, mode); 722 722 + return -ENODEV; 723 723 + } 724 724 + } 725 725 + 726 726 + /* We are reasonably sure that this is really a SPD5118 hub controller */ 727 727 + return 0; 616 728 } 617 729 618 618 - static DEFINE_SIMPLE_DEV_PM_OPS(spd5118_pm_ops, spd5118_suspend, spd5118_resume); 730 730 + /* 731 731 + * 16-bit addressing note: 732 732 + * 733 733 + * If I2C_FUNC_I2C is not supported by an I2C adapter driver, regmap uses 734 734 + * SMBus operations as alternative. To simulate a read operation with a 16-bit 735 735 + * address, it writes the address using i2c_smbus_write_byte_data(), followed 736 736 + * by one or more calls to i2c_smbus_read_byte() to read the data. 737 737 + * Per spd5118 standard, a read operation after writing the address must start 738 738 + * with <Sr> (Repeat Start). However, a SMBus read byte operation starts with 739 739 + * <S> (Start). This resets the register address in the spd5118 chip. As result, 740 740 + * i2c_smbus_read_byte() always returns data from register address 0x00. 741 741 + * 742 742 + * A working alternative to access chips with 16-bit register addresses in the 743 743 + * absence of I2C_FUNC_I2C support is not known. 744 744 + * 745 745 + * For this reason, 16-bit addressing can only be supported with I2C if the 746 746 + * adapter supports I2C_FUNC_I2C. 747 747 + * 748 748 + * For I2C, the addressing mode selected by the BIOS must not be changed. 749 749 + * Experiments show that at least some PC BIOS versions will not change the 750 750 + * addressing mode on a soft reboot and end up in setup, claiming that some 751 751 + * configuration change happened. This will happen again after a power cycle, 752 752 + * which does reset the addressing mode. To prevent this from happening, 753 753 + * detect if 16-bit addressing is enabled and always use the currently 754 754 + * configured addressing mode. 755 755 + */ 619 756 620 620 - static const struct i2c_device_id spd5118_id[] = { 757 757 + static int spd5118_i2c_probe(struct i2c_client *client) 758 758 + { 759 759 + const struct regmap_config *config; 760 760 + struct device *dev = &client->dev; 761 761 + struct regmap *regmap; 762 762 + int err, mode; 763 763 + bool is_16bit; 764 764 + 765 765 + err = spd5118_i2c_init(client); 766 766 + if (err) 767 767 + return err; 768 768 + 769 769 + mode = i2c_smbus_read_byte_data(client, SPD5118_REG_I2C_LEGACY_MODE); 770 770 + if (mode < 0) 771 771 + return mode; 772 772 + 773 773 + is_16bit = mode & SPD5118_LEGACY_MODE_ADDR; 774 774 + if (is_16bit) { 775 775 + /* 776 776 + * See 16-bit addressing note above explaining why it is 777 777 + * necessary to check for I2C_FUNC_I2C support here. 778 778 + */ 779 779 + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 780 780 + dev_err(dev, "Adapter does not support 16-bit register addresses\n"); 781 781 + return -ENODEV; 782 782 + } 783 783 + config = &spd5118_regmap16_config; 784 784 + } else { 785 785 + config = &spd5118_regmap8_config; 786 786 + } 787 787 + 788 788 + regmap = devm_regmap_init_i2c(client, config); 789 789 + if (IS_ERR(regmap)) 790 790 + return dev_err_probe(dev, PTR_ERR(regmap), "regmap init failed\n"); 791 791 + 792 792 + return spd5118_common_probe(dev, regmap, is_16bit); 793 793 + } 794 794 + 795 795 + static const struct i2c_device_id spd5118_i2c_id[] = { 621 796 { "spd5118" }, 622 797 { } 623 798 }; 624 624 - MODULE_DEVICE_TABLE(i2c, spd5118_id); 799 799 + MODULE_DEVICE_TABLE(i2c, spd5118_i2c_id); 625 800 626 801 static const struct of_device_id spd5118_of_ids[] = { 627 802 { .compatible = "jedec,spd5118", }, ··· 757 676 }; 758 677 MODULE_DEVICE_TABLE(of, spd5118_of_ids); 759 678 760 760 - static struct i2c_driver spd5118_driver = { 679 679 + static struct i2c_driver spd5118_i2c_driver = { 761 680 .class = I2C_CLASS_HWMON, 762 681 .driver = { 763 682 .name = "spd5118", 764 683 .of_match_table = spd5118_of_ids, 765 684 .pm = pm_sleep_ptr(&spd5118_pm_ops), 766 685 }, 767 767 - .probe = spd5118_probe, 768 768 - .id_table = spd5118_id, 686 686 + .probe = spd5118_i2c_probe, 687 687 + .id_table = spd5118_i2c_id, 769 688 .detect = IS_ENABLED(CONFIG_SENSORS_SPD5118_DETECT) ? spd5118_detect : NULL, 770 689 .address_list = IS_ENABLED(CONFIG_SENSORS_SPD5118_DETECT) ? normal_i2c : NULL, 771 690 }; 772 691 773 773 - module_i2c_driver(spd5118_driver); 692 692 + module_i2c_driver(spd5118_i2c_driver); 774 693 775 694 MODULE_AUTHOR("René Rebe <rene@exactcode.de>"); 776 695 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");

+5

drivers/hwmon/tmp102.c

reviewed

··· 16 16 #include <linux/device.h> 17 17 #include <linux/jiffies.h> 18 18 #include <linux/regmap.h> 19 19 + #include <linux/regulator/consumer.h> 19 20 #include <linux/of.h> 20 21 21 22 #define DRIVER_NAME "tmp102" ··· 204 203 "adapter doesn't support SMBus word transactions\n"); 205 204 return -ENODEV; 206 205 } 206 206 + 207 207 + err = devm_regulator_get_enable_optional(dev, "vcc"); 208 208 + if (err < 0 && err != -ENODEV) 209 209 + return dev_err_probe(dev, err, "Failed to enable regulator\n"); 207 210 208 211 tmp102 = devm_kzalloc(dev, sizeof(*tmp102), GFP_KERNEL); 209 212 if (!tmp102)

+4 -35

drivers/hwmon/xgene-hwmon.c

reviewed

··· 103 103 struct device *hwmon_dev; 104 104 bool temp_critical_alarm; 105 105 106 106 - phys_addr_t comm_base_addr; 107 107 - void *pcc_comm_addr; 108 106 unsigned int usecs_lat; 109 107 }; 110 108 ··· 123 125 124 126 static int xgene_hwmon_pcc_rd(struct xgene_hwmon_dev *ctx, u32 *msg) 125 127 { 126 126 - struct acpi_pcct_shared_memory *generic_comm_base = ctx->pcc_comm_addr; 128 128 + struct acpi_pcct_shared_memory __iomem *generic_comm_base = 129 129 + ctx->pcc_chan->shmem; 127 130 u32 *ptr = (void *)(generic_comm_base + 1); 128 131 int rc, i; 129 132 u16 val; ··· 522 523 static void xgene_hwmon_pcc_rx_cb(struct mbox_client *cl, void *msg) 523 524 { 524 525 struct xgene_hwmon_dev *ctx = to_xgene_hwmon_dev(cl); 525 525 - struct acpi_pcct_shared_memory *generic_comm_base = ctx->pcc_comm_addr; 526 526 + struct acpi_pcct_shared_memory __iomem *generic_comm_base = 527 527 + ctx->pcc_chan->shmem; 526 528 struct slimpro_resp_msg amsg; 527 529 528 530 /* ··· 649 649 } else { 650 650 struct pcc_mbox_chan *pcc_chan; 651 651 const struct acpi_device_id *acpi_id; 652 652 - int version; 653 652 654 653 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table, 655 654 &pdev->dev); ··· 656 657 rc = -EINVAL; 657 658 goto out_mbox_free; 658 659 } 659 659 - 660 660 - version = (int)acpi_id->driver_data; 661 660 662 661 if (device_property_read_u32(&pdev->dev, "pcc-channel", 663 662 &ctx->mbox_idx)) { ··· 679 682 if (!ctx->mbox_chan->mbox->txdone_irq) { 680 683 dev_err(&pdev->dev, "PCC IRQ not supported\n"); 681 684 rc = -ENODEV; 682 682 - goto out; 683 683 - } 684 684 - 685 685 - /* 686 686 - * This is the shared communication region 687 687 - * for the OS and Platform to communicate over. 688 688 - */ 689 689 - ctx->comm_base_addr = pcc_chan->shmem_base_addr; 690 690 - if (ctx->comm_base_addr) { 691 691 - if (version == XGENE_HWMON_V2) 692 692 - ctx->pcc_comm_addr = (void __force *)devm_ioremap(&pdev->dev, 693 693 - ctx->comm_base_addr, 694 694 - pcc_chan->shmem_size); 695 695 - else 696 696 - ctx->pcc_comm_addr = devm_memremap(&pdev->dev, 697 697 - ctx->comm_base_addr, 698 698 - pcc_chan->shmem_size, 699 699 - MEMREMAP_WB); 700 700 - } else { 701 701 - dev_err(&pdev->dev, "Failed to get PCC comm region\n"); 702 702 - rc = -ENODEV; 703 703 - goto out; 704 704 - } 705 705 - 706 706 - if (IS_ERR_OR_NULL(ctx->pcc_comm_addr)) { 707 707 - dev_err(&pdev->dev, 708 708 - "Failed to ioremap PCC comm region\n"); 709 709 - rc = -ENOMEM; 710 685 goto out; 711 686 } 712 687