tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'mtd/fixes-for-5.10-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux

Pull mtd fixes from Miquel Raynal:
"Because of a recent change in the core, NAND controller drivers
initializing the ECC engine too early in the probe path are broken.

Drivers should wait for the NAND device to be discovered and its
memory layout known before doing any ECC related initialization, so
instead of reverting the faulty change which is actually moving in the
right direction, let's fix the drivers directly: socrates, sharpsl,
r852, plat_nand, pasemi, tmio, txx9ndfmc, orion, mpc5121, lpc32xx_slc,
lpc32xx_mlc, fsmc, diskonchip, davinci, cs553x, au1550, ams-delta,
xway and gpio"

* tag 'mtd/fixes-for-5.10-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux:
mtd: rawnand: socrates: Move the ECC initialization to ->attach_chip()
mtd: rawnand: sharpsl: Move the ECC initialization to ->attach_chip()
mtd: rawnand: r852: Move the ECC initialization to ->attach_chip()
mtd: rawnand: plat_nand: Move the ECC initialization to ->attach_chip()
mtd: rawnand: pasemi: Move the ECC initialization to ->attach_chip()
mtd: rawnand: tmio: Move the ECC initialization to ->attach_chip()
mtd: rawnand: txx9ndfmc: Move the ECC initialization to ->attach_chip()
mtd: rawnand: orion: Move the ECC initialization to ->attach_chip()
mtd: rawnand: mpc5121: Move the ECC initialization to ->attach_chip()
mtd: rawnand: lpc32xx_slc: Move the ECC initialization to ->attach_chip()
mtd: rawnand: lpc32xx_mlc: Move the ECC initialization to ->attach_chip()
mtd: rawnand: fsmc: Move the ECC initialization to ->attach_chip()
mtd: rawnand: diskonchip: Move the ECC initialization to ->attach_chip()
mtd: rawnand: davinci: Move the ECC initialization to ->attach_chip()
mtd: rawnand: cs553x: Move the ECC initialization to ->attach_chip()
mtd: rawnand: au1550: Move the ECC initialization to ->attach_chip()
mtd: rawnand: ams-delta: Move the ECC initialization to ->attach_chip()
mtd: rawnand: xway: Move the ECC initialization to ->attach_chip()
mtd: rawnand: gpio: Move the ECC initialization to ->attach_chip()

Linus Torvalds 76dc2bfc 87c301ca

+294 -116
+9 -3
drivers/mtd/nand/raw/ams-delta.c
··· 215 215 return 0; 216 216 } 217 217 218 + static int gpio_nand_attach_chip(struct nand_chip *chip) 219 + { 220 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 221 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 222 + 223 + return 0; 224 + } 225 + 218 226 static const struct nand_controller_ops gpio_nand_ops = { 219 227 .exec_op = gpio_nand_exec_op, 228 + .attach_chip = gpio_nand_attach_chip, 220 229 .setup_interface = gpio_nand_setup_interface, 221 230 }; 222 231 ··· 268 259 dev_warn(&pdev->dev, "RDY GPIO request failed (%d)\n", err); 269 260 return err; 270 261 } 271 - 272 - this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 273 - this->ecc.algo = NAND_ECC_ALGO_HAMMING; 274 262 275 263 platform_set_drvdata(pdev, priv); 276 264
+9 -2
drivers/mtd/nand/raw/au1550nd.c
··· 236 236 return ret; 237 237 } 238 238 239 + static int au1550nd_attach_chip(struct nand_chip *chip) 240 + { 241 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 242 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 243 + 244 + return 0; 245 + } 246 + 239 247 static const struct nand_controller_ops au1550nd_ops = { 240 248 .exec_op = au1550nd_exec_op, 249 + .attach_chip = au1550nd_attach_chip, 241 250 }; 242 251 243 252 static int au1550nd_probe(struct platform_device *pdev) ··· 303 294 nand_controller_init(&ctx->controller); 304 295 ctx->controller.ops = &au1550nd_ops; 305 296 this->controller = &ctx->controller; 306 - this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 307 - this->ecc.algo = NAND_ECC_ALGO_HAMMING; 308 297 309 298 if (pd->devwidth) 310 299 this->options |= NAND_BUSWIDTH_16;
+16 -8
drivers/mtd/nand/raw/cs553x_nand.c
··· 243 243 244 244 static struct cs553x_nand_controller *controllers[4]; 245 245 246 + static int cs553x_attach_chip(struct nand_chip *chip) 247 + { 248 + if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 249 + return 0; 250 + 251 + chip->ecc.size = 256; 252 + chip->ecc.bytes = 3; 253 + chip->ecc.hwctl = cs_enable_hwecc; 254 + chip->ecc.calculate = cs_calculate_ecc; 255 + chip->ecc.correct = nand_correct_data; 256 + chip->ecc.strength = 1; 257 + 258 + return 0; 259 + } 260 + 246 261 static const struct nand_controller_ops cs553x_nand_controller_ops = { 247 262 .exec_op = cs553x_exec_op, 263 + .attach_chip = cs553x_attach_chip, 248 264 }; 249 265 250 266 static int __init cs553x_init_one(int cs, int mmio, unsigned long adr) ··· 301 285 err = -EIO; 302 286 goto out_mtd; 303 287 } 304 - 305 - this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 306 - this->ecc.size = 256; 307 - this->ecc.bytes = 3; 308 - this->ecc.hwctl = cs_enable_hwecc; 309 - this->ecc.calculate = cs_calculate_ecc; 310 - this->ecc.correct = nand_correct_data; 311 - this->ecc.strength = 1; 312 288 313 289 /* Enable the following for a flash based bad block table */ 314 290 this->bbt_options = NAND_BBT_USE_FLASH;
+4 -4
drivers/mtd/nand/raw/davinci_nand.c
··· 585 585 if (IS_ERR(pdata)) 586 586 return PTR_ERR(pdata); 587 587 588 + /* Use board-specific ECC config */ 589 + info->chip.ecc.engine_type = pdata->engine_type; 590 + info->chip.ecc.placement = pdata->ecc_placement; 591 + 588 592 switch (info->chip.ecc.engine_type) { 589 593 case NAND_ECC_ENGINE_TYPE_NONE: 590 594 pdata->ecc_bits = 0; ··· 853 849 /* use nandboot-capable ALE/CLE masks by default */ 854 850 info->mask_ale = pdata->mask_ale ? : MASK_ALE; 855 851 info->mask_cle = pdata->mask_cle ? : MASK_CLE; 856 - 857 - /* Use board-specific ECC config */ 858 - info->chip.ecc.engine_type = pdata->engine_type; 859 - info->chip.ecc.placement = pdata->ecc_placement; 860 852 861 853 spin_lock_irq(&davinci_nand_lock); 862 854
+19 -10
drivers/mtd/nand/raw/diskonchip.c
··· 1269 1269 return 1; 1270 1270 } 1271 1271 1272 + static int doc200x_attach_chip(struct nand_chip *chip) 1273 + { 1274 + if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 1275 + return 0; 1276 + 1277 + chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED; 1278 + chip->ecc.size = 512; 1279 + chip->ecc.bytes = 6; 1280 + chip->ecc.strength = 2; 1281 + chip->ecc.options = NAND_ECC_GENERIC_ERASED_CHECK; 1282 + chip->ecc.hwctl = doc200x_enable_hwecc; 1283 + chip->ecc.calculate = doc200x_calculate_ecc; 1284 + chip->ecc.correct = doc200x_correct_data; 1285 + 1286 + return 0; 1287 + } 1288 + 1272 1289 static const struct nand_controller_ops doc200x_ops = { 1273 1290 .exec_op = doc200x_exec_op, 1291 + .attach_chip = doc200x_attach_chip, 1274 1292 }; 1275 1293 1276 1294 static const struct nand_controller_ops doc2001plus_ops = { 1277 1295 .exec_op = doc2001plus_exec_op, 1296 + .attach_chip = doc200x_attach_chip, 1278 1297 }; 1279 1298 1280 1299 static int __init doc_probe(unsigned long physadr) ··· 1471 1452 1472 1453 nand->controller = &doc->base; 1473 1454 nand_set_controller_data(nand, doc); 1474 - nand->ecc.hwctl = doc200x_enable_hwecc; 1475 - nand->ecc.calculate = doc200x_calculate_ecc; 1476 - nand->ecc.correct = doc200x_correct_data; 1477 - 1478 - nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 1479 - nand->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED; 1480 - nand->ecc.size = 512; 1481 - nand->ecc.bytes = 6; 1482 - nand->ecc.strength = 2; 1483 - nand->ecc.options = NAND_ECC_GENERIC_ERASED_CHECK; 1484 1455 nand->bbt_options = NAND_BBT_USE_FLASH; 1485 1456 /* Skip the automatic BBT scan so we can run it manually */ 1486 1457 nand->options |= NAND_SKIP_BBTSCAN | NAND_NO_BBM_QUIRK;
+15 -15
drivers/mtd/nand/raw/fsmc_nand.c
··· 880 880 struct mtd_info *mtd = nand_to_mtd(nand); 881 881 struct fsmc_nand_data *host = nand_to_fsmc(nand); 882 882 883 + if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID) 884 + nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 885 + 886 + if (!nand->ecc.size) 887 + nand->ecc.size = 512; 888 + 889 + if (AMBA_REV_BITS(host->pid) >= 8) { 890 + nand->ecc.read_page = fsmc_read_page_hwecc; 891 + nand->ecc.calculate = fsmc_read_hwecc_ecc4; 892 + nand->ecc.correct = fsmc_bch8_correct_data; 893 + nand->ecc.bytes = 13; 894 + nand->ecc.strength = 8; 895 + } 896 + 883 897 if (AMBA_REV_BITS(host->pid) >= 8) { 884 898 switch (mtd->oobsize) { 885 899 case 16: ··· 919 905 dev_info(host->dev, "Using 1-bit HW ECC scheme\n"); 920 906 nand->ecc.calculate = fsmc_read_hwecc_ecc1; 921 907 nand->ecc.correct = nand_correct_data; 908 + nand->ecc.hwctl = fsmc_enable_hwecc; 922 909 nand->ecc.bytes = 3; 923 910 nand->ecc.strength = 1; 924 911 nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER; ··· 1070 1055 1071 1056 mtd->dev.parent = &pdev->dev; 1072 1057 1073 - /* 1074 - * Setup default ECC mode. nand_dt_init() called from nand_scan_ident() 1075 - * can overwrite this value if the DT provides a different value. 1076 - */ 1077 - nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 1078 - nand->ecc.hwctl = fsmc_enable_hwecc; 1079 - nand->ecc.size = 512; 1080 1058 nand->badblockbits = 7; 1081 1059 1082 1060 if (host->mode == USE_DMA_ACCESS) { ··· 1090 1082 if (host->dev_timings) { 1091 1083 fsmc_nand_setup(host, host->dev_timings); 1092 1084 nand->options |= NAND_KEEP_TIMINGS; 1093 - } 1094 - 1095 - if (AMBA_REV_BITS(host->pid) >= 8) { 1096 - nand->ecc.read_page = fsmc_read_page_hwecc; 1097 - nand->ecc.calculate = fsmc_read_hwecc_ecc4; 1098 - nand->ecc.correct = fsmc_bch8_correct_data; 1099 - nand->ecc.bytes = 13; 1100 - nand->ecc.strength = 8; 1101 1085 } 1102 1086 1103 1087 nand_controller_init(&host->base);
+9 -2
drivers/mtd/nand/raw/gpio.c
··· 161 161 return ret; 162 162 } 163 163 164 + static int gpio_nand_attach_chip(struct nand_chip *chip) 165 + { 166 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 167 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 168 + 169 + return 0; 170 + } 171 + 164 172 static const struct nand_controller_ops gpio_nand_ops = { 165 173 .exec_op = gpio_nand_exec_op, 174 + .attach_chip = gpio_nand_attach_chip, 166 175 }; 167 176 168 177 #ifdef CONFIG_OF ··· 351 342 gpiomtd->base.ops = &gpio_nand_ops; 352 343 353 344 nand_set_flash_node(chip, pdev->dev.of_node); 354 - chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 355 - chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 356 345 chip->options = gpiomtd->plat.options; 357 346 chip->controller = &gpiomtd->base; 358 347
+13 -10
drivers/mtd/nand/raw/lpc32xx_mlc.c
··· 648 648 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 649 649 struct device *dev = &host->pdev->dev; 650 650 651 + if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 652 + return 0; 653 + 651 654 host->dma_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL); 652 655 if (!host->dma_buf) 653 656 return -ENOMEM; ··· 659 656 if (!host->dummy_buf) 660 657 return -ENOMEM; 661 658 662 - chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 663 659 chip->ecc.size = 512; 660 + chip->ecc.hwctl = lpc32xx_ecc_enable; 661 + chip->ecc.read_page_raw = lpc32xx_read_page; 662 + chip->ecc.read_page = lpc32xx_read_page; 663 + chip->ecc.write_page_raw = lpc32xx_write_page_lowlevel; 664 + chip->ecc.write_page = lpc32xx_write_page_lowlevel; 665 + chip->ecc.write_oob = lpc32xx_write_oob; 666 + chip->ecc.read_oob = lpc32xx_read_oob; 667 + chip->ecc.strength = 4; 668 + chip->ecc.bytes = 10; 669 + 664 670 mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops); 665 671 host->mlcsubpages = mtd->writesize / 512; 666 672 ··· 753 741 platform_set_drvdata(pdev, host); 754 742 755 743 /* Initialize function pointers */ 756 - nand_chip->ecc.hwctl = lpc32xx_ecc_enable; 757 - nand_chip->ecc.read_page_raw = lpc32xx_read_page; 758 - nand_chip->ecc.read_page = lpc32xx_read_page; 759 - nand_chip->ecc.write_page_raw = lpc32xx_write_page_lowlevel; 760 - nand_chip->ecc.write_page = lpc32xx_write_page_lowlevel; 761 - nand_chip->ecc.write_oob = lpc32xx_write_oob; 762 - nand_chip->ecc.read_oob = lpc32xx_read_oob; 763 - nand_chip->ecc.strength = 4; 764 - nand_chip->ecc.bytes = 10; 765 744 nand_chip->legacy.waitfunc = lpc32xx_waitfunc; 766 745 767 746 nand_chip->options = NAND_NO_SUBPAGE_WRITE;
+14 -12
drivers/mtd/nand/raw/lpc32xx_slc.c
··· 775 775 struct mtd_info *mtd = nand_to_mtd(chip); 776 776 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 777 777 778 + if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 779 + return 0; 780 + 778 781 /* OOB and ECC CPU and DMA work areas */ 779 782 host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE); 780 783 ··· 789 786 if (mtd->writesize <= 512) 790 787 mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops); 791 788 789 + chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED; 792 790 /* These sizes remain the same regardless of page size */ 793 791 chip->ecc.size = 256; 792 + chip->ecc.strength = 1; 794 793 chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES; 795 794 chip->ecc.prepad = 0; 796 795 chip->ecc.postpad = 0; 796 + chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome; 797 + chip->ecc.read_page = lpc32xx_nand_read_page_syndrome; 798 + chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome; 799 + chip->ecc.write_page = lpc32xx_nand_write_page_syndrome; 800 + chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome; 801 + chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome; 802 + chip->ecc.calculate = lpc32xx_nand_ecc_calculate; 803 + chip->ecc.correct = nand_correct_data; 804 + chip->ecc.hwctl = lpc32xx_nand_ecc_enable; 797 805 798 806 /* 799 807 * Use a custom BBT marker setup for small page FLASH that ··· 895 881 platform_set_drvdata(pdev, host); 896 882 897 883 /* NAND callbacks for LPC32xx SLC hardware */ 898 - chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 899 - chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED; 900 884 chip->legacy.read_byte = lpc32xx_nand_read_byte; 901 885 chip->legacy.read_buf = lpc32xx_nand_read_buf; 902 886 chip->legacy.write_buf = lpc32xx_nand_write_buf; 903 - chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome; 904 - chip->ecc.read_page = lpc32xx_nand_read_page_syndrome; 905 - chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome; 906 - chip->ecc.write_page = lpc32xx_nand_write_page_syndrome; 907 - chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome; 908 - chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome; 909 - chip->ecc.calculate = lpc32xx_nand_ecc_calculate; 910 - chip->ecc.correct = nand_correct_data; 911 - chip->ecc.strength = 1; 912 - chip->ecc.hwctl = lpc32xx_nand_ecc_enable; 913 887 914 888 /* 915 889 * Allocate a large enough buffer for a single huge page plus
+17 -2
drivers/mtd/nand/raw/mpc5121_nfc.c
··· 104 104 #define NFC_TIMEOUT (HZ / 10) /* 1/10 s */ 105 105 106 106 struct mpc5121_nfc_prv { 107 + struct nand_controller controller; 107 108 struct nand_chip chip; 108 109 int irq; 109 110 void __iomem *regs; ··· 603 602 iounmap(prv->csreg); 604 603 } 605 604 605 + static int mpc5121_nfc_attach_chip(struct nand_chip *chip) 606 + { 607 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 608 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 609 + 610 + return 0; 611 + } 612 + 613 + static const struct nand_controller_ops mpc5121_nfc_ops = { 614 + .attach_chip = mpc5121_nfc_attach_chip, 615 + }; 616 + 606 617 static int mpc5121_nfc_probe(struct platform_device *op) 607 618 { 608 619 struct device_node *dn = op->dev.of_node; ··· 646 633 647 634 chip = &prv->chip; 648 635 mtd = nand_to_mtd(chip); 636 + 637 + nand_controller_init(&prv->controller); 638 + prv->controller.ops = &mpc5121_nfc_ops; 639 + chip->controller = &prv->controller; 649 640 650 641 mtd->dev.parent = dev; 651 642 nand_set_controller_data(chip, prv); ··· 705 688 chip->legacy.set_features = nand_get_set_features_notsupp; 706 689 chip->legacy.get_features = nand_get_set_features_notsupp; 707 690 chip->bbt_options = NAND_BBT_USE_FLASH; 708 - chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 709 - chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 710 691 711 692 /* Support external chip-select logic on ADS5121 board */ 712 693 if (of_machine_is_compatible("fsl,mpc5121ads")) {
+17 -2
drivers/mtd/nand/raw/orion_nand.c
··· 22 22 #include <linux/platform_data/mtd-orion_nand.h> 23 23 24 24 struct orion_nand_info { 25 + struct nand_controller controller; 25 26 struct nand_chip chip; 26 27 struct clk *clk; 27 28 }; ··· 83 82 buf[i++] = readb(io_base); 84 83 } 85 84 85 + static int orion_nand_attach_chip(struct nand_chip *chip) 86 + { 87 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 88 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 89 + 90 + return 0; 91 + } 92 + 93 + static const struct nand_controller_ops orion_nand_ops = { 94 + .attach_chip = orion_nand_attach_chip, 95 + }; 96 + 86 97 static int __init orion_nand_probe(struct platform_device *pdev) 87 98 { 88 99 struct orion_nand_info *info; ··· 113 100 return -ENOMEM; 114 101 nc = &info->chip; 115 102 mtd = nand_to_mtd(nc); 103 + 104 + nand_controller_init(&info->controller); 105 + info->controller.ops = &orion_nand_ops; 106 + nc->controller = &info->controller; 116 107 117 108 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 118 109 io_base = devm_ioremap_resource(&pdev->dev, res); ··· 156 139 nc->legacy.IO_ADDR_R = nc->legacy.IO_ADDR_W = io_base; 157 140 nc->legacy.cmd_ctrl = orion_nand_cmd_ctrl; 158 141 nc->legacy.read_buf = orion_nand_read_buf; 159 - nc->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 160 - nc->ecc.algo = NAND_ECC_ALGO_HAMMING; 161 142 162 143 if (board->chip_delay) 163 144 nc->legacy.chip_delay = board->chip_delay;
+17 -2
drivers/mtd/nand/raw/pasemi_nand.c
··· 29 29 30 30 static unsigned int lpcctl; 31 31 static struct mtd_info *pasemi_nand_mtd; 32 + static struct nand_controller controller; 32 33 static const char driver_name[] = "pasemi-nand"; 33 34 34 35 static void pasemi_read_buf(struct nand_chip *chip, u_char *buf, int len) ··· 74 73 return !!(inl(lpcctl) & LBICTRL_LPCCTL_NR); 75 74 } 76 75 76 + static int pasemi_attach_chip(struct nand_chip *chip) 77 + { 78 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 79 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 80 + 81 + return 0; 82 + } 83 + 84 + static const struct nand_controller_ops pasemi_ops = { 85 + .attach_chip = pasemi_attach_chip, 86 + }; 87 + 77 88 static int pasemi_nand_probe(struct platform_device *ofdev) 78 89 { 79 90 struct device *dev = &ofdev->dev; ··· 112 99 err = -ENOMEM; 113 100 goto out; 114 101 } 102 + 103 + controller.ops = &pasemi_ops; 104 + nand_controller_init(&controller); 105 + chip->controller = &controller; 115 106 116 107 pasemi_nand_mtd = nand_to_mtd(chip); 117 108 ··· 149 132 chip->legacy.read_buf = pasemi_read_buf; 150 133 chip->legacy.write_buf = pasemi_write_buf; 151 134 chip->legacy.chip_delay = 0; 152 - chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 153 - chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 154 135 155 136 /* Enable the following for a flash based bad block table */ 156 137 chip->bbt_options = NAND_BBT_USE_FLASH;
+17 -3
drivers/mtd/nand/raw/plat_nand.c
··· 14 14 #include <linux/mtd/platnand.h> 15 15 16 16 struct plat_nand_data { 17 + struct nand_controller controller; 17 18 struct nand_chip chip; 18 19 void __iomem *io_base; 20 + }; 21 + 22 + static int plat_nand_attach_chip(struct nand_chip *chip) 23 + { 24 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 25 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 26 + 27 + return 0; 28 + } 29 + 30 + static const struct nand_controller_ops plat_nand_ops = { 31 + .attach_chip = plat_nand_attach_chip, 19 32 }; 20 33 21 34 /* ··· 59 46 if (!data) 60 47 return -ENOMEM; 61 48 49 + data->controller.ops = &plat_nand_ops; 50 + nand_controller_init(&data->controller); 51 + data->chip.controller = &data->controller; 52 + 62 53 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 63 54 data->io_base = devm_ioremap_resource(&pdev->dev, res); 64 55 if (IS_ERR(data->io_base)) ··· 82 65 data->chip.legacy.chip_delay = pdata->chip.chip_delay; 83 66 data->chip.options |= pdata->chip.options; 84 67 data->chip.bbt_options |= pdata->chip.bbt_options; 85 - 86 - data->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 87 - data->chip.ecc.algo = NAND_ECC_ALGO_HAMMING; 88 68 89 69 platform_set_drvdata(pdev, data); 90 70
+27 -13
drivers/mtd/nand/raw/r852.c
··· 817 817 return ret; 818 818 } 819 819 820 + static int r852_attach_chip(struct nand_chip *chip) 821 + { 822 + if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 823 + return 0; 824 + 825 + chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED; 826 + chip->ecc.size = R852_DMA_LEN; 827 + chip->ecc.bytes = SM_OOB_SIZE; 828 + chip->ecc.strength = 2; 829 + chip->ecc.hwctl = r852_ecc_hwctl; 830 + chip->ecc.calculate = r852_ecc_calculate; 831 + chip->ecc.correct = r852_ecc_correct; 832 + 833 + /* TODO: hack */ 834 + chip->ecc.read_oob = r852_read_oob; 835 + 836 + return 0; 837 + } 838 + 839 + static const struct nand_controller_ops r852_ops = { 840 + .attach_chip = r852_attach_chip, 841 + }; 842 + 820 843 static int r852_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) 821 844 { 822 845 int error; ··· 881 858 chip->legacy.read_buf = r852_read_buf; 882 859 chip->legacy.write_buf = r852_write_buf; 883 860 884 - /* ecc */ 885 - chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 886 - chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED; 887 - chip->ecc.size = R852_DMA_LEN; 888 - chip->ecc.bytes = SM_OOB_SIZE; 889 - chip->ecc.strength = 2; 890 - chip->ecc.hwctl = r852_ecc_hwctl; 891 - chip->ecc.calculate = r852_ecc_calculate; 892 - chip->ecc.correct = r852_ecc_correct; 893 - 894 - /* TODO: hack */ 895 - chip->ecc.read_oob = r852_read_oob; 896 - 897 861 /* init our device structure */ 898 862 dev = kzalloc(sizeof(struct r852_device), GFP_KERNEL); 899 863 ··· 891 881 dev->chip = chip; 892 882 dev->pci_dev = pci_dev; 893 883 pci_set_drvdata(pci_dev, dev); 884 + 885 + nand_controller_init(&dev->controller); 886 + dev->controller.ops = &r852_ops; 887 + chip->controller = &dev->controller; 894 888 895 889 dev->bounce_buffer = dma_alloc_coherent(&pci_dev->dev, R852_DMA_LEN, 896 890 &dev->phys_bounce_buffer, GFP_KERNEL);
+1
drivers/mtd/nand/raw/r852.h
··· 104 104 #define DMA_MEMORY 1 105 105 106 106 struct r852_device { 107 + struct nand_controller controller; 107 108 void __iomem *mmio; /* mmio */ 108 109 struct nand_chip *chip; /* nand chip backpointer */ 109 110 struct pci_dev *pci_dev; /* pci backpointer */
+24 -8
drivers/mtd/nand/raw/sharpsl.c
··· 20 20 #include <linux/io.h> 21 21 22 22 struct sharpsl_nand { 23 + struct nand_controller controller; 23 24 struct nand_chip chip; 24 25 25 26 void __iomem *io; ··· 97 96 return readb(sharpsl->io + ECCCNTR) != 0; 98 97 } 99 98 99 + static int sharpsl_attach_chip(struct nand_chip *chip) 100 + { 101 + if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 102 + return 0; 103 + 104 + chip->ecc.size = 256; 105 + chip->ecc.bytes = 3; 106 + chip->ecc.strength = 1; 107 + chip->ecc.hwctl = sharpsl_nand_enable_hwecc; 108 + chip->ecc.calculate = sharpsl_nand_calculate_ecc; 109 + chip->ecc.correct = nand_correct_data; 110 + 111 + return 0; 112 + } 113 + 114 + static const struct nand_controller_ops sharpsl_ops = { 115 + .attach_chip = sharpsl_attach_chip, 116 + }; 117 + 100 118 /* 101 119 * Main initialization routine 102 120 */ ··· 156 136 /* Get pointer to private data */ 157 137 this = (struct nand_chip *)(&sharpsl->chip); 158 138 139 + nand_controller_init(&sharpsl->controller); 140 + sharpsl->controller.ops = &sharpsl_ops; 141 + this->controller = &sharpsl->controller; 142 + 159 143 /* Link the private data with the MTD structure */ 160 144 mtd = nand_to_mtd(this); 161 145 mtd->dev.parent = &pdev->dev; ··· 180 156 this->legacy.dev_ready = sharpsl_nand_dev_ready; 181 157 /* 15 us command delay time */ 182 158 this->legacy.chip_delay = 15; 183 - /* set eccmode using hardware ECC */ 184 - this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 185 - this->ecc.size = 256; 186 - this->ecc.bytes = 3; 187 - this->ecc.strength = 1; 188 159 this->badblock_pattern = data->badblock_pattern; 189 - this->ecc.hwctl = sharpsl_nand_enable_hwecc; 190 - this->ecc.calculate = sharpsl_nand_calculate_ecc; 191 - this->ecc.correct = nand_correct_data; 192 160 193 161 /* Scan to find existence of the device */ 194 162 err = nand_scan(this, 1);
+17 -4
drivers/mtd/nand/raw/socrates_nand.c
··· 22 22 #define FPGA_NAND_DATA_SHIFT 16 23 23 24 24 struct socrates_nand_host { 25 + struct nand_controller controller; 25 26 struct nand_chip nand_chip; 26 27 void __iomem *io_base; 27 28 struct device *dev; ··· 117 116 return 1; 118 117 } 119 118 119 + static int socrates_attach_chip(struct nand_chip *chip) 120 + { 121 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 122 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 123 + 124 + return 0; 125 + } 126 + 127 + static const struct nand_controller_ops socrates_ops = { 128 + .attach_chip = socrates_attach_chip, 129 + }; 130 + 120 131 /* 121 132 * Probe for the NAND device. 122 133 */ ··· 154 141 mtd = nand_to_mtd(nand_chip); 155 142 host->dev = &ofdev->dev; 156 143 144 + nand_controller_init(&host->controller); 145 + host->controller.ops = &socrates_ops; 146 + nand_chip->controller = &host->controller; 147 + 157 148 /* link the private data structures */ 158 149 nand_set_controller_data(nand_chip, host); 159 150 nand_set_flash_node(nand_chip, ofdev->dev.of_node); ··· 169 152 nand_chip->legacy.write_buf = socrates_nand_write_buf; 170 153 nand_chip->legacy.read_buf = socrates_nand_read_buf; 171 154 nand_chip->legacy.dev_ready = socrates_nand_device_ready; 172 - 173 - /* enable ECC */ 174 - nand_chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 175 - nand_chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 176 155 177 156 /* TODO: I have no idea what real delay is. */ 178 157 nand_chip->legacy.chip_delay = 20; /* 20us command delay time */
+24 -9
drivers/mtd/nand/raw/tmio_nand.c
··· 103 103 /*--------------------------------------------------------------------------*/ 104 104 105 105 struct tmio_nand { 106 + struct nand_controller controller; 106 107 struct nand_chip chip; 107 108 struct completion comp; 108 109 ··· 356 355 cell->disable(dev); 357 356 } 358 357 358 + static int tmio_attach_chip(struct nand_chip *chip) 359 + { 360 + if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 361 + return 0; 362 + 363 + chip->ecc.size = 512; 364 + chip->ecc.bytes = 6; 365 + chip->ecc.strength = 2; 366 + chip->ecc.hwctl = tmio_nand_enable_hwecc; 367 + chip->ecc.calculate = tmio_nand_calculate_ecc; 368 + chip->ecc.correct = tmio_nand_correct_data; 369 + 370 + return 0; 371 + } 372 + 373 + static const struct nand_controller_ops tmio_ops = { 374 + .attach_chip = tmio_attach_chip, 375 + }; 376 + 359 377 static int tmio_probe(struct platform_device *dev) 360 378 { 361 379 struct tmio_nand_data *data = dev_get_platdata(&dev->dev); ··· 405 385 mtd->name = "tmio-nand"; 406 386 mtd->dev.parent = &dev->dev; 407 387 388 + nand_controller_init(&tmio->controller); 389 + tmio->controller.ops = &tmio_ops; 390 + nand_chip->controller = &tmio->controller; 391 + 408 392 tmio->ccr = devm_ioremap(&dev->dev, ccr->start, resource_size(ccr)); 409 393 if (!tmio->ccr) 410 394 return -EIO; ··· 432 408 nand_chip->legacy.read_byte = tmio_nand_read_byte; 433 409 nand_chip->legacy.write_buf = tmio_nand_write_buf; 434 410 nand_chip->legacy.read_buf = tmio_nand_read_buf; 435 - 436 - /* set eccmode using hardware ECC */ 437 - nand_chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 438 - nand_chip->ecc.size = 512; 439 - nand_chip->ecc.bytes = 6; 440 - nand_chip->ecc.strength = 2; 441 - nand_chip->ecc.hwctl = tmio_nand_enable_hwecc; 442 - nand_chip->ecc.calculate = tmio_nand_calculate_ecc; 443 - nand_chip->ecc.correct = tmio_nand_correct_data; 444 411 445 412 if (data) 446 413 nand_chip->badblock_pattern = data->badblock_pattern;
+9 -5
drivers/mtd/nand/raw/txx9ndfmc.c
··· 253 253 { 254 254 struct mtd_info *mtd = nand_to_mtd(chip); 255 255 256 + if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 257 + return 0; 258 + 259 + chip->ecc.strength = 1; 260 + 256 261 if (mtd->writesize >= 512) { 257 262 chip->ecc.size = 512; 258 263 chip->ecc.bytes = 6; ··· 265 260 chip->ecc.size = 256; 266 261 chip->ecc.bytes = 3; 267 262 } 263 + 264 + chip->ecc.calculate = txx9ndfmc_calculate_ecc; 265 + chip->ecc.correct = txx9ndfmc_correct_data; 266 + chip->ecc.hwctl = txx9ndfmc_enable_hwecc; 268 267 269 268 return 0; 270 269 } ··· 335 326 chip->legacy.write_buf = txx9ndfmc_write_buf; 336 327 chip->legacy.cmd_ctrl = txx9ndfmc_cmd_ctrl; 337 328 chip->legacy.dev_ready = txx9ndfmc_dev_ready; 338 - chip->ecc.calculate = txx9ndfmc_calculate_ecc; 339 - chip->ecc.correct = txx9ndfmc_correct_data; 340 - chip->ecc.hwctl = txx9ndfmc_enable_hwecc; 341 - chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 342 - chip->ecc.strength = 1; 343 329 chip->legacy.chip_delay = 100; 344 330 chip->controller = &drvdata->controller; 345 331
+16 -2
drivers/mtd/nand/raw/xway_nand.c
··· 62 62 #define NAND_CON_NANDM 1 63 63 64 64 struct xway_nand_data { 65 + struct nand_controller controller; 65 66 struct nand_chip chip; 66 67 unsigned long csflags; 67 68 void __iomem *nandaddr; ··· 146 145 xway_writeb(nand_to_mtd(chip), NAND_WRITE_DATA, buf[i]); 147 146 } 148 147 148 + static int xway_attach_chip(struct nand_chip *chip) 149 + { 150 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 151 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 152 + 153 + return 0; 154 + } 155 + 156 + static const struct nand_controller_ops xway_nand_ops = { 157 + .attach_chip = xway_attach_chip, 158 + }; 159 + 149 160 /* 150 161 * Probe for the NAND device. 151 162 */ ··· 193 180 data->chip.legacy.read_byte = xway_read_byte; 194 181 data->chip.legacy.chip_delay = 30; 195 182 196 - data->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 197 - data->chip.ecc.algo = NAND_ECC_ALGO_HAMMING; 183 + nand_controller_init(&data->controller); 184 + data->controller.ops = &xway_nand_ops; 185 + data->chip.controller = &data->controller; 198 186 199 187 platform_set_drvdata(pdev, data); 200 188 nand_set_controller_data(&data->chip, data);