Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2023-01-27' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Fairly small this week as well, i915 has a memory leak fix and some
minor changes, and amdgpu has some MST fixes, and some other minor
ones:
drm:
- DP MST kref fix
- fb_helper: check return value
i915:
- Fix BSC default context for Meteor Lake
- Fix selftest-scheduler's modify_type
- memory leak fix
amdgpu:
- GC11.x fixes
- SMU13.0.0 fix
- Freesync video fix
- DP MST fixes
- build fix"
* tag 'drm-fixes-2023-01-27' of git://anongit.freedesktop.org/drm/drm:
amdgpu: fix build on non-DCN platforms.
drm/amd/display: Fix timing not changning when freesync video is enabled
drm/display/dp_mst: Correct the kref of port.
drm/amdgpu/display/mst: update mst_mgr relevant variable when long HPD
drm/amdgpu/display/mst: limit payload to be updated one by one
drm/amdgpu/display/mst: Fix mst_state->pbn_div and slot count assignments
drm/amdgpu: declare firmware for new MES 11.0.4
drm/amdgpu: enable imu firmware for GC 11.0.4
drm/amd/pm: add missing AllowIHInterrupt message mapping for SMU13.0.0
drm/amdgpu: remove unconditional trap enable on add gfx11 queues
drm/fb-helper: Use a per-driver FB deferred I/O handler
drm/fb-helper: Check fb_deferred_io_init() return value
drm/i915/selftest: fix intel_selftest_modify_policy argument types
drm/i915/mtl: Fix bcs default context
drm/i915: Fix a memory leak with reused mmap_offset
drm/drm_vma_manager: Add drm_vma_node_allow_once()
+167
-89
+1
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
+1
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
+2
-1
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+2
-1
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
···
40
40
MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin");
41
41
MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin");
42
42
MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin");
43
+
MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin");
44
+
MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin");
43
45
44
46
static int mes_v11_0_hw_fini(void *handle);
45
47
static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev);
···
198
196
mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
199
197
mes_add_queue_pkt.tma_addr = input->tma_addr;
200
198
mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
201
-
mes_add_queue_pkt.trap_en = 1;
202
199
203
200
/* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
204
201
mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
+31
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+31
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
8881
8881
if (!dm_old_crtc_state->stream)
8882
8882
goto skip_modeset;
8883
8883
8884
+
/* Unset freesync video if it was active before */
8885
+
if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
8886
+
dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
8887
+
dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
8888
+
}
8889
+
8890
+
/* Now check if we should set freesync video mode */
8884
8891
if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
8885
8892
is_timing_unchanged_for_freesync(new_crtc_state,
8886
8893
old_crtc_state)) {
···
9504
9497
bool lock_and_validation_needed = false;
9505
9498
struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9506
9499
#if defined(CONFIG_DRM_AMD_DC_DCN)
9500
+
struct drm_dp_mst_topology_mgr *mgr;
9501
+
struct drm_dp_mst_topology_state *mst_state;
9507
9502
struct dsc_mst_fairness_vars vars[MAX_PIPES];
9508
9503
#endif
9509
9504
···
9753
9744
9754
9745
lock_and_validation_needed = true;
9755
9746
}
9747
+
9748
+
#if defined(CONFIG_DRM_AMD_DC_DCN)
9749
+
/* set the slot info for each mst_state based on the link encoding format */
9750
+
for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
9751
+
struct amdgpu_dm_connector *aconnector;
9752
+
struct drm_connector *connector;
9753
+
struct drm_connector_list_iter iter;
9754
+
u8 link_coding_cap;
9755
+
9756
+
drm_connector_list_iter_begin(dev, &iter);
9757
+
drm_for_each_connector_iter(connector, &iter) {
9758
+
if (connector->index == mst_state->mgr->conn_base_id) {
9759
+
aconnector = to_amdgpu_dm_connector(connector);
9760
+
link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
9761
+
drm_dp_mst_update_slots(mst_state, link_coding_cap);
9762
+
9763
+
break;
9764
+
}
9765
+
}
9766
+
drm_connector_list_iter_end(&iter);
9767
+
}
9768
+
#endif
9756
9769
9757
9770
/**
9758
9771
* Streams and planes are reset when there are changes that affect
+39
-12
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+39
-12
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
···
120
120
}
121
121
122
122
static void
123
-
fill_dc_mst_payload_table_from_drm(struct drm_dp_mst_topology_state *mst_state,
124
-
struct amdgpu_dm_connector *aconnector,
123
+
fill_dc_mst_payload_table_from_drm(struct dc_link *link,
124
+
bool enable,
125
+
struct drm_dp_mst_atomic_payload *target_payload,
125
126
struct dc_dp_mst_stream_allocation_table *table)
126
127
{
127
128
struct dc_dp_mst_stream_allocation_table new_table = { 0 };
128
129
struct dc_dp_mst_stream_allocation *sa;
129
-
struct drm_dp_mst_atomic_payload *payload;
130
+
struct link_mst_stream_allocation_table copy_of_link_table =
131
+
link->mst_stream_alloc_table;
132
+
133
+
int i;
134
+
int current_hw_table_stream_cnt = copy_of_link_table.stream_count;
135
+
struct link_mst_stream_allocation *dc_alloc;
136
+
137
+
/* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/
138
+
if (enable) {
139
+
dc_alloc =
140
+
©_of_link_table.stream_allocations[current_hw_table_stream_cnt];
141
+
dc_alloc->vcp_id = target_payload->vcpi;
142
+
dc_alloc->slot_count = target_payload->time_slots;
143
+
} else {
144
+
for (i = 0; i < copy_of_link_table.stream_count; i++) {
145
+
dc_alloc =
146
+
©_of_link_table.stream_allocations[i];
147
+
148
+
if (dc_alloc->vcp_id == target_payload->vcpi) {
149
+
dc_alloc->vcp_id = 0;
150
+
dc_alloc->slot_count = 0;
151
+
break;
152
+
}
153
+
}
154
+
ASSERT(i != copy_of_link_table.stream_count);
155
+
}
130
156
131
157
/* Fill payload info*/
132
-
list_for_each_entry(payload, &mst_state->payloads, next) {
133
-
if (payload->delete)
134
-
continue;
135
-
136
-
sa = &new_table.stream_allocations[new_table.stream_count];
137
-
sa->slot_count = payload->time_slots;
138
-
sa->vcp_id = payload->vcpi;
139
-
new_table.stream_count++;
158
+
for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
159
+
dc_alloc =
160
+
©_of_link_table.stream_allocations[i];
161
+
if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) {
162
+
sa = &new_table.stream_allocations[new_table.stream_count];
163
+
sa->slot_count = dc_alloc->slot_count;
164
+
sa->vcp_id = dc_alloc->vcp_id;
165
+
new_table.stream_count++;
166
+
}
140
167
}
141
168
142
169
/* Overwrite the old table */
···
212
185
* AUX message. The sequence is slot 1-63 allocated sequence for each
213
186
* stream. AMD ASIC stream slot allocation should follow the same
214
187
* sequence. copy DRM MST allocation to dc */
215
-
fill_dc_mst_payload_table_from_drm(mst_state, aconnector, proposed_table);
188
+
fill_dc_mst_payload_table_from_drm(stream->link, enable, payload, proposed_table);
216
189
217
190
return true;
218
191
}
-5
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
-5
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
···
903
903
if (IS_ERR(mst_state))
904
904
return PTR_ERR(mst_state);
905
905
906
-
mst_state->pbn_div = dm_mst_get_pbn_divider(dc_link);
907
-
#if defined(CONFIG_DRM_AMD_DC_DCN)
908
-
drm_dp_mst_update_slots(mst_state, dc_link_dp_mst_decide_link_encoding_format(dc_link));
909
-
#endif
910
-
911
906
/* Set up params */
912
907
for (i = 0; i < dc_state->stream_count; i++) {
913
908
struct dc_dsc_policy dsc_policy = {0};
+12
-2
drivers/gpu/drm/amd/display/dc/core/dc_link.c
+12
-2
drivers/gpu/drm/amd/display/dc/core/dc_link.c
···
3995
3995
struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3996
3996
int i;
3997
3997
bool mst_mode = (link->type == dc_connection_mst_branch);
3998
+
/* adjust for drm changes*/
3999
+
bool update_drm_mst_state = true;
3998
4000
const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3999
4001
const struct dc_link_settings empty_link_settings = {0};
4000
4002
DC_LOGGER_INIT(link->ctx->logger);
4003
+
4001
4004
4002
4005
/* deallocate_mst_payload is called before disable link. When mode or
4003
4006
* disable/enable monitor, new stream is created which is not in link
···
4017
4014
&empty_link_settings,
4018
4015
avg_time_slots_per_mtp);
4019
4016
4020
-
if (mst_mode) {
4017
+
if (mst_mode || update_drm_mst_state) {
4021
4018
/* when link is in mst mode, reply on mst manager to remove
4022
4019
* payload
4023
4020
*/
···
4080
4077
stream->ctx,
4081
4078
stream);
4082
4079
4080
+
if (!update_drm_mst_state)
4081
+
dm_helpers_dp_mst_send_payload_allocation(
4082
+
stream->ctx,
4083
+
stream,
4084
+
false);
4085
+
}
4086
+
4087
+
if (update_drm_mst_state)
4083
4088
dm_helpers_dp_mst_send_payload_allocation(
4084
4089
stream->ctx,
4085
4090
stream,
4086
4091
false);
4087
-
}
4088
4092
4089
4093
return DC_OK;
4090
4094
}
+1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
···
145
145
MSG_MAP(SetBadMemoryPagesRetiredFlagsPerChannel,
146
146
PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel, 0),
147
147
MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow, 0),
148
+
MSG_MAP(AllowIHHostInterrupt, PPSMC_MSG_AllowIHHostInterrupt, 0),
148
149
};
149
150
150
151
static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
+3
-1
drivers/gpu/drm/display/drm_dp_mst_topology.c
+3
-1
drivers/gpu/drm/display/drm_dp_mst_topology.c
···
3372
3372
3373
3373
mgr->payload_count--;
3374
3374
mgr->next_start_slot -= payload->time_slots;
3375
+
3376
+
if (payload->delete)
3377
+
drm_dp_mst_put_port_malloc(payload->port);
3375
3378
}
3376
3379
EXPORT_SYMBOL(drm_dp_remove_payload);
3377
3380
···
4330
4327
4331
4328
drm_dbg_atomic(mgr->dev, "[MST PORT:%p] TU %d -> 0\n", port, payload->time_slots);
4332
4329
if (!payload->delete) {
4333
-
drm_dp_mst_put_port_malloc(port);
4334
4330
payload->pbn = 0;
4335
4331
payload->delete = true;
4336
4332
topology_state->payload_mask &= ~BIT(payload->vcpi - 1);
+8
-7
drivers/gpu/drm/drm_fbdev_generic.c
+8
-7
drivers/gpu/drm/drm_fbdev_generic.c
···
171
171
.fb_imageblit = drm_fbdev_fb_imageblit,
172
172
};
173
173
174
-
static struct fb_deferred_io drm_fbdev_defio = {
175
-
.delay = HZ / 20,
176
-
.deferred_io = drm_fb_helper_deferred_io,
177
-
};
178
-
179
174
/*
180
175
* This function uses the client API to create a framebuffer backed by a dumb buffer.
181
176
*/
···
217
222
return -ENOMEM;
218
223
fbi->flags |= FBINFO_VIRTFB | FBINFO_READS_FAST;
219
224
220
-
fbi->fbdefio = &drm_fbdev_defio;
221
-
fb_deferred_io_init(fbi);
225
+
/* Set a default deferred I/O handler */
226
+
fb_helper->fbdefio.delay = HZ / 20;
227
+
fb_helper->fbdefio.deferred_io = drm_fb_helper_deferred_io;
228
+
229
+
fbi->fbdefio = &fb_helper->fbdefio;
230
+
ret = fb_deferred_io_init(fbi);
231
+
if (ret)
232
+
return ret;
222
233
} else {
223
234
/* buffer is mapped for HW framebuffer */
224
235
ret = drm_client_buffer_vmap(fb_helper->buffer, &map);
+54
-22
drivers/gpu/drm/drm_vma_manager.c
+54
-22
drivers/gpu/drm/drm_vma_manager.c
···
240
240
}
241
241
EXPORT_SYMBOL(drm_vma_offset_remove);
242
242
243
-
/**
244
-
* drm_vma_node_allow - Add open-file to list of allowed users
245
-
* @node: Node to modify
246
-
* @tag: Tag of file to remove
247
-
*
248
-
* Add @tag to the list of allowed open-files for this node. If @tag is
249
-
* already on this list, the ref-count is incremented.
250
-
*
251
-
* The list of allowed-users is preserved across drm_vma_offset_add() and
252
-
* drm_vma_offset_remove() calls. You may even call it if the node is currently
253
-
* not added to any offset-manager.
254
-
*
255
-
* You must remove all open-files the same number of times as you added them
256
-
* before destroying the node. Otherwise, you will leak memory.
257
-
*
258
-
* This is locked against concurrent access internally.
259
-
*
260
-
* RETURNS:
261
-
* 0 on success, negative error code on internal failure (out-of-mem)
262
-
*/
263
-
int drm_vma_node_allow(struct drm_vma_offset_node *node, struct drm_file *tag)
243
+
static int vma_node_allow(struct drm_vma_offset_node *node,
244
+
struct drm_file *tag, bool ref_counted)
264
245
{
265
246
struct rb_node **iter;
266
247
struct rb_node *parent = NULL;
···
263
282
entry = rb_entry(*iter, struct drm_vma_offset_file, vm_rb);
264
283
265
284
if (tag == entry->vm_tag) {
266
-
entry->vm_count++;
285
+
if (ref_counted)
286
+
entry->vm_count++;
267
287
goto unlock;
268
288
} else if (tag > entry->vm_tag) {
269
289
iter = &(*iter)->rb_right;
···
289
307
kfree(new);
290
308
return ret;
291
309
}
310
+
311
+
/**
312
+
* drm_vma_node_allow - Add open-file to list of allowed users
313
+
* @node: Node to modify
314
+
* @tag: Tag of file to remove
315
+
*
316
+
* Add @tag to the list of allowed open-files for this node. If @tag is
317
+
* already on this list, the ref-count is incremented.
318
+
*
319
+
* The list of allowed-users is preserved across drm_vma_offset_add() and
320
+
* drm_vma_offset_remove() calls. You may even call it if the node is currently
321
+
* not added to any offset-manager.
322
+
*
323
+
* You must remove all open-files the same number of times as you added them
324
+
* before destroying the node. Otherwise, you will leak memory.
325
+
*
326
+
* This is locked against concurrent access internally.
327
+
*
328
+
* RETURNS:
329
+
* 0 on success, negative error code on internal failure (out-of-mem)
330
+
*/
331
+
int drm_vma_node_allow(struct drm_vma_offset_node *node, struct drm_file *tag)
332
+
{
333
+
return vma_node_allow(node, tag, true);
334
+
}
292
335
EXPORT_SYMBOL(drm_vma_node_allow);
336
+
337
+
/**
338
+
* drm_vma_node_allow_once - Add open-file to list of allowed users
339
+
* @node: Node to modify
340
+
* @tag: Tag of file to remove
341
+
*
342
+
* Add @tag to the list of allowed open-files for this node.
343
+
*
344
+
* The list of allowed-users is preserved across drm_vma_offset_add() and
345
+
* drm_vma_offset_remove() calls. You may even call it if the node is currently
346
+
* not added to any offset-manager.
347
+
*
348
+
* This is not ref-counted unlike drm_vma_node_allow() hence drm_vma_node_revoke()
349
+
* should only be called once after this.
350
+
*
351
+
* This is locked against concurrent access internally.
352
+
*
353
+
* RETURNS:
354
+
* 0 on success, negative error code on internal failure (out-of-mem)
355
+
*/
356
+
int drm_vma_node_allow_once(struct drm_vma_offset_node *node, struct drm_file *tag)
357
+
{
358
+
return vma_node_allow(node, tag, false);
359
+
}
360
+
EXPORT_SYMBOL(drm_vma_node_allow_once);
293
361
294
362
/**
295
363
* drm_vma_node_revoke - Remove open-file from list of allowed users
+1
-1
drivers/gpu/drm/i915/gem/i915_gem_mman.c
+1
-1
drivers/gpu/drm/i915/gem/i915_gem_mman.c
+1
-36
drivers/gpu/drm/i915/gt/intel_lrc.c
+1
-36
drivers/gpu/drm/i915/gt/intel_lrc.c
···
288
288
END
289
289
};
290
290
291
-
static const u8 mtl_xcs_offsets[] = {
292
-
NOP(1),
293
-
LRI(13, POSTED),
294
-
REG16(0x244),
295
-
REG(0x034),
296
-
REG(0x030),
297
-
REG(0x038),
298
-
REG(0x03c),
299
-
REG(0x168),
300
-
REG(0x140),
301
-
REG(0x110),
302
-
REG(0x1c0),
303
-
REG(0x1c4),
304
-
REG(0x1c8),
305
-
REG(0x180),
306
-
REG16(0x2b4),
307
-
NOP(4),
308
-
309
-
NOP(1),
310
-
LRI(9, POSTED),
311
-
REG16(0x3a8),
312
-
REG16(0x28c),
313
-
REG16(0x288),
314
-
REG16(0x284),
315
-
REG16(0x280),
316
-
REG16(0x27c),
317
-
REG16(0x278),
318
-
REG16(0x274),
319
-
REG16(0x270),
320
-
321
-
END
322
-
};
323
-
324
291
static const u8 gen8_rcs_offsets[] = {
325
292
NOP(1),
326
293
LRI(14, POSTED),
···
706
739
else
707
740
return gen8_rcs_offsets;
708
741
} else {
709
-
if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
710
-
return mtl_xcs_offsets;
711
-
else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
742
+
if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
712
743
return dg2_xcs_offsets;
713
744
else if (GRAPHICS_VER(engine->i915) >= 12)
714
745
return gen12_xcs_offsets;
+1
-2
drivers/gpu/drm/i915/selftests/intel_scheduler_helpers.c
+1
-2
drivers/gpu/drm/i915/selftests/intel_scheduler_helpers.c
+12
include/drm/drm_fb_helper.h
+12
include/drm/drm_fb_helper.h
···
208
208
* the smem_start field should always be cleared to zero.
209
209
*/
210
210
bool hint_leak_smem_start;
211
+
212
+
#ifdef CONFIG_FB_DEFERRED_IO
213
+
/**
214
+
* @fbdefio:
215
+
*
216
+
* Temporary storage for the driver's FB deferred I/O handler. If the
217
+
* driver uses the DRM fbdev emulation layer, this is set by the core
218
+
* to a generic deferred I/O handler if a driver is preferring to use
219
+
* a shadow buffer.
220
+
*/
221
+
struct fb_deferred_io fbdefio;
222
+
#endif
211
223
};
212
224
213
225
static inline struct drm_fb_helper *
+1
include/drm/drm_vma_manager.h
+1
include/drm/drm_vma_manager.h
···
74
74
struct drm_vma_offset_node *node);
75
75
76
76
int drm_vma_node_allow(struct drm_vma_offset_node *node, struct drm_file *tag);
77
+
int drm_vma_node_allow_once(struct drm_vma_offset_node *node, struct drm_file *tag);
77
78
void drm_vma_node_revoke(struct drm_vma_offset_node *node,
78
79
struct drm_file *tag);
79
80
bool drm_vma_node_is_allowed(struct drm_vma_offset_node *node,