Merge tag 'iommu-fixes-v5.3-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu

+35 -5

drivers/iommu/amd_iommu.c

··· 1143 1143 iommu_completion_wait(iommu); 1144 1144 } 1145 1145 1146 + static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id) 1147 + { 1148 + struct iommu_cmd cmd; 1149 + 1150 + build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1151 + dom_id, 1); 1152 + iommu_queue_command(iommu, &cmd); 1153 + 1154 + iommu_completion_wait(iommu); 1155 + } 1156 + 1146 1157 static void amd_iommu_flush_all(struct amd_iommu *iommu) 1147 1158 { 1148 1159 struct iommu_cmd cmd; ··· 1435 1424 * another level increases the size of the address space by 9 bits to a size up 1436 1425 * to 64 bits. 1437 1426 */ 1438 - static bool increase_address_space(struct protection_domain *domain, 1427 + static void increase_address_space(struct protection_domain *domain, 1439 1428 gfp_t gfp) 1440 1429 { 1430 + unsigned long flags; 1441 1431 u64 *pte; 1442 1432 1443 - if (domain->mode == PAGE_MODE_6_LEVEL) 1433 + spin_lock_irqsave(&domain->lock, flags); 1434 + 1435 + if (WARN_ON_ONCE(domain->mode == PAGE_MODE_6_LEVEL)) 1444 1436 /* address space already 64 bit large */ 1445 - return false; 1437 + goto out; 1446 1438 1447 1439 pte = (void *)get_zeroed_page(gfp); 1448 1440 if (!pte) 1449 - return false; 1441 + goto out; 1450 1442 1451 1443 *pte = PM_LEVEL_PDE(domain->mode, 1452 1444 iommu_virt_to_phys(domain->pt_root)); ··· 1457 1443 domain->mode += 1; 1458 1444 domain->updated = true; 1459 1445 1460 - return true; 1446 + out: 1447 + spin_unlock_irqrestore(&domain->lock, flags); 1448 + 1449 + return; 1461 1450 } 1462 1451 1463 1452 static u64 *alloc_pte(struct protection_domain *domain, ··· 1890 1873 { 1891 1874 u64 pte_root = 0; 1892 1875 u64 flags = 0; 1876 + u32 old_domid; 1893 1877 1894 1878 if (domain->mode != PAGE_MODE_NONE) 1895 1879 pte_root = iommu_virt_to_phys(domain->pt_root); ··· 1940 1922 flags &= ~DEV_DOMID_MASK; 1941 1923 flags |= domain->id; 1942 1924 1925 + old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK; 1943 1926 amd_iommu_dev_table[devid].data[1] = flags; 1944 1927 amd_iommu_dev_table[devid].data[0] = pte_root; 1928 + 1929 + /* 1930 + * A kdump kernel might be replacing a domain ID that was copied from 1931 + * the previous kernel--if so, it needs to flush the translation cache 1932 + * entries for the old domain ID that is being overwritten 1933 + */ 1934 + if (old_domid) { 1935 + struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; 1936 + 1937 + amd_iommu_flush_tlb_domid(iommu, old_domid); 1938 + } 1945 1939 } 1946 1940 1947 1941 static void clear_dte_entry(u16 devid)

+53 -2

drivers/iommu/intel-iommu.c

··· 339 339 static void domain_remove_dev_info(struct dmar_domain *domain); 340 340 static void dmar_remove_one_dev_info(struct device *dev); 341 341 static void __dmar_remove_one_dev_info(struct device_domain_info *info); 342 + static void domain_context_clear(struct intel_iommu *iommu, 343 + struct device *dev); 342 344 static int domain_detach_iommu(struct dmar_domain *domain, 343 345 struct intel_iommu *iommu); 344 346 static bool device_is_rmrr_locked(struct device *dev); ··· 2107 2105 return ret; 2108 2106 } 2109 2107 2108 + struct domain_context_mapping_data { 2109 + struct dmar_domain *domain; 2110 + struct intel_iommu *iommu; 2111 + struct pasid_table *table; 2112 + }; 2113 + 2114 + static int domain_context_mapping_cb(struct pci_dev *pdev, 2115 + u16 alias, void *opaque) 2116 + { 2117 + struct domain_context_mapping_data *data = opaque; 2118 + 2119 + return domain_context_mapping_one(data->domain, data->iommu, 2120 + data->table, PCI_BUS_NUM(alias), 2121 + alias & 0xff); 2122 + } 2123 + 2110 2124 static int 2111 2125 domain_context_mapping(struct dmar_domain *domain, struct device *dev) 2112 2126 { 2127 + struct domain_context_mapping_data data; 2113 2128 struct pasid_table *table; 2114 2129 struct intel_iommu *iommu; 2115 2130 u8 bus, devfn; ··· 2136 2117 return -ENODEV; 2137 2118 2138 2119 table = intel_pasid_get_table(dev); 2139 - return domain_context_mapping_one(domain, iommu, table, bus, devfn); 2120 + 2121 + if (!dev_is_pci(dev)) 2122 + return domain_context_mapping_one(domain, iommu, table, 2123 + bus, devfn); 2124 + 2125 + data.domain = domain; 2126 + data.iommu = iommu; 2127 + data.table = table; 2128 + 2129 + return pci_for_each_dma_alias(to_pci_dev(dev), 2130 + &domain_context_mapping_cb, &data); 2140 2131 } 2141 2132 2142 2133 static int domain_context_mapped_cb(struct pci_dev *pdev, ··· 4788 4759 return ret; 4789 4760 } 4790 4761 4762 + static int domain_context_clear_one_cb(struct pci_dev *pdev, u16 alias, void *opaque) 4763 + { 4764 + struct intel_iommu *iommu = opaque; 4765 + 4766 + domain_context_clear_one(iommu, PCI_BUS_NUM(alias), alias & 0xff); 4767 + return 0; 4768 + } 4769 + 4770 + /* 4771 + * NB - intel-iommu lacks any sort of reference counting for the users of 4772 + * dependent devices. If multiple endpoints have intersecting dependent 4773 + * devices, unbinding the driver from any one of them will possibly leave 4774 + * the others unable to operate. 4775 + */ 4776 + static void domain_context_clear(struct intel_iommu *iommu, struct device *dev) 4777 + { 4778 + if (!iommu || !dev || !dev_is_pci(dev)) 4779 + return; 4780 + 4781 + pci_for_each_dma_alias(to_pci_dev(dev), &domain_context_clear_one_cb, iommu); 4782 + } 4783 + 4791 4784 static void __dmar_remove_one_dev_info(struct device_domain_info *info) 4792 4785 { 4793 4786 struct dmar_domain *domain; ··· 4830 4779 PASID_RID2PASID); 4831 4780 4832 4781 iommu_disable_dev_iotlb(info); 4833 - domain_context_clear_one(iommu, info->bus, info->devfn); 4782 + domain_context_clear(iommu, info->dev); 4834 4783 intel_pasid_free_table(info->dev); 4835 4784 } 4836 4785

+15 -21

drivers/iommu/intel-svm.c

··· 100 100 } 101 101 102 102 static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev, 103 - unsigned long address, unsigned long pages, int ih, int gl) 103 + unsigned long address, unsigned long pages, int ih) 104 104 { 105 105 struct qi_desc desc; 106 106 107 - if (pages == -1) { 108 - /* For global kernel pages we have to flush them in *all* PASIDs 109 - * because that's the only option the hardware gives us. Despite 110 - * the fact that they are actually only accessible through one. */ 111 - if (gl) 112 - desc.qw0 = QI_EIOTLB_PASID(svm->pasid) | 113 - QI_EIOTLB_DID(sdev->did) | 114 - QI_EIOTLB_GRAN(QI_GRAN_ALL_ALL) | 115 - QI_EIOTLB_TYPE; 116 - else 117 - desc.qw0 = QI_EIOTLB_PASID(svm->pasid) | 118 - QI_EIOTLB_DID(sdev->did) | 119 - QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | 120 - QI_EIOTLB_TYPE; 107 + /* 108 + * Do PASID granu IOTLB invalidation if page selective capability is 109 + * not available. 110 + */ 111 + if (pages == -1 || !cap_pgsel_inv(svm->iommu->cap)) { 112 + desc.qw0 = QI_EIOTLB_PASID(svm->pasid) | 113 + QI_EIOTLB_DID(sdev->did) | 114 + QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | 115 + QI_EIOTLB_TYPE; 121 116 desc.qw1 = 0; 122 117 } else { 123 118 int mask = ilog2(__roundup_pow_of_two(pages)); ··· 122 127 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | 123 128 QI_EIOTLB_TYPE; 124 129 desc.qw1 = QI_EIOTLB_ADDR(address) | 125 - QI_EIOTLB_GL(gl) | 126 130 QI_EIOTLB_IH(ih) | 127 131 QI_EIOTLB_AM(mask); 128 132 } ··· 156 162 } 157 163 158 164 static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address, 159 - unsigned long pages, int ih, int gl) 165 + unsigned long pages, int ih) 160 166 { 161 167 struct intel_svm_dev *sdev; 162 168 163 169 rcu_read_lock(); 164 170 list_for_each_entry_rcu(sdev, &svm->devs, list) 165 - intel_flush_svm_range_dev(svm, sdev, address, pages, ih, gl); 171 + intel_flush_svm_range_dev(svm, sdev, address, pages, ih); 166 172 rcu_read_unlock(); 167 173 } 168 174 ··· 174 180 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier); 175 181 176 182 intel_flush_svm_range(svm, start, 177 - (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0, 0); 183 + (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0); 178 184 } 179 185 180 186 static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm) ··· 197 203 rcu_read_lock(); 198 204 list_for_each_entry_rcu(sdev, &svm->devs, list) { 199 205 intel_pasid_tear_down_entry(svm->iommu, sdev->dev, svm->pasid); 200 - intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm); 206 + intel_flush_svm_range_dev(svm, sdev, 0, -1, 0); 201 207 } 202 208 rcu_read_unlock(); 203 209 ··· 419 425 * large and has to be physically contiguous. So it's 420 426 * hard to be as defensive as we might like. */ 421 427 intel_pasid_tear_down_entry(iommu, dev, svm->pasid); 422 - intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm); 428 + intel_flush_svm_range_dev(svm, sdev, 0, -1, 0); 423 429 kfree_rcu(sdev, rcu); 424 430 425 431 if (list_empty(&svm->devs)) {

-3

include/linux/intel-iommu.h

··· 346 346 #define QI_PC_PASID_SEL (QI_PC_TYPE | QI_PC_GRAN(1)) 347 347 348 348 #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK) 349 - #define QI_EIOTLB_GL(gl) (((u64)gl) << 7) 350 349 #define QI_EIOTLB_IH(ih) (((u64)ih) << 6) 351 350 #define QI_EIOTLB_AM(am) (((u64)am)) 352 351 #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32) ··· 377 378 #define QI_RESP_INVALID 0x1 378 379 #define QI_RESP_FAILURE 0xf 379 380 380 - #define QI_GRAN_ALL_ALL 0 381 - #define QI_GRAN_NONG_ALL 1 382 381 #define QI_GRAN_NONG_PASID 2 383 382 #define QI_GRAN_PSI_PASID 3 384 383

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