tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'support-some-features-for-the-hibmcge-driver'

Jijie Shao says:

====================
Support some features for the HIBMCGE driver

v4: https://lore.kernel.org/20250701125446.720176-1-shaojijie@huawei.com
v3: https://lore.kernel.org/20250626020613.637949-1-shaojijie@huawei.com
v2: https://lore.kernel.org/20250623034129.838246-1-shaojijie@huawei.com
v1: https://lore.kernel.org/20250619144423.2661528-1-shaojijie@huawei.com
====================

Link: https://patch.msgid.link/20250702125716.2875169-1-shaojijie@huawei.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski 7725a35e effdbb29

+103
+57
drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c
··· 18 18 #define HBG_ENDIAN_CTRL_LE_DATA_BE 0x0 19 19 #define HBG_PCU_FRAME_LEN_PLUS 4 20 20 21 + #define HBG_FIFO_TX_FULL_THRSLD 0x3F0 22 + #define HBG_FIFO_TX_EMPTY_THRSLD 0x1F0 23 + #define HBG_FIFO_RX_FULL_THRSLD 0x240 24 + #define HBG_FIFO_RX_EMPTY_THRSLD 0x190 25 + #define HBG_CFG_FIFO_FULL_THRSLD 0x10 26 + #define HBG_CFG_FIFO_EMPTY_THRSLD 0x01 27 + 21 28 static bool hbg_hw_spec_is_valid(struct hbg_priv *priv) 22 29 { 23 30 return hbg_reg_read(priv, HBG_REG_SPEC_VALID_ADDR) && ··· 175 168 176 169 void hbg_hw_set_mtu(struct hbg_priv *priv, u16 mtu) 177 170 { 171 + /* burst_len BIT(29) set to 1 can improve the TX performance. 172 + * But packet drop occurs when mtu > 2000. 173 + * So, BIT(29) reset to 0 when mtu > 2000. 174 + */ 175 + u32 burst_len_bit = (mtu > 2000) ? 0 : 1; 178 176 u32 frame_len; 179 177 180 178 frame_len = mtu + VLAN_HLEN * priv->dev_specs.vlan_layers + ··· 187 175 188 176 hbg_hw_set_pcu_max_frame_len(priv, frame_len); 189 177 hbg_hw_set_mac_max_frame_len(priv, frame_len); 178 + 179 + hbg_reg_write_field(priv, HBG_REG_BRUST_LENGTH_ADDR, 180 + HBG_REG_BRUST_LENGTH_B, burst_len_bit); 190 181 } 191 182 192 183 void hbg_hw_mac_enable(struct hbg_priv *priv, u32 enable) ··· 279 264 hbg_reg_write64(priv, HBG_REG_FD_FC_ADDR_LOW_ADDR, mac_addr); 280 265 } 281 266 267 + static void hbg_hw_set_fifo_thrsld(struct hbg_priv *priv, 268 + u32 full, u32 empty, enum hbg_dir dir) 269 + { 270 + u32 value = 0; 271 + 272 + value |= FIELD_PREP(HBG_REG_FIFO_THRSLD_FULL_M, full); 273 + value |= FIELD_PREP(HBG_REG_FIFO_THRSLD_EMPTY_M, empty); 274 + 275 + if (dir & HBG_DIR_TX) 276 + hbg_reg_write(priv, HBG_REG_TX_FIFO_THRSLD_ADDR, value); 277 + 278 + if (dir & HBG_DIR_RX) 279 + hbg_reg_write(priv, HBG_REG_RX_FIFO_THRSLD_ADDR, value); 280 + } 281 + 282 + static void hbg_hw_set_cfg_fifo_thrsld(struct hbg_priv *priv, 283 + u32 full, u32 empty, enum hbg_dir dir) 284 + { 285 + u32 value; 286 + 287 + value = hbg_reg_read(priv, HBG_REG_CFG_FIFO_THRSLD_ADDR); 288 + 289 + if (dir & HBG_DIR_TX) { 290 + value |= FIELD_PREP(HBG_REG_CFG_FIFO_THRSLD_TX_FULL_M, full); 291 + value |= FIELD_PREP(HBG_REG_CFG_FIFO_THRSLD_TX_EMPTY_M, empty); 292 + } 293 + 294 + if (dir & HBG_DIR_RX) { 295 + value |= FIELD_PREP(HBG_REG_CFG_FIFO_THRSLD_RX_FULL_M, full); 296 + value |= FIELD_PREP(HBG_REG_CFG_FIFO_THRSLD_RX_EMPTY_M, empty); 297 + } 298 + 299 + hbg_reg_write(priv, HBG_REG_CFG_FIFO_THRSLD_ADDR, value); 300 + } 301 + 282 302 static void hbg_hw_init_transmit_ctrl(struct hbg_priv *priv) 283 303 { 284 304 u32 ctrl = 0; ··· 374 324 375 325 hbg_hw_init_rx_control(priv); 376 326 hbg_hw_init_transmit_ctrl(priv); 327 + 328 + hbg_hw_set_fifo_thrsld(priv, HBG_FIFO_TX_FULL_THRSLD, 329 + HBG_FIFO_TX_EMPTY_THRSLD, HBG_DIR_TX); 330 + hbg_hw_set_fifo_thrsld(priv, HBG_FIFO_RX_FULL_THRSLD, 331 + HBG_FIFO_RX_EMPTY_THRSLD, HBG_DIR_RX); 332 + hbg_hw_set_cfg_fifo_thrsld(priv, HBG_CFG_FIFO_FULL_THRSLD, 333 + HBG_CFG_FIFO_EMPTY_THRSLD, HBG_DIR_TX_RX); 377 334 return 0; 378 335 }
+38
drivers/net/ethernet/hisilicon/hibmcge/hbg_mdio.c
··· 2 2 // Copyright (c) 2024 Hisilicon Limited. 3 3 4 4 #include <linux/phy.h> 5 + #include <linux/phy_fixed.h> 5 6 #include <linux/rtnetlink.h> 6 7 #include "hbg_common.h" 7 8 #include "hbg_hw.h" ··· 20 19 #define HBG_MDIO_OP_INTERVAL_US (5 * 1000) 21 20 22 21 #define HBG_NP_LINK_FAIL_RETRY_TIMES 5 22 + #define HBG_NO_PHY 0xFF 23 23 24 24 static void hbg_mdio_set_command(struct hbg_mac *mac, u32 cmd) 25 25 { ··· 231 229 phy_stop(priv->mac.phydev); 232 230 } 233 231 232 + static void hbg_fixed_phy_uninit(void *data) 233 + { 234 + fixed_phy_unregister((struct phy_device *)data); 235 + } 236 + 237 + static int hbg_fixed_phy_init(struct hbg_priv *priv) 238 + { 239 + struct fixed_phy_status hbg_fixed_phy_status = { 240 + .link = 1, 241 + .speed = SPEED_1000, 242 + .duplex = DUPLEX_FULL, 243 + .pause = 1, 244 + .asym_pause = 1, 245 + }; 246 + struct device *dev = &priv->pdev->dev; 247 + struct phy_device *phydev; 248 + int ret; 249 + 250 + phydev = fixed_phy_register(&hbg_fixed_phy_status, NULL); 251 + if (IS_ERR(phydev)) { 252 + dev_err_probe(dev, PTR_ERR(phydev), 253 + "failed to register fixed PHY device\n"); 254 + return PTR_ERR(phydev); 255 + } 256 + 257 + ret = devm_add_action_or_reset(dev, hbg_fixed_phy_uninit, phydev); 258 + if (ret) 259 + return ret; 260 + 261 + priv->mac.phydev = phydev; 262 + return hbg_phy_connect(priv); 263 + } 264 + 234 265 int hbg_mdio_init(struct hbg_priv *priv) 235 266 { 236 267 struct device *dev = &priv->pdev->dev; ··· 273 238 int ret; 274 239 275 240 mac->phy_addr = priv->dev_specs.phy_addr; 241 + if (mac->phy_addr == HBG_NO_PHY) 242 + return hbg_fixed_phy_init(priv); 243 + 276 244 mdio_bus = devm_mdiobus_alloc(dev); 277 245 if (!mdio_bus) 278 246 return dev_err_probe(dev, -ENOMEM,
+8
drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h
··· 141 141 /* PCU */ 142 142 #define HBG_REG_TX_FIFO_THRSLD_ADDR (HBG_REG_SGMII_BASE + 0x0420) 143 143 #define HBG_REG_RX_FIFO_THRSLD_ADDR (HBG_REG_SGMII_BASE + 0x0424) 144 + #define HBG_REG_FIFO_THRSLD_FULL_M GENMASK(25, 16) 145 + #define HBG_REG_FIFO_THRSLD_EMPTY_M GENMASK(9, 0) 144 146 #define HBG_REG_CFG_FIFO_THRSLD_ADDR (HBG_REG_SGMII_BASE + 0x0428) 147 + #define HBG_REG_CFG_FIFO_THRSLD_TX_FULL_M GENMASK(31, 24) 148 + #define HBG_REG_CFG_FIFO_THRSLD_TX_EMPTY_M GENMASK(23, 16) 149 + #define HBG_REG_CFG_FIFO_THRSLD_RX_FULL_M GENMASK(15, 8) 150 + #define HBG_REG_CFG_FIFO_THRSLD_RX_EMPTY_M GENMASK(7, 0) 145 151 #define HBG_REG_CF_INTRPT_MSK_ADDR (HBG_REG_SGMII_BASE + 0x042C) 146 152 #define HBG_INT_MSK_WE_ERR_B BIT(31) 147 153 #define HBG_INT_MSK_RBREQ_ERR_B BIT(30) ··· 191 185 #define HBG_REG_TX_CFF_ADDR_2_ADDR (HBG_REG_SGMII_BASE + 0x0490) 192 186 #define HBG_REG_TX_CFF_ADDR_3_ADDR (HBG_REG_SGMII_BASE + 0x0494) 193 187 #define HBG_REG_RX_CFF_ADDR_ADDR (HBG_REG_SGMII_BASE + 0x04A0) 188 + #define HBG_REG_BRUST_LENGTH_ADDR (HBG_REG_SGMII_BASE + 0x04C4) 189 + #define HBG_REG_BRUST_LENGTH_B BIT(29) 194 190 #define HBG_REG_RX_BUF_SIZE_ADDR (HBG_REG_SGMII_BASE + 0x04E4) 195 191 #define HBG_REG_RX_BUF_SIZE_M GENMASK(15, 0) 196 192 #define HBG_REG_BUS_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x04E8)