Merge tag 'gpio-fixes-for-v6.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux

+1 -1

MAINTAINERS

··· 22307 22307 R: Srinivas Neeli <srinivas.neeli@xilinx.com> 22308 22308 R: Michal Simek <michal.simek@xilinx.com> 22309 22309 S: Maintained 22310 - F: Documentation/devicetree/bindings/gpio/gpio-xilinx.txt 22310 + F: Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml 22311 22311 F: Documentation/devicetree/bindings/gpio/gpio-zynq.yaml 22312 22312 F: drivers/gpio/gpio-xilinx.c 22313 22313 F: drivers/gpio/gpio-zynq.c

+7 -3

drivers/gpio/gpio-104-dio-48e.c

··· 164 164 dio48egpio->irq_mask &= ~BIT(0); 165 165 else 166 166 dio48egpio->irq_mask &= ~BIT(1); 167 + gpiochip_disable_irq(chip, offset); 167 168 168 169 if (!dio48egpio->irq_mask) 169 170 /* disable interrupts */ ··· 192 191 iowrite8(0x00, &dio48egpio->reg->enable_interrupt); 193 192 } 194 193 194 + gpiochip_enable_irq(chip, offset); 195 195 if (offset == 19) 196 196 dio48egpio->irq_mask |= BIT(0); 197 197 else ··· 215 213 return 0; 216 214 } 217 215 218 - static struct irq_chip dio48e_irqchip = { 216 + static const struct irq_chip dio48e_irqchip = { 219 217 .name = "104-dio-48e", 220 218 .irq_ack = dio48e_irq_ack, 221 219 .irq_mask = dio48e_irq_mask, 222 220 .irq_unmask = dio48e_irq_unmask, 223 - .irq_set_type = dio48e_irq_set_type 221 + .irq_set_type = dio48e_irq_set_type, 222 + .flags = IRQCHIP_IMMUTABLE, 223 + GPIOCHIP_IRQ_RESOURCE_HELPERS, 224 224 }; 225 225 226 226 static irqreturn_t dio48e_irq_handler(int irq, void *dev_id) ··· 326 322 dio48egpio->chip.set_multiple = dio48e_gpio_set_multiple; 327 323 328 324 girq = &dio48egpio->chip.irq; 329 - girq->chip = &dio48e_irqchip; 325 + gpio_irq_chip_set_chip(girq, &dio48e_irqchip); 330 326 /* This will let us handle the parent IRQ in the driver */ 331 327 girq->parent_handler = NULL; 332 328 girq->num_parents = 0;

+7 -3

drivers/gpio/gpio-104-idi-48.c

··· 113 113 spin_lock_irqsave(&idi48gpio->lock, flags); 114 114 115 115 idi48gpio->irq_mask[boundary] &= ~mask; 116 + gpiochip_disable_irq(chip, offset); 116 117 117 118 /* Exit early if there are still input lines with IRQ unmasked */ 118 119 if (idi48gpio->irq_mask[boundary]) ··· 141 140 142 141 prev_irq_mask = idi48gpio->irq_mask[boundary]; 143 142 143 + gpiochip_enable_irq(chip, offset); 144 144 idi48gpio->irq_mask[boundary] |= mask; 145 145 146 146 /* Exit early if IRQ was already unmasked for this boundary */ ··· 166 164 return 0; 167 165 } 168 166 169 - static struct irq_chip idi_48_irqchip = { 167 + static const struct irq_chip idi_48_irqchip = { 170 168 .name = "104-idi-48", 171 169 .irq_ack = idi_48_irq_ack, 172 170 .irq_mask = idi_48_irq_mask, 173 171 .irq_unmask = idi_48_irq_unmask, 174 - .irq_set_type = idi_48_irq_set_type 172 + .irq_set_type = idi_48_irq_set_type, 173 + .flags = IRQCHIP_IMMUTABLE, 174 + GPIOCHIP_IRQ_RESOURCE_HELPERS, 175 175 }; 176 176 177 177 static irqreturn_t idi_48_irq_handler(int irq, void *dev_id) ··· 271 267 idi48gpio->chip.get_multiple = idi_48_gpio_get_multiple; 272 268 273 269 girq = &idi48gpio->chip.irq; 274 - girq->chip = &idi_48_irqchip; 270 + gpio_irq_chip_set_chip(girq, &idi_48_irqchip); 275 271 /* This will let us handle the parent IRQ in the driver */ 276 272 girq->parent_handler = NULL; 277 273 girq->num_parents = 0;

+11 -7

drivers/gpio/gpio-104-idio-16.c

··· 174 174 { 175 175 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 176 176 struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip); 177 - const unsigned long mask = BIT(irqd_to_hwirq(data)); 177 + const unsigned long offset = irqd_to_hwirq(data); 178 178 unsigned long flags; 179 179 180 - idio16gpio->irq_mask &= ~mask; 180 + idio16gpio->irq_mask &= ~BIT(offset); 181 + gpiochip_disable_irq(chip, offset); 181 182 182 183 if (!idio16gpio->irq_mask) { 183 184 raw_spin_lock_irqsave(&idio16gpio->lock, flags); ··· 193 192 { 194 193 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 195 194 struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip); 196 - const unsigned long mask = BIT(irqd_to_hwirq(data)); 195 + const unsigned long offset = irqd_to_hwirq(data); 197 196 const unsigned long prev_irq_mask = idio16gpio->irq_mask; 198 197 unsigned long flags; 199 198 200 - idio16gpio->irq_mask |= mask; 199 + gpiochip_enable_irq(chip, offset); 200 + idio16gpio->irq_mask |= BIT(offset); 201 201 202 202 if (!prev_irq_mask) { 203 203 raw_spin_lock_irqsave(&idio16gpio->lock, flags); ··· 219 217 return 0; 220 218 } 221 219 222 - static struct irq_chip idio_16_irqchip = { 220 + static const struct irq_chip idio_16_irqchip = { 223 221 .name = "104-idio-16", 224 222 .irq_ack = idio_16_irq_ack, 225 223 .irq_mask = idio_16_irq_mask, 226 224 .irq_unmask = idio_16_irq_unmask, 227 - .irq_set_type = idio_16_irq_set_type 225 + .irq_set_type = idio_16_irq_set_type, 226 + .flags = IRQCHIP_IMMUTABLE, 227 + GPIOCHIP_IRQ_RESOURCE_HELPERS, 228 228 }; 229 229 230 230 static irqreturn_t idio_16_irq_handler(int irq, void *dev_id) ··· 303 299 idio16gpio->out_state = 0xFFFF; 304 300 305 301 girq = &idio16gpio->chip.irq; 306 - girq->chip = &idio_16_irqchip; 302 + gpio_irq_chip_set_chip(girq, &idio_16_irqchip); 307 303 /* This will let us handle the parent IRQ in the driver */ 308 304 girq->parent_handler = NULL; 309 305 girq->num_parents = 0;

+8 -1

drivers/gpio/gpio-mockup.c

··· 373 373 } 374 374 } 375 375 376 + static void gpio_mockup_debugfs_cleanup(void *data) 377 + { 378 + struct gpio_mockup_chip *chip = data; 379 + 380 + debugfs_remove_recursive(chip->dbg_dir); 381 + } 382 + 376 383 static void gpio_mockup_dispose_mappings(void *data) 377 384 { 378 385 struct gpio_mockup_chip *chip = data; ··· 462 455 463 456 gpio_mockup_debugfs_setup(dev, chip); 464 457 465 - return 0; 458 + return devm_add_action_or_reset(dev, gpio_mockup_debugfs_cleanup, chip); 466 459 } 467 460 468 461 static const struct of_device_id gpio_mockup_of_match[] = {

+7 -1

drivers/gpio/gpio-pca953x.c

··· 1175 1175 { 1176 1176 struct pca953x_chip *chip = dev_get_drvdata(dev); 1177 1177 1178 + mutex_lock(&chip->i2c_lock); 1178 1179 regcache_cache_only(chip->regmap, true); 1180 + mutex_unlock(&chip->i2c_lock); 1179 1181 1180 1182 if (atomic_read(&chip->wakeup_path)) 1181 1183 device_set_wakeup_path(dev); ··· 1200 1198 } 1201 1199 } 1202 1200 1201 + mutex_lock(&chip->i2c_lock); 1203 1202 regcache_cache_only(chip->regmap, false); 1204 1203 regcache_mark_dirty(chip->regmap); 1205 1204 ret = pca953x_regcache_sync(dev); 1206 - if (ret) 1205 + if (ret) { 1206 + mutex_unlock(&chip->i2c_lock); 1207 1207 return ret; 1208 + } 1208 1209 1209 1210 ret = regcache_sync(chip->regmap); 1211 + mutex_unlock(&chip->i2c_lock); 1210 1212 if (ret) { 1211 1213 dev_err(dev, "Failed to restore register map: %d\n", ret); 1212 1214 return ret;

+2 -9

drivers/gpio/gpio-pxa.c

··· 661 661 if (IS_ERR(gpio_reg_base)) 662 662 return PTR_ERR(gpio_reg_base); 663 663 664 - clk = clk_get(&pdev->dev, NULL); 664 + clk = devm_clk_get_enabled(&pdev->dev, NULL); 665 665 if (IS_ERR(clk)) { 666 666 dev_err(&pdev->dev, "Error %ld to get gpio clock\n", 667 667 PTR_ERR(clk)); 668 668 return PTR_ERR(clk); 669 669 } 670 - ret = clk_prepare_enable(clk); 671 - if (ret) { 672 - clk_put(clk); 673 - return ret; 674 - } 675 670 676 671 /* Initialize GPIO chips */ 677 672 ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, gpio_reg_base); 678 - if (ret) { 679 - clk_put(clk); 673 + if (ret) 680 674 return ret; 681 - } 682 675 683 676 /* clear all GPIO edge detects */ 684 677 for_each_gpio_bank(gpio, c, pchip) {

+85 -81

drivers/gpio/gpio-realtek-otto.c

··· 46 46 * @lock: Lock for accessing the IRQ registers and values 47 47 * @intr_mask: Mask for interrupts lines 48 48 * @intr_type: Interrupt type selection 49 + * @bank_read: Read a bank setting as a single 32-bit value 50 + * @bank_write: Write a bank setting as a single 32-bit value 51 + * @imr_line_pos: Bit shift of an IRQ line's IMR value. 52 + * 53 + * The DIR, DATA, and ISR registers consist of four 8-bit port values, packed 54 + * into a single 32-bit register. Use @bank_read (@bank_write) to get (assign) 55 + * a value from (to) these registers. The IMR register consists of four 16-bit 56 + * port values, packed into two 32-bit registers. Use @imr_line_pos to get the 57 + * bit shift of the 2-bit field for a line's IMR settings. Shifts larger than 58 + * 32 overflow into the second register. 49 59 * 50 60 * Because the interrupt mask register (IMR) combines the function of IRQ type 51 61 * selection and masking, two extra values are stored. @intr_mask is used to 52 - * mask/unmask the interrupts for a GPIO port, and @intr_type is used to store 62 + * mask/unmask the interrupts for a GPIO line, and @intr_type is used to store 53 63 * the selected interrupt types. The logical AND of these values is written to 54 64 * IMR on changes. 55 65 */ ··· 69 59 void __iomem *cpumask_base; 70 60 struct cpumask cpu_irq_maskable; 71 61 raw_spinlock_t lock; 72 - u16 intr_mask[REALTEK_GPIO_PORTS_PER_BANK]; 73 - u16 intr_type[REALTEK_GPIO_PORTS_PER_BANK]; 74 - unsigned int (*port_offset_u8)(unsigned int port); 75 - unsigned int (*port_offset_u16)(unsigned int port); 62 + u8 intr_mask[REALTEK_GPIO_MAX]; 63 + u8 intr_type[REALTEK_GPIO_MAX]; 64 + u32 (*bank_read)(void __iomem *reg); 65 + void (*bank_write)(void __iomem *reg, u32 value); 66 + unsigned int (*line_imr_pos)(unsigned int line); 76 67 }; 77 68 78 69 /* Expand with more flags as devices with other quirks are added */ ··· 112 101 * port. The two interrupt mask registers store two bits per GPIO, so use u16 113 102 * values. 114 103 */ 115 - static unsigned int realtek_gpio_port_offset_u8(unsigned int port) 104 + static u32 realtek_gpio_bank_read_swapped(void __iomem *reg) 116 105 { 117 - return port; 106 + return ioread32be(reg); 118 107 } 119 108 120 - static unsigned int realtek_gpio_port_offset_u16(unsigned int port) 109 + static void realtek_gpio_bank_write_swapped(void __iomem *reg, u32 value) 121 110 { 122 - return 2 * port; 111 + iowrite32be(value, reg); 112 + } 113 + 114 + static unsigned int realtek_gpio_line_imr_pos_swapped(unsigned int line) 115 + { 116 + unsigned int port_pin = line % 8; 117 + unsigned int port = line / 8; 118 + 119 + return 2 * (8 * (port ^ 1) + port_pin); 123 120 } 124 121 125 122 /* ··· 138 119 * per GPIO, so use u16 values. The first register contains ports 1 and 0, the 139 120 * second ports 3 and 2. 140 121 */ 141 - static unsigned int realtek_gpio_port_offset_u8_rev(unsigned int port) 122 + static u32 realtek_gpio_bank_read(void __iomem *reg) 142 123 { 143 - return 3 - port; 124 + return ioread32(reg); 144 125 } 145 126 146 - static unsigned int realtek_gpio_port_offset_u16_rev(unsigned int port) 127 + static void realtek_gpio_bank_write(void __iomem *reg, u32 value) 147 128 { 148 - return 2 * (port ^ 1); 129 + iowrite32(value, reg); 149 130 } 150 131 151 - static void realtek_gpio_write_imr(struct realtek_gpio_ctrl *ctrl, 152 - unsigned int port, u16 irq_type, u16 irq_mask) 132 + static unsigned int realtek_gpio_line_imr_pos(unsigned int line) 153 133 { 154 - iowrite16(irq_type & irq_mask, 155 - ctrl->base + REALTEK_GPIO_REG_IMR + ctrl->port_offset_u16(port)); 134 + return 2 * line; 156 135 } 157 136 158 - static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl, 159 - unsigned int port, u8 mask) 137 + static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl, u32 mask) 160 138 { 161 - iowrite8(mask, ctrl->base + REALTEK_GPIO_REG_ISR + ctrl->port_offset_u8(port)); 139 + ctrl->bank_write(ctrl->base + REALTEK_GPIO_REG_ISR, mask); 162 140 } 163 141 164 - static u8 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl, unsigned int port) 142 + static u32 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl) 165 143 { 166 - return ioread8(ctrl->base + REALTEK_GPIO_REG_ISR + ctrl->port_offset_u8(port)); 144 + return ctrl->bank_read(ctrl->base + REALTEK_GPIO_REG_ISR); 167 145 } 168 146 169 - /* Set the rising and falling edge mask bits for a GPIO port pin */ 170 - static u16 realtek_gpio_imr_bits(unsigned int pin, u16 value) 147 + /* Set the rising and falling edge mask bits for a GPIO pin */ 148 + static void realtek_gpio_update_line_imr(struct realtek_gpio_ctrl *ctrl, unsigned int line) 171 149 { 172 - return (value & REALTEK_GPIO_IMR_LINE_MASK) << 2 * pin; 150 + void __iomem *reg = ctrl->base + REALTEK_GPIO_REG_IMR; 151 + unsigned int line_shift = ctrl->line_imr_pos(line); 152 + unsigned int shift = line_shift % 32; 153 + u32 irq_type = ctrl->intr_type[line]; 154 + u32 irq_mask = ctrl->intr_mask[line]; 155 + u32 reg_val; 156 + 157 + reg += 4 * (line_shift / 32); 158 + reg_val = ioread32(reg); 159 + reg_val &= ~(REALTEK_GPIO_IMR_LINE_MASK << shift); 160 + reg_val |= (irq_type & irq_mask & REALTEK_GPIO_IMR_LINE_MASK) << shift; 161 + iowrite32(reg_val, reg); 173 162 } 174 163 175 164 static void realtek_gpio_irq_ack(struct irq_data *data) 176 165 { 177 166 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 178 167 irq_hw_number_t line = irqd_to_hwirq(data); 179 - unsigned int port = line / 8; 180 - unsigned int port_pin = line % 8; 181 168 182 - realtek_gpio_clear_isr(ctrl, port, BIT(port_pin)); 169 + realtek_gpio_clear_isr(ctrl, BIT(line)); 183 170 } 184 171 185 172 static void realtek_gpio_irq_unmask(struct irq_data *data) 186 173 { 187 174 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 188 175 unsigned int line = irqd_to_hwirq(data); 189 - unsigned int port = line / 8; 190 - unsigned int port_pin = line % 8; 191 176 unsigned long flags; 192 - u16 m; 193 177 194 178 gpiochip_enable_irq(&ctrl->gc, line); 195 179 196 180 raw_spin_lock_irqsave(&ctrl->lock, flags); 197 - m = ctrl->intr_mask[port]; 198 - m |= realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK); 199 - ctrl->intr_mask[port] = m; 200 - realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m); 181 + ctrl->intr_mask[line] = REALTEK_GPIO_IMR_LINE_MASK; 182 + realtek_gpio_update_line_imr(ctrl, line); 201 183 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 202 184 } 203 185 ··· 206 186 { 207 187 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 208 188 unsigned int line = irqd_to_hwirq(data); 209 - unsigned int port = line / 8; 210 - unsigned int port_pin = line % 8; 211 189 unsigned long flags; 212 - u16 m; 213 190 214 191 raw_spin_lock_irqsave(&ctrl->lock, flags); 215 - m = ctrl->intr_mask[port]; 216 - m &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK); 217 - ctrl->intr_mask[port] = m; 218 - realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m); 192 + ctrl->intr_mask[line] = 0; 193 + realtek_gpio_update_line_imr(ctrl, line); 219 194 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 220 195 221 196 gpiochip_disable_irq(&ctrl->gc, line); ··· 220 205 { 221 206 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 222 207 unsigned int line = irqd_to_hwirq(data); 223 - unsigned int port = line / 8; 224 - unsigned int port_pin = line % 8; 225 208 unsigned long flags; 226 - u16 type, t; 209 + u8 type; 227 210 228 211 switch (flow_type & IRQ_TYPE_SENSE_MASK) { 229 212 case IRQ_TYPE_EDGE_FALLING: ··· 240 227 irq_set_handler_locked(data, handle_edge_irq); 241 228 242 229 raw_spin_lock_irqsave(&ctrl->lock, flags); 243 - t = ctrl->intr_type[port]; 244 - t &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK); 245 - t |= realtek_gpio_imr_bits(port_pin, type); 246 - ctrl->intr_type[port] = t; 247 - realtek_gpio_write_imr(ctrl, port, t, ctrl->intr_mask[port]); 230 + ctrl->intr_type[line] = type; 231 + realtek_gpio_update_line_imr(ctrl, line); 248 232 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 249 233 250 234 return 0; ··· 252 242 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 253 243 struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc); 254 244 struct irq_chip *irq_chip = irq_desc_get_chip(desc); 255 - unsigned int lines_done; 256 - unsigned int port_pin_count; 257 245 unsigned long status; 258 246 int offset; 259 247 260 248 chained_irq_enter(irq_chip, desc); 261 249 262 - for (lines_done = 0; lines_done < gc->ngpio; lines_done += 8) { 263 - status = realtek_gpio_read_isr(ctrl, lines_done / 8); 264 - port_pin_count = min(gc->ngpio - lines_done, 8U); 265 - for_each_set_bit(offset, &status, port_pin_count) 266 - generic_handle_domain_irq(gc->irq.domain, offset + lines_done); 267 - } 250 + status = realtek_gpio_read_isr(ctrl); 251 + for_each_set_bit(offset, &status, gc->ngpio) 252 + generic_handle_domain_irq(gc->irq.domain, offset); 268 253 269 254 chained_irq_exit(irq_chip, desc); 270 255 } 271 256 272 - static inline void __iomem *realtek_gpio_irq_cpu_mask(struct realtek_gpio_ctrl *ctrl, 273 - unsigned int port, int cpu) 257 + static inline void __iomem *realtek_gpio_irq_cpu_mask(struct realtek_gpio_ctrl *ctrl, int cpu) 274 258 { 275 - return ctrl->cpumask_base + ctrl->port_offset_u8(port) + 276 - REALTEK_GPIO_PORTS_PER_BANK * cpu; 259 + return ctrl->cpumask_base + REALTEK_GPIO_PORTS_PER_BANK * cpu; 277 260 } 278 261 279 262 static int realtek_gpio_irq_set_affinity(struct irq_data *data, ··· 274 271 { 275 272 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 276 273 unsigned int line = irqd_to_hwirq(data); 277 - unsigned int port = line / 8; 278 - unsigned int port_pin = line % 8; 279 274 void __iomem *irq_cpu_mask; 280 275 unsigned long flags; 281 276 int cpu; 282 - u8 v; 277 + u32 v; 283 278 284 279 if (!ctrl->cpumask_base) 285 280 return -ENXIO; ··· 285 284 raw_spin_lock_irqsave(&ctrl->lock, flags); 286 285 287 286 for_each_cpu(cpu, &ctrl->cpu_irq_maskable) { 288 - irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, port, cpu); 289 - v = ioread8(irq_cpu_mask); 287 + irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, cpu); 288 + v = ctrl->bank_read(irq_cpu_mask); 290 289 291 290 if (cpumask_test_cpu(cpu, dest)) 292 - v |= BIT(port_pin); 291 + v |= BIT(line); 293 292 else 294 - v &= ~BIT(port_pin); 293 + v &= ~BIT(line); 295 294 296 - iowrite8(v, irq_cpu_mask); 295 + ctrl->bank_write(irq_cpu_mask, v); 297 296 } 298 297 299 298 raw_spin_unlock_irqrestore(&ctrl->lock, flags); ··· 306 305 static int realtek_gpio_irq_init(struct gpio_chip *gc) 307 306 { 308 307 struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc); 309 - unsigned int port; 308 + u32 mask_all = GENMASK(gc->ngpio - 1, 0); 309 + unsigned int line; 310 310 int cpu; 311 311 312 - for (port = 0; (port * 8) < gc->ngpio; port++) { 313 - realtek_gpio_write_imr(ctrl, port, 0, 0); 314 - realtek_gpio_clear_isr(ctrl, port, GENMASK(7, 0)); 312 + for (line = 0; line < gc->ngpio; line++) 313 + realtek_gpio_update_line_imr(ctrl, line); 315 314 316 - for_each_cpu(cpu, &ctrl->cpu_irq_maskable) 317 - iowrite8(GENMASK(7, 0), realtek_gpio_irq_cpu_mask(ctrl, port, cpu)); 318 - } 315 + realtek_gpio_clear_isr(ctrl, mask_all); 316 + 317 + for_each_cpu(cpu, &ctrl->cpu_irq_maskable) 318 + ctrl->bank_write(realtek_gpio_irq_cpu_mask(ctrl, cpu), mask_all); 319 319 320 320 return 0; 321 321 } ··· 389 387 390 388 if (dev_flags & GPIO_PORTS_REVERSED) { 391 389 bgpio_flags = 0; 392 - ctrl->port_offset_u8 = realtek_gpio_port_offset_u8_rev; 393 - ctrl->port_offset_u16 = realtek_gpio_port_offset_u16_rev; 390 + ctrl->bank_read = realtek_gpio_bank_read; 391 + ctrl->bank_write = realtek_gpio_bank_write; 392 + ctrl->line_imr_pos = realtek_gpio_line_imr_pos; 394 393 } else { 395 394 bgpio_flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER; 396 - ctrl->port_offset_u8 = realtek_gpio_port_offset_u8; 397 - ctrl->port_offset_u16 = realtek_gpio_port_offset_u16; 395 + ctrl->bank_read = realtek_gpio_bank_read_swapped; 396 + ctrl->bank_write = realtek_gpio_bank_write_swapped; 397 + ctrl->line_imr_pos = realtek_gpio_line_imr_pos_swapped; 398 398 } 399 399 400 400 err = bgpio_init(&ctrl->gc, dev, 4,

+7 -3

drivers/gpio/gpio-ws16c48.c

··· 265 265 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 266 266 267 267 ws16c48gpio->irq_mask &= ~mask; 268 + gpiochip_disable_irq(chip, offset); 268 269 port_state = ws16c48gpio->irq_mask >> (8 * port); 269 270 270 271 /* Select Register Page 2; Unlock all I/O ports */ ··· 296 295 297 296 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 298 297 298 + gpiochip_enable_irq(chip, offset); 299 299 ws16c48gpio->irq_mask |= mask; 300 300 port_state = ws16c48gpio->irq_mask >> (8 * port); 301 301 ··· 358 356 return 0; 359 357 } 360 358 361 - static struct irq_chip ws16c48_irqchip = { 359 + static const struct irq_chip ws16c48_irqchip = { 362 360 .name = "ws16c48", 363 361 .irq_ack = ws16c48_irq_ack, 364 362 .irq_mask = ws16c48_irq_mask, 365 363 .irq_unmask = ws16c48_irq_unmask, 366 - .irq_set_type = ws16c48_irq_set_type 364 + .irq_set_type = ws16c48_irq_set_type, 365 + .flags = IRQCHIP_IMMUTABLE, 366 + GPIOCHIP_IRQ_RESOURCE_HELPERS, 367 367 }; 368 368 369 369 static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id) ··· 467 463 ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple; 468 464 469 465 girq = &ws16c48gpio->chip.irq; 470 - girq->chip = &ws16c48_irqchip; 466 + gpio_irq_chip_set_chip(girq, &ws16c48_irqchip); 471 467 /* This will let us handle the parent IRQ in the driver */ 472 468 girq->parent_handler = NULL; 473 469 girq->num_parents = 0;

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