Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
gpu: nova-core: sequencer: Implement core resume operation
Implement core resume operation. This is the last step of the sequencer
resulting in resume of the GSP and proceeding to INIT_DONE stage of GSP
boot.
Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Message-ID: <20251114195552.739371-12-joelagnelf@nvidia.com>
authored by
Joel Fernandes
and committed by
Alexandre Courbot
77410985
9641f052
+42
-3
-1
drivers/gpu/nova-core/falcon/gsp.rs
-1
drivers/gpu/nova-core/falcon/gsp.rs
···
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}
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/// Checks if GSP reload/resume has completed during the boot process.
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-
#[expect(dead_code)]
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pub(crate) fn check_reload_completed(&self, bar: &Bar0, timeout: Delta) -> Result<bool> {
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read_poll_timeout(
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|| Ok(regs::NV_PGC6_BSI_SECURE_SCRATCH_14::read(bar)),
+42
-2
drivers/gpu/nova-core/gsp/sequencer.rs
+42
-2
drivers/gpu/nova-core/gsp/sequencer.rs
···
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CoreReset,
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CoreStart,
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CoreWaitForHalt,
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CoreResume,
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}
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impl GspSeqCmd {
···
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fw::SeqBufOpcode::CoreReset => (GspSeqCmd::CoreReset, opcode_size),
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fw::SeqBufOpcode::CoreStart => (GspSeqCmd::CoreStart, opcode_size),
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fw::SeqBufOpcode::CoreWaitForHalt => (GspSeqCmd::CoreWaitForHalt, opcode_size),
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-
_ => return Err(EINVAL),
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+
fw::SeqBufOpcode::CoreResume => (GspSeqCmd::CoreResume, opcode_size),
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};
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if data.len() < size {
···
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}
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/// GSP Sequencer for executing firmware commands during boot.
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#[expect(dead_code)]
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pub(crate) struct GspSequencer<'a> {
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/// Sequencer information with command data.
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seq_info: GspSequence,
···
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}
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GspSeqCmd::CoreWaitForHalt => {
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seq.gsp_falcon.wait_till_halted(seq.bar)?;
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+
Ok(())
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}
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GspSeqCmd::CoreResume => {
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// At this point, 'SEC2-RTOS' has been loaded into SEC2 by the sequencer
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// but neither SEC2-RTOS nor GSP-RM is running yet. This part of the
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// sequencer will start both.
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+
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// Reset the GSP to prepare it for resuming.
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seq.gsp_falcon.reset(seq.bar)?;
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+
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// Write the libOS DMA handle to GSP mailboxes.
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seq.gsp_falcon.write_mailboxes(
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seq.bar,
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Some(seq.libos_dma_handle as u32),
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Some((seq.libos_dma_handle >> 32) as u32),
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);
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+
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// Start the SEC2 falcon which will trigger GSP-RM to resume on the GSP.
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seq.sec2_falcon.start(seq.bar)?;
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+
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// Poll until GSP-RM reload/resume has completed (up to 2 seconds).
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seq.gsp_falcon
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.check_reload_completed(seq.bar, Delta::from_secs(2))?;
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+
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// Verify SEC2 completed successfully by checking its mailbox for errors.
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let mbox0 = seq.sec2_falcon.read_mailbox0(seq.bar);
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if mbox0 != 0 {
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dev_err!(seq.dev, "Sequencer: sec2 errors: {:?}\n", mbox0);
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return Err(EIO);
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}
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+
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// Configure GSP with the bootloader version.
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seq.gsp_falcon
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.write_os_version(seq.bar, seq.bootloader_app_version);
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+
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// Verify the GSP's RISC-V core is active indicating successful GSP boot.
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if !seq.gsp_falcon.is_riscv_active(seq.bar) {
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dev_err!(seq.dev, "Sequencer: RISC-V core is not active\n");
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return Err(EIO);
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}
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Ok(())
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}
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}