Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
iommu/amd: Add support for nested domain allocation
The nested domain is allocated with IOMMU_DOMAIN_NESTED type to store
stage-1 translation (i.e. GVA->GPA). This includes the GCR3 root pointer
table along with guest page tables. The struct iommu_hwpt_amd_guest
contains this information, and is passed from user-space as a parameter
of the struct iommu_ops.domain_alloc_nested().
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
authored by
Suravee Suthikulpanit
and committed by
Joerg Roedel
774180a7
e113a725
+129
-1
+1
-1
drivers/iommu/amd/Makefile
+1
-1
drivers/iommu/amd/Makefile
+4
drivers/iommu/amd/amd_iommu.h
+4
drivers/iommu/amd/amd_iommu.h
+14
drivers/iommu/amd/amd_iommu_types.h
+14
drivers/iommu/amd/amd_iommu_types.h
···
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#include <linux/irqreturn.h>
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#include <linux/generic_pt/iommu.h>
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#include <uapi/linux/iommufd.h>
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+
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/*
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* Maximum number of IOMMUs supported
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*/
···
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#define DTE_FLAG_V BIT_ULL(0)
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#define DTE_FLAG_TV BIT_ULL(1)
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#define DTE_FLAG_HAD (3ULL << 7)
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#define DTE_MODE_MASK GENMASK_ULL(11, 9)
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#define DTE_HOST_TRP GENMASK_ULL(51, 12)
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#define DTE_FLAG_GIOV BIT_ULL(54)
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#define DTE_FLAG_GV BIT_ULL(55)
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#define DTE_GLX GENMASK_ULL(57, 56)
···
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struct amd_iommu_viommu {
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struct iommufd_viommu core;
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struct protection_domain *parent; /* nest parent domain for this viommu */
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};
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/*
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* Nested domain is specifically used for nested translation
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*/
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struct nested_domain {
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struct iommu_domain domain; /* generic domain handle used by iommu core code */
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u16 gdom_id; /* domain ID from gDTE */
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struct iommu_hwpt_amd_guest gdte; /* Guest vIOMMU DTE */
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struct amd_iommu_viommu *viommu; /* AMD hw-viommu this nested domain belong to */
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};
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/*
+110
drivers/iommu/amd/nested.c
+110
drivers/iommu/amd/nested.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2025 Advanced Micro Devices, Inc.
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*/
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#define dev_fmt(fmt) "AMD-Vi: " fmt
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#include <linux/iommu.h>
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#include <uapi/linux/iommufd.h>
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+
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#include "amd_iommu.h"
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+
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static const struct iommu_domain_ops nested_domain_ops;
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static inline struct nested_domain *to_ndomain(struct iommu_domain *dom)
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{
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return container_of(dom, struct nested_domain, domain);
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}
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+
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/*
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* Validate guest DTE to make sure that configuration for host (v1)
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* and guest (v2) page tables are valid when allocating nested domain.
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*/
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static int validate_gdte_nested(struct iommu_hwpt_amd_guest *gdte)
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{
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u32 gpt_level = FIELD_GET(DTE_GPT_LEVEL_MASK, gdte->dte[2]);
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+
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/* Must be zero: Mode, Host-TPR */
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if (FIELD_GET(DTE_MODE_MASK, gdte->dte[0]) != 0 ||
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FIELD_GET(DTE_HOST_TRP, gdte->dte[0]) != 0)
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return -EINVAL;
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+
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/* GCR3 TRP must be non-zero if V, GV is set */
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if (FIELD_GET(DTE_FLAG_V, gdte->dte[0]) == 1 &&
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FIELD_GET(DTE_FLAG_GV, gdte->dte[0]) == 1 &&
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FIELD_GET(DTE_GCR3_14_12, gdte->dte[0]) == 0 &&
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FIELD_GET(DTE_GCR3_30_15, gdte->dte[1]) == 0 &&
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FIELD_GET(DTE_GCR3_51_31, gdte->dte[1]) == 0)
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return -EINVAL;
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/* Valid Guest Paging Mode values are 0 and 1 */
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if (gpt_level != GUEST_PGTABLE_4_LEVEL &&
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gpt_level != GUEST_PGTABLE_5_LEVEL)
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return -EINVAL;
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/* GLX = 3 is reserved */
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if (FIELD_GET(DTE_GLX, gdte->dte[0]) == 3)
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return -EINVAL;
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/*
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* We need to check host capability before setting
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* the Guest Paging Mode
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*/
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if (gpt_level == GUEST_PGTABLE_5_LEVEL &&
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amd_iommu_gpt_level < PAGE_MODE_5_LEVEL)
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return -EOPNOTSUPP;
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return 0;
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}
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+
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/*
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* This function is assigned to struct iommufd_viommu_ops.alloc_domain_nested()
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* during the call to struct iommu_ops.viommu_init().
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*/
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struct iommu_domain *
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amd_iommu_alloc_domain_nested(struct iommufd_viommu *viommu, u32 flags,
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const struct iommu_user_data *user_data)
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{
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int ret;
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struct nested_domain *ndom;
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struct amd_iommu_viommu *aviommu = container_of(viommu, struct amd_iommu_viommu, core);
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if (user_data->type != IOMMU_HWPT_DATA_AMD_GUEST)
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return ERR_PTR(-EOPNOTSUPP);
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ndom = kzalloc(sizeof(*ndom), GFP_KERNEL);
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if (!ndom)
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return ERR_PTR(-ENOMEM);
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ret = iommu_copy_struct_from_user(&ndom->gdte, user_data,
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IOMMU_HWPT_DATA_AMD_GUEST,
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dte);
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if (ret)
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goto out_err;
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ret = validate_gdte_nested(&ndom->gdte);
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if (ret)
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goto out_err;
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ndom->gdom_id = FIELD_GET(DTE_DOMID_MASK, ndom->gdte.dte[1]);
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ndom->domain.ops = &nested_domain_ops;
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ndom->domain.type = IOMMU_DOMAIN_NESTED;
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ndom->viommu = aviommu;
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return &ndom->domain;
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out_err:
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kfree(ndom);
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return ERR_PTR(ret);
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}
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static void nested_domain_free(struct iommu_domain *dom)
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{
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struct nested_domain *ndom = to_ndomain(dom);
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kfree(ndom);
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}
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static const struct iommu_domain_ops nested_domain_ops = {
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.free = nested_domain_free,
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};